JPWO2014058069A1 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Abstract

Furthermore, the present invention provides a semiconductor light emitting device capable of improving the light extraction efficiency and a method for manufacturing the same. An optical wavelength of light emitted from the light emitting layer on the surface of the sapphire substrate, wherein the semiconductor light emitting device includes a semiconductor stacked portion including a light emitting layer and a sapphire substrate on which the semiconductor stacked portion is formed. Concave portions or convex portions are formed with a period that is larger and smaller than the coherent length, include a dielectric multilayer film, and have a reflective portion having a reflectance of 90% or more in the wavelength region of light emitted from the light emitting layer.

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  High-intensity blue, green, white, and other light-emitting diodes have already been put into practical use through the accumulation of basic technologies such as low-temperature deposition buffer layer technology, p-type conductivity control, n-type conductivity control, and a method for producing high-efficiency light-emitting layers. ing. Currently, in the light emitting diode, the refractive index of the semiconductor is larger than the refractive index of the substrate, air, etc., and a large part of the light emitted from the light emitting layer cannot be extracted outside the light emitting diode by total reflection or Fresnel reflection. Improvement of light extraction efficiency is a problem.

  In order to solve this problem, a structure has been proposed in which a semiconductor surface is subjected to uneven processing with a period of several microns (for example, see Non-Patent Document 1). By providing a concavo-convex structure on the light extraction side of the semiconductor surface, total reflection disappears due to the effect of light scattering, a transmittance of about 50% can be obtained over a relatively wide radiation angle, and the light extraction efficiency can be up to about 50%. Can be improved.

  Furthermore, it has also been proposed to improve the light extraction efficiency by reducing the period of the concavo-convex structure to twice or less the optical wavelength of the light emitting diode (see, for example, Patent Document 1). In this case, the light extraction mechanism is different from the concavo-convex structure having a period of several microns, the wave nature of light becomes obvious, the boundary of the refractive index disappears, and Fresnel reflection is suppressed. Such a structure is called a photonic crystal or a moth-eye structure, and the light extraction efficiency can be improved up to about 50%.

  Furthermore, the inventors of the present application have proposed that the period of the concavo-convex structure be made smaller than the coherent length of light and that light be extracted using the diffraction action (see, for example, Patent Document 2). In Patent Document 2, a group III nitride semiconductor formed on the surface of a sapphire substrate and including a light-emitting layer and light emitted from the light-emitting layer formed on the surface side of the sapphire substrate are incident and are larger than the optical wavelength of the light. A diffractive surface in which concave or convex portions are formed with a period smaller than the coherent length of light, and an Al reflective film that is formed on the back side of the substrate and reflects light diffracted by the diffractive surface and re-enters the diffractive surface. A semiconductor light emitting device comprising is described. According to this semiconductor light emitting device, the light transmitted by the diffractive action is re-incident on the diffractive surface, and the light is transmitted again using the diffractive action on the diffractive surface, thereby extracting the light in a plurality of modes to the outside of the device. Can do.

JP 2005-354020 A International Publication No. 2011/0276779

Japanese Journal of Applied Physics Vol.41, 2004, L1431

  The inventors of the present application sought to further improve the light extraction efficiency.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor light emitting device capable of further improving the light extraction efficiency and a method for manufacturing the same.

  In order to achieve the above object, according to the present invention, a semiconductor multilayer part including a light emitting layer and a sapphire substrate on which the semiconductor multilayer part is formed are provided, and emitted from the light emitting layer on the surface of the sapphire substrate. The surface of the sapphire substrate is formed with recesses or projections with a period that is greater than the optical wavelength of the light emitted from the light emitting layer and less than the coherent length. A reflection part that reflects light transmitted through the light source and re-enters the surface is formed. The reflection part includes a dielectric multilayer film, and has a reflectance of 90% or more in a wavelength region of light emitted from the light emitting layer. A semiconductor light emitting device is provided.

  In the semiconductor light emitting device, the dielectric multilayer film formed on the back surface of the sapphire substrate may be covered with a metal layer.

  In the semiconductor light emitting device, the metal layer may be made of Al.

  In the semiconductor light emitting device, the height of the concave portion or the convex portion may be 300 nm or more.

  In the present invention, in manufacturing the semiconductor light emitting device, a mask layer forming step of forming a mask layer on the surface of the sapphire substrate, a resist film forming step of forming a resist film on the mask layer, and the resist A pattern forming process for forming a predetermined pattern on the film, and Ar gas plasma is induced to the sapphire substrate side by applying a predetermined bias output, and the resist film is altered by the Ar gas plasma to perform etching selection. A resist alteration process for increasing the ratio, and a plasma of Ar gas is applied to the sapphire substrate side by applying a bias output higher than the bias output of the resist alteration process to mask the resist film having a high etching selectivity. As an etching process of the mask layer for etching the mask layer, and before the etching Etching the substrate using the mask layer as a mask to etch the sapphire substrate to form the concave portion or the convex portion, and forming the semiconductor stacked portion on the etched surface of the sapphire substrate And a multilayer film forming step of forming the dielectric multilayer film on the back surface of the sapphire substrate.

  In the method for manufacturing a semiconductor light emitting device, the sapphire substrate may be etched in the state in which the resist film remains on the mask layer in the substrate etching step.

In the manufacturing method of the semiconductor light-emitting device, wherein the mask layer, and the SiO ₂ layer on the sapphire substrate, anda Ni layer on the SiO ₂ layer, by an etching process of the substrate, the SiO ₂ layer The sapphire substrate may be etched in a state where the Ni layer and the resist film are laminated.

  Furthermore, in the present invention, a semiconductor laminated portion including a light emitting layer and a sapphire substrate on which the semiconductor laminated portion is formed are provided, and the surface of the sapphire substrate has an optical element for light emitted from the light emitting layer. A semiconductor light emitting device having a reflective portion having a concave portion or a convex portion formed with a period larger than the wavelength and smaller than the coherent length, including a dielectric multilayer film, and having a reflectance of 90% or more in a wavelength region of light emitted from the light emitting layer Is provided.

  In the semiconductor light emitting device, the semiconductor light emitting device is of a flip chip type, has a transparent diffusion electrode formed on the semiconductor stacked portion, and the reflection portion is formed on a part of the diffusion electrode. You may have a dielectric multilayer film and the metal electrode which coat | covers the said dielectric multilayer film, and contacts the said diffusion electrode in the part in which the said dielectric multilayer film is not formed.

  In the semiconductor light emitting device, a plurality of via holes may be formed in the dielectric multilayer film at a predetermined interval, and the metal electrode may be in contact with the diffusion electrode through the via hole.

  In the semiconductor light emitting device, the predetermined interval between the plurality of via holes may be 20 μm or more and 40 μm or less.

  In the semiconductor light emitting device, the contact resistance of the diffusion electrode with the semiconductor stacked portion is relatively higher immediately below the formation region of the dielectric multilayer film than immediately below the contact portion with the metal electrode. It may be.

  In the semiconductor light emitting device, the diffusion electrode may be made of a conductive oxide.

  In the semiconductor light emitting device, the metal electrode may be made of an Ag—Pd—Cu alloy material.

  Furthermore, in the present invention, in manufacturing the semiconductor light emitting device, the dielectric multilayer film having the plurality of via holes is formed on the diffusion electrode, and the diffusion electrode is exposed using the dielectric multilayer film as a mask. A method of manufacturing a semiconductor light emitting device is provided in which the contact resistance between the diffusion electrode and the semiconductor laminated portion is changed by altering the portion.

  In the method for manufacturing the semiconductor light emitting device, the metal electrode is formed on the dielectric multilayer film by a sputtering method, and a material of the metal electrode that is made plasma at the time of sputtering is applied to the diffusion electrode through the via hole. You may make it resistance.

  According to the semiconductor light emitting device of the present invention, the light extraction efficiency can be further improved.

FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device showing a first embodiment of the present invention. 2A and 2B are explanatory diagrams showing the diffraction action of light at the interface having different refractive indexes, where FIG. 2A shows a state of reflection at the interface, and FIG. 2B shows a state of transmission through the interface. FIG. 3 is a partially enlarged schematic cross-sectional view of the semiconductor light emitting device. 4A and 4B show a sapphire substrate, in which FIG. 4A is a schematic perspective view, FIG. 4B is a schematic explanatory view showing an AA cross section, and FIG. 4C is a schematic enlarged explanatory view. FIG. 5 is a schematic explanatory diagram of a plasma etching apparatus. FIG. 6 is a flowchart showing a method for etching a sapphire substrate. 7A shows the process of the etching method of the sapphire substrate and the mask layer, (a) shows the sapphire substrate before processing, (b) shows the state in which the mask layer is formed on sapphire, and (c) shows the mask layer. A state where a resist film is formed is shown, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film. FIG. 7B shows the process of the etching method of the sapphire substrate and the mask layer, (f) shows the state where the remaining film of the resist film is removed, (g) shows the state where the resist film has been altered, and (h) The mask layer is etched using the resist film as a mask, and (i) shows the sapphire substrate etched using the mask layer as a mask. FIG. 7C shows the process of etching the sapphire substrate and the mask layer, (j) shows a state where the sapphire substrate is further etched using the mask layer as a mask, and (k) shows a state where the remaining mask layer is removed from the sapphire substrate. (L) shows a state in which wet etching is performed on the sapphire substrate. FIG. 8 is a graph showing the relationship between forward current and light output in a light-emitting device using a sapphire substrate whose surface has a diffractive surface due to unevenness and a light-emitting device using a sapphire substrate having a flat surface. . FIG. 9 is a graph showing the reflectivity of the reflecting portion of the example. FIG. 10 shows a light emitting device using a sapphire substrate (MPSS substrate) whose surface has been subjected to moth-eye processing by unevenness, a light emitting device using a flat sapphire substrate (FLAT substrate), and a linear shape on the surface. The light output of a light-emitting device using a sapphire substrate (PSS substrate) with concavo-convex processing when a dielectric multilayer film and an Al layer are formed on the back surface of the sapphire substrate is compared with the case where only the Al layer is formed on the back surface. It is a table showing how much has increased. FIG. 11 is a graph showing the reflectance when the reflective part is made of only a dielectric multilayer film. FIG. 12 is a graph showing the reflectance when the reflective part is only a dielectric multilayer film. FIG. 13 is a graph showing the reflectance when the reflective part is made of only a dielectric multilayer film. FIG. 14 is a graph showing the reflectivity of the reflection portion when Ag is used as the metal film. FIG. 15 is a schematic cross-sectional view of a semiconductor light emitting device showing a second embodiment of the present invention. 16A and 16B show a sapphire substrate, in which FIG. 16A is a schematic perspective view, and FIG. 16B is a schematic longitudinal sectional view showing a BB cross section. FIG. 17 is an explanatory view for processing a sapphire substrate. FIG. 17A shows a state in which a first mask layer is formed on the diffraction surface, and FIG. 17B shows a state in which a resist layer is formed on the first mask layer. (C) shows a state in which the resist layer is selectively irradiated with an electron beam, (d) shows a state in which the resist layer is developed and removed, and (e) shows a state in which the second mask layer is formed. Is shown. FIG. 18 is an explanatory view for processing a sapphire substrate, (a) shows a state where the resist layer is completely removed, (b) shows a state where the first mask layer is etched using the second mask layer as a mask, (C) shows a state where the second mask layer is removed, (d) shows a state where the diffraction surface is etched using the first mask layer as a mask, and (e) shows a state where the first mask layer is removed. . FIG. 19 is a schematic cross-sectional view of a semiconductor light emitting element showing a modification. FIG. 20 is a schematic cross-sectional view of a light emitting device showing a third embodiment of the present invention. FIG. 21 is a partially enlarged schematic cross-sectional view of the light emitting element. FIG. 22 shows a flip chip type light emitting device using a sapphire substrate (MPSS substrate) having a moth-eye process on the surface and a flat surface sapphire substrate (FLAT substrate). It is a table | surface which shows how much the optical output at the time of forming a dielectric multilayer film and a metal electrode on a semiconductor lamination part of an element increased compared with the case where only a metal electrode is formed on a semiconductor lamination part. FIG. 23 is a graph showing the reflectance when a metal layer is formed over a dielectric multilayer film. FIG. 24 is a graph showing the reflectance when the reflective part is made of only a dielectric multilayer film. FIG. 25 is a graph showing the reflectance when the reflective part is only a dielectric multilayer film. FIG. 26 is a graph showing the reflectance when the reflective part is only a dielectric multilayer film. FIG. 27 is a graph showing the reflectance when the reflective part is made of only a metal layer. FIG. 28 is a graph showing the relationship between the pitch of via holes formed in the dielectric multilayer film and the light output. FIG. 29 is a graph showing the relationship between current and voltage for light emitting elements with and without a dielectric multilayer film.

  1 to 7C show a first embodiment of the present invention, and FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device.

  As shown in FIG. 1, the light emitting element 1 includes a semiconductor laminated portion 19 made of a group III nitride semiconductor layer formed on the surface of a sapphire substrate 2 having a diffractive surface 2 a. The light-emitting element 1 is a face-up type, and light is mainly extracted from the side opposite to the sapphire substrate 2. The group III nitride semiconductor layer has a buffer layer 10, an n-type GaN layer 12, a multiple quantum well active layer 14, an electron block layer 16, and a p-type GaN layer 18 in this order from the sapphire substrate 2 side. A p-side electrode 20 is formed on the p-type GaN layer 18, and an n-side electrode 22 is formed on the n-type GaN layer 12.

  The sapphire substrate 2 has a diffractive surface 2a on the surface side, which is a c-plane ({0001}) on which a nitride semiconductor is grown. On the diffractive surface 2a, a flat portion 2b (see FIG. 4A) and a plurality of convex portions 2c (see FIG. 4A) periodically formed on the flat portion 2b are formed. The shape of each convex part 2c can be a frustum shape such as a truncated cone or a polygonal frustum, with the top of the weight cut off, in addition to a conical or polygonal pyramid shape. In the present embodiment, a light diffraction effect can be obtained by each of the convex portions 2c arranged periodically.

  2A and 2B are explanatory diagrams showing the diffraction action of light at the interface having different refractive indexes, where FIG. 2A shows a state of reflection at the interface, and FIG. 2B shows a state of transmission through the interface.

Here, from the Bragg diffraction condition, when light is reflected at the interface, the condition that the reflection angle θ _ref should satisfy with respect to the incident angle θ _in is:
d · n1 · (sin θ _in −sin θ _ref ) = m · λ (1)
It is. Here, n1 is the refractive index of the medium on the incident side, λ is the wavelength of the incident light, and m is an integer. In the present embodiment, n1 is the refractive index of the group III nitride semiconductor. As shown in FIG. 2A, light incident on the interface is reflected at a reflection angle θ _ref that satisfies the above equation (1).

On the other hand, from the Bragg diffraction condition, when light is transmitted at the interface, the condition that the transmission angle θ _out should satisfy with respect to the incident angle θ _in is:
d · (n1 · sin θ _in −n2 · sin θ _out ) = m ′ · λ (2)
It is. Here, n2 is the refractive index of the medium on the exit side, and m ′ is an integer. In the present embodiment, n2 is the refractive index of sapphire. As shown in FIG. 2B, light incident on the interface is transmitted at a transmission angle θ _out that satisfies the above equation (2).

In order for the reflection angle θ _ref and the transmission angle θ _out that satisfy the diffraction conditions of the above expressions (1) and (2) to exist, the period of the diffraction surface 2a is the optical wavelength inside the element (λ / n1). It must be larger than (λ / n2). The generally known moth-eye structure has a period set smaller than (λ / n1) or (λ / n2), and there is no diffracted light. The period of the diffractive surface 2a must be smaller than the coherent length that allows the light to maintain its properties as a wave, and is preferably less than or equal to half the coherent length. By setting it to half or less of the coherent length, the intensity of reflected light and transmitted light by diffraction can be secured.

  FIG. 3 is a partially enlarged schematic cross-sectional view of the semiconductor light emitting device.

  As shown in FIG. 3, a dielectric multilayer film 24 is formed on the back side of the sapphire substrate 2. The dielectric multilayer film 24 is covered with a metal layer. In the present embodiment, an Al layer 26 is formed on the lower surface of the dielectric multilayer film 24. In the light emitting element 1, the dielectric multilayer film 24 and the Al layer 26 form a reflecting portion, and light emitted from the active layer 14 and transmitted through the diffractive surface 2a by the diffracting action is reflected by the reflecting portion. Then, the light transmitted by the diffractive action is incident again on the diffractive surface 2a, and is transmitted again by using the diffractive action on the diffractive surface 2a, whereby the light can be extracted outside the element in a plurality of modes. The inventors of the present application use the one having a dielectric multilayer film 24 as a reflecting portion and having a wavelength of 90% or more in the wavelength range of light emitted from the multiple quantum well active layer 14, thereby dramatically improving the light extraction efficiency of the light-emitting element 1. Found to improve.

The buffer layer 10 is formed on the diffraction surface 2a of the sapphire substrate 2 and is made of AlN. In the present embodiment, the buffer layer 10 is formed by MOCVD (Metal Organic Chemical).
A Vapor Deposition method is used, but a sputtering method can also be used. In addition, the buffer layer 10 has a plurality of frustum-shaped concave portions formed periodically along the convex portions 2c on the diffraction surface 2a side. The n-type GaN layer 12 as the first conductivity type layer is formed on the buffer layer 10 and is composed of n-GaN. The multiple quantum well active layer 14 as a light emitting layer is formed on the n-type GaN layer 12, is composed of GalnN / GaN, and emits blue light by injection of electrons and holes. Here, blue light refers to light having a peak wavelength of 430 nm or more and 480 nm or less, for example. In the present embodiment, the peak wavelength of light emission of the multiple quantum well active layer 14 is 450 nm.

  The electron block layer 16 is formed on the multiple quantum well active layer 14 and is made of p-AIGaN. The p-type GaN layer 18 as the second conductivity type layer is formed on the electron block layer 16 and is made of p-GaN. The n-type GaN layer 12 to the p-type GaN layer 18 are formed by epitaxial growth of a group III nitride semiconductor, and convex portions 2c are periodically formed on the diffraction surface 2a of the sapphire substrate 2. Planarization is achieved by lateral growth in the early stage of growth of the physical semiconductor. In addition, when a voltage is applied to the first conductive type layer and the second conductive type layer at least including the first conductive type layer, the active layer, and the second conductive type layer, the active layer is formed by recombination of electrons and holes. The layer structure of the semiconductor layer is arbitrary as long as it emits light.

  The p-side electrode 20 is formed on the p-type GaN layer 18 and is made of a transparent material such as ITO (Indium Tin Oxide). In the present embodiment, the p-side electrode 120 is formed by a vacuum deposition method, a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like.

  The n-side electrode 22 is formed on the exposed n-type GaN layer 12 by etching the n-type GaN layer 12 from the p-type GaN layer 18. The n-side electrode 22 is made of, for example, Ti / Al / Ti / Au, and is formed by a vacuum deposition method, a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like.

As shown in FIG. 3, the dielectric multilayer film 24 is configured by repeating a plurality of pairs of the first material 24a and the second material 24b having different refractive indexes. In the dielectric multilayer film 24, for example, the first material 24a may be ZrO ₂ (refractive index: 2.18), the second material 24b may be SiO ₂ (refractive index: 1.46), and the number of pairs is five. it can. The dielectric multilayer film 24 may be formed using a material different from ZrO ₂ and SiO ₂ , for example, AlN (refractive index: 2.18), Nb ₂ O ₃ (refractive index: 2.4), Ta ₂ O ₃ (refractive index: 2.35) or the like may be used.

  Next, the sapphire substrate 2 will be described in detail with reference to FIG. 4A and 4B show a sapphire substrate, in which FIG. 4A is a schematic perspective view, FIG. 4B is a schematic explanatory view showing an AA cross section, and FIG. 4C is a schematic enlarged explanatory view.

As shown in FIG. 4 (a), the diffractive surface 2a is aligned with the intersections of the virtual triangular lattice at a predetermined period so that the center of each convex portion 2c is the position of the apex of the regular triangle in plan view. Formed. The period of each convex part 2c is larger than the optical wavelength of the light emitted from the multiple quantum well active layer 14, and smaller than the coherent length of the light. In addition, the period here means the distance of the peak position of the height in the adjacent convex part 2c. The optical wavelength means a value obtained by dividing the actual wavelength by the refractive index. Furthermore, the coherent length corresponds to a distance until the periodic vibrations of the waves cancel each other and the coherence disappears due to the difference in the individual wavelengths of the photon group having a predetermined spectral width. The coherent length lc is approximately lc = (λ ² / Δλ), where λ is the wavelength of light and Δλ is the half width of the light. Here, it is preferable that the period of each convex part 2c is larger than twice the optical wavelength of the light emitted from the multiple quantum well active layer 14. Moreover, it is preferable that the period of each convex part 2c is below half of the coherent length of the light emitted from the multiple quantum well active layer 14.

  In this embodiment, the period of each convex part 2c is 460 nm. Further, since the refractive index of the group III nitride semiconductor is 2.4 and the refractive index of sapphire is 1.8, the refractive index when considering the coherent length on the diffractive surface 2a is an average value of 2. 1 In the present embodiment, since the wavelength of light emitted from the active layer 14 is 450 nm, the optical wavelength when considering the coherent length on the diffraction surface 2a is 214 nm. Further, since the half-value width of the light emitted from the active layer 14 is 27 nm, the half-value width in consideration of the coherent length on the diffractive surface 2a is 13 nm. That is, the coherent length of the light is 3523 nm, and the period of the diffractive surface 2a is greater than twice the optical wavelength of the active layer 14 and less than or equal to half the coherent length.

  In the present embodiment, as shown in FIG. 4C, each convex portion 2c of the diffractive surface 2a is curved from the side surface 2d extending upward from the flat portion 2b and from the upper end of the side surface 2d to the center side of the convex portion 2c. And a curved upper surface 2f formed continuously with the curved portion 2e. As will be described later, the curved portion 2e is formed by dropping the corners by wet etching of the convex portion 2c before the curved portion 2e formed with the corners formed by the meeting portions of the side surface 2d and the upper surface 2f. In addition, as long as the corner is dropped by wet etching, the shape may not be curved. Further, wet etching may be performed until the flat upper surface 2f disappears and the entire upper side of the convex portion 2c becomes the curved portion 2e. In this embodiment, specifically, each convex part 2c has a base end diameter of 380 nm and a height of 350 nm. The diffractive surface 2a of the sapphire substrate 2 is a flat portion 2b in addition to the convex portions 2c, so that the lateral growth of the semiconductor is promoted.

  Here, a manufacturing method of the sapphire substrate 2 for the light emitting element 1 will be described with reference to FIGS. FIG. 5 is a schematic explanatory view of a plasma etching apparatus for processing a sapphire substrate.

As shown in FIG. 5, the plasma etching apparatus 91 is an inductively coupled type (ICP), a flat substrate holding base 92 that holds the sapphire substrate 2, a container 93 that houses the substrate holding base 92, A coil 94 provided via a quartz plate 96 and a power source 95 connected to the substrate holding base 92 are provided. The coil 94 is a solid spiral coil, which supplies high-frequency power from the center of the coil, and is grounded at the outer periphery of the coil. The sapphire substrate 2 to be etched is placed on the substrate holder 92 directly or via a transfer tray. The substrate holding base 92 incorporates a cooling mechanism for cooling the sapphire substrate 2, and is controlled by the cooling control unit 97. The container 93 has a supply port and can supply various gases such as O ₂ gas and Ar gas.

  In performing the etching with the plasma etching apparatus 1, the sapphire substrate 2 is placed on the substrate holder 92, and then the air in the container 93 is discharged to make the pressure reduced. Then, a predetermined processing gas is supplied into the container 93 and the gas pressure in the container 93 is adjusted. Thereafter, high-frequency high-frequency power is supplied to the coil 94 and the substrate holder 92 for a predetermined time to generate a reactive gas plasma 98. The plasma 98 is used to etch the sapphire substrate 2.

Next, an etching method using the plasma etching apparatus 1 will be described with reference to FIGS. 6, 7A, 7B, and 7C.
FIG. 6 is a flowchart showing an etching method. As shown in FIG. 6, the etching method of this embodiment includes a mask layer forming step S1, a resist film forming step S2, a pattern forming step S3, a residual film removing step S4, a resist alteration step S5, and a mask layer. Etching step S6, sapphire substrate etching step S7, mask layer removing step S8, and curved portion forming step S9.

7A shows the process of the etching method of the sapphire substrate and the mask layer, (a) shows the sapphire substrate before processing, (b) shows the state in which the mask layer is formed on the sapphire substrate, and (c) shows the mask. A state where a resist film is formed on the layer is shown, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film.
FIG. 7B shows the process of the etching method of the sapphire substrate and the mask layer, (f) shows the state where the remaining film of the resist film is removed, (g) shows the state where the resist film has been altered, and (h) The mask layer is etched using the resist film as a mask, and (i) shows the sapphire substrate etched using the mask layer as a mask. Incidentally, the resist film after the alteration is expressed by painting out in the drawing.
FIG. 7C shows the process of etching the sapphire substrate and the mask layer, (j) shows a state where the sapphire substrate is further etched using the mask layer as a mask, and (k) shows a state where the remaining mask layer is removed from the sapphire substrate. (L) shows a state in which wet etching is performed on the sapphire substrate.

  First, as shown in FIG. 7A (a), a sapphire substrate 2 before processing is prepared. Prior to etching, the sapphire substrate 2 is cleaned with a predetermined cleaning solution. In the present embodiment, the sapphire substrate 2 is a sapphire substrate.

Next, as shown in FIG. 7A (b), a mask layer 30 is formed on the sapphire substrate 2 (mask layer forming step: S1). In the present embodiment, the mask layer 30 has a SiO ₂ layer 31 on the sapphire substrate 2 and a Ni layer 32 on the SiO ₂ layer 31. Although the thickness of each layer 31 and 112 is arbitrary, for example, the SiO ₂ layer can be 1 nm to 100 nm and the Ni layer 32 can be 1 nm to 100 nm. Note that the mask layer 30 may be a single layer. The mask layer 30 is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like.

  Next, as shown in FIG. 7A (c), a resist film 40 is formed on the mask layer 30 (resist film forming step: S2). In the present embodiment, a thermoplastic resin is used as the resist film 40 and is formed to have a uniform thickness by a spin coating method. The resist film 40 is made of, for example, an epoxy resin and has a thickness of, for example, not less than 100 nm and not more than 300 nm. Note that a photo-curable resin can also be used as the resist film 40.

  Then, the resist film 40 is heated and softened together with the sapphire substrate 2, and the resist film 40 is pressed with a mold 50 as shown in FIG. 7A (d). An uneven structure 51 is formed on the contact surface of the mold 50, and the resist film 40 is deformed along the uneven structure 51.

  Thereafter, while maintaining the pressed state, the resist film 40 is cooled and cured together with the sapphire substrate 2. Then, by separating the mold 50 from the resist film 40, the concavo-convex structure 41 is transferred to the resist film 40 as shown in FIG. 7A (e) (pattern forming step: S3). Here, the period of the concavo-convex structure 41 is 1 μm or less. In the present embodiment, the period of the concavo-convex structure 41 is 460 nm. Moreover, in this embodiment, the diameter of the convex part 43 of the uneven structure 41 is 100 nm or more and 300 nm or less, for example, 230 nm. Moreover, the height of the convex part 43 is 100 nm or more and 300 nm or less, for example, 250 nm. In this state, a remaining film 42 is formed in the recess of the resist film 40.

The sapphire substrate 2 on which the resist film 40 is formed as described above is attached to the substrate holder 92 of the plasma etching apparatus 1. Then, for example, the residual film 42 is removed by plasma ashing to expose the mask layer 30 as a workpiece as shown in FIG. 7B (f) (residual film removing step: S4). In the present embodiment, O ₂ gas is used as a processing gas for plasma ashing. At this time, the convex portion 43 of the resist film 40 is also affected by ashing, and the side surface 44 of the convex portion 43 is not perpendicular to the surface of the mask layer 30 and is inclined by a predetermined angle.

  Then, as shown in FIG. 7B (g), the resist film 40 is exposed to plasma under the condition for alteration, thereby altering the resist film 40 and increasing the etching selectivity (resist alteration step: S5). In the present embodiment, Ar gas is used as a process gas for modifying the resist film 40. In the present embodiment, as the condition for alteration, the bias output of the power source 95 for inducing plasma to the sapphire substrate 2 side is set to be lower than the etching condition described later.

  Thereafter, the mask layer 30 as a workpiece is etched using the resist film 40 that has been exposed to plasma under etching conditions and has a high etching selectivity as a mask (mask layer etching step: S6). In the present embodiment, Ar gas is used as a processing gas for etching the resist film 40. As a result, a pattern 33 is formed on the mask layer 30 as shown in FIG.

  Here, the processing gas, the antenna output, the bias output, and the like can be changed as appropriate for the alteration condition and the etching condition, but it is preferable to change the bias output using the same processing gas as in this embodiment. Specifically, with respect to the condition for alteration, when the processing gas is Ar gas, the antenna output of the coil 94 is 350 W, and the bias output of the power supply 95 is 50 W, curing of the resist film 40 was observed. Etching of the mask layer 30 was observed when the etching gas was Ar gas, the antenna output of the coil 94 was 350 W, and the bias output of the power source 95 was 100 W. In addition to lowering the bias output relative to the etching conditions, the resist can be cured even if the antenna output is reduced or the gas flow rate is reduced.

Next, as shown in FIG. 7B (i), the sapphire substrate 2 is etched using the mask layer 30 as a mask (sapphire substrate etching step: S7). In the present embodiment, etching is performed with the resist film 40 remaining on the mask layer 30. Further, plasma etching is performed using a chlorine-based gas such as BCl ₃ gas as a processing gas.

  Then, as shown in FIG. 7C (j), as the etching proceeds, a diffractive surface 2a is formed on the sapphire substrate 2. In the present embodiment, the height of the concavo-convex structure on the diffractive surface 2a is 350 nm. Note that the height of the concavo-convex structure can be made larger than 350 nm. Here, if the height of the concavo-convex structure is relatively shallow, for example, 300 nm, the etching may be finished with the resist film 40 remaining as shown in FIG. 7B (i).

In the present embodiment, side etching is promoted by the SiO ₂ layer 31 of the mask layer 30, and the side surface 2d of the convex portion 2c of the diffractive surface 2a is inclined. Further, the side etching state can also be controlled by the inclination angle of the side surface 43 of the resist film 40. If the mask layer 30 is a single layer of the Ni layer 32, the side surface 2d of the convex portion 2c can be made substantially perpendicular to the main surface.

Thereafter, as shown in FIG. 7B (k), the mask layer 30 remaining on the sapphire substrate 2 is removed using a predetermined stripping solution (mask layer removing step: S8). In this embodiment, after removing the Ni layer 32 by using high-temperature nitric acid, the SiO ₂ layer 31 is removed by using hydrofluoric acid. Even if the resist film 40 remains on the mask layer 30, it can be removed together with the Ni layer 32 with high-temperature nitric acid. However, if the residual amount of the resist film 40 is large, the resist film 40 is previously obtained by O ₂ ashing. Is preferably removed.

  Then, as shown in FIG. 7B (l), the corner of the convex portion 2c is removed by wet etching to form a curved portion (curved portion forming step: S9). Here, the etching solution is arbitrary, but for example, a phosphoric acid aqueous solution heated to about 170 ° C., so-called “hot phosphoric acid” can be used. In addition, this bending part formation process can be abbreviate | omitted suitably. Through the above steps, the sapphire substrate 2 having a concavo-convex structure on the surface is produced.

  According to this etching method of the sapphire substrate 2, the resist film 40 is exposed to plasma and altered, so that the etching selectivity between the mask layer 30 and the resist film 40 can be increased. Thereby, it becomes easy to process the mask layer 30 with a fine and deep shape, and the mask layer 30 with a fine shape can be formed sufficiently thick.

  Further, the plasma etching apparatus 1 can continuously perform the alteration of the resist film 40 and the etching of the mask layer 30 without significantly increasing the number of steps. In the present embodiment, the resist film 40 is altered and the mask layer 30 is etched by changing the bias output of the power supply 95, and the selectivity of the resist film 40 can be easily increased.

  Furthermore, since the sapphire substrate 2 is etched using the sufficiently thick mask layer 30 as a mask, the sapphire substrate 2 can be easily processed in a fine and deep shape. In particular, forming a concavo-convex structure with a period of 1 μm or less and a depth of 300 nm or more in a sapphire substrate forms a resist film on the substrate on which the mask layer is formed, and etches the mask layer using the resist film. In the etching method that performs the above, it has been impossible in the past, but in the etching method of the present embodiment, it is possible. In particular, the etching method of this embodiment is suitable for forming a concavo-convex structure having a period of 1 μm or less and a depth of 500 nm or more.

  The nanoscale periodic concavo-convex structure is referred to as moth eye. However, when this moth eye is processed on sapphire, sapphire is a difficult-to-cut material and can only be processed to a depth of about 200 nm. However, a step of about 200 nm may be insufficient as a moth eye. It can be said that the etching method of this embodiment has solved a novel problem in the case of performing moth-eye processing on a sapphire substrate.

Although the mask layer 30 made of SiO ₂ / Ni is shown as a workpiece, it is needless to say that the mask layer 30 may be a single Ni layer or another material. In short, the resist may be altered to increase the etching selectivity between the mask layer 30 and the resist film 40.

  In addition, the change of the bias output of the plasma etching apparatus 1 is shown to be the condition for alteration and the condition for etching. Good. In short, the condition for alteration may be a condition in which the resist is altered when the resist is exposed to plasma and the etching selectivity is increased.

  Although the mask layer 30 includes the Ni layer 32, it is needless to say that the present invention can be applied to etching of other materials. Note that the sapphire substrate etching method of the present embodiment can also be applied to substrates of SiC, Si, GaAs, GaN, InP, ZnO, and the like.

  A group III nitride semiconductor is epitaxially grown on the diffractive surface 2a of the sapphire substrate 2 fabricated as described above by utilizing lateral growth (semiconductor formation step), each electrode is formed, and the dielectric multilayer film 24 is formed on the back surface. And after forming Al layer 26 (multilayer film formation process), light emitting element 1 is manufactured by dividing into a plurality of light emitting elements 1 by dicing.

  In the light emitting element 1 configured as described above, the diffractive surface 2a in which the convex portions 2c are formed with a period larger than the optical wavelength of the light emitted from the active layer 14 and smaller than the coherent length of the light, and the diffractive surface 2a And a reflection part that reflects the diffracted light and re-enters the diffractive surface 2a, so that the light incident on the interface between the sapphire substrate 2 and the group III nitride semiconductor layer at an angle exceeding the total reflection critical angle. Also, the light can be extracted outside the element by utilizing the diffraction action. Specifically, the light transmitted by the diffractive action is re-incident on the diffractive surface 2a and transmitted again using the diffractive action on the diffractive surface 2a, so that the light can be extracted outside the device in a plurality of modes. it can. About this embodiment, since the light is extracted by the diffractive action, an effect different from that of the light extracted by the scattering action can be obtained, and the light extraction efficiency of the light emitting element 1 can be greatly improved.

  Moreover, in the light emitting element 1 of this embodiment, since the convex part 2c is formed with a short period, the number of the convex parts 2c per unit area increases. When the convex portion 2c exceeds twice the coherent length, even if the convex portion 2c has a corner portion as a starting point of dislocation, the dislocation density is small, so that the light emission efficiency is hardly affected. However, when the period of the convex portion 2c becomes smaller than the coherent length, the dislocation density in the buffer layer 10 of the semiconductor stacked portion 19 increases, and the light emission efficiency decreases significantly. This tendency becomes more prominent when the period is 1 μm or less. Note that the decrease in light emission efficiency occurs regardless of the manufacturing method of the buffer layer 10 and occurs regardless of whether it is formed by the MOCVD method or the sputtering method. In the present embodiment, since there is no corner that becomes the starting point of dislocation above each convex portion 2 c, dislocation does not occur starting from the corner when the buffer layer 10 is formed. As a result, the multiquantum well active layer 14 is also a crystal having a relatively low dislocation density, and the luminous efficiency is not impaired by forming the convex portion 2c on the diffractive surface 2a.

  Here, the inventors of the present application have found that the light extraction efficiency of the light-emitting element 1 is remarkably increased by providing a reflective portion including the dielectric multilayer film 24 on the back surface of the sapphire substrate 2. Compared with the case where the reflection part is made of a single Al layer, the light output is improved by 20% or more by making the reflection part a reflectance of 90% or more. When the reflective part including the dielectric multilayer film 24 is provided on the back surface of the sapphire substrate 2, even if the reflectance of the reflective part is 90%, the reflectance of the Al layer is about 80%. If it sees, it is an improvement of about 10%. When the surface of the sapphire substrate 2 is flat, even if the reflectance of the back surface of the sapphire substrate 2 is improved by about 10%, the light output of the entire device is improved only by about 10%. However, when the diffractive surface 2a is formed on the surface of the sapphire substrate 2 and the semiconductor layer including the active layer 14 is formed on the diffractive surface 2a, the light output is improved by 20% or more, which is predicted by those skilled in the art. It can be said that the effect is unique to the element in which the moth-eye structure is formed on the surface of the sapphire substrate 2 that exceeds the above range.

FIG. 8 is a graph showing the relationship between forward current and light output in a light-emitting device using a sapphire substrate whose surface has a diffractive surface due to unevenness and a light-emitting device using a sapphire substrate having a flat surface. . In data acquisition, as an example, a sample body of a light emitting device using a sapphire substrate in which convex portions having a height of 350 nm were formed on the surface with a period of 460 nm and a dielectric multilayer film and an Al layer were formed on the back surface was prepared. . Further, as Comparative Example 1, a sample body of a light-emitting element using a sapphire substrate in which convex portions having a height of 350 nm were formed on the surface with a period of 460 nm and only an Al layer was formed on the back surface was manufactured. Further, as Comparative Example 2, a sample body of a light-emitting element using a sapphire substrate having a flat front surface and a dielectric multilayer film and an Al layer formed on the back surface was manufactured. Moreover, as Comparative Example 3, a sample body of a light emitting element using a sapphire substrate having a flat front surface and only an Al layer formed on the back surface was manufactured. In addition, all the semiconductor lamination parts of each sample body were the same structures, and it was made for the light of a wavelength of 450 nm to be emitted from a light emitting layer. In addition, the dielectric multilayer film of each sample body had a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO ₂ and had 5 pairs.

  As shown in FIG. 8, in the example and the comparative example 1, when the surface of the sapphire substrate is a diffraction surface and the dielectric multilayer film and the Al layer are formed on the back surface of the sapphire substrate, only the Al layer is formed on the back surface. It is understood that the light output is greatly increased compared to the case. It is understood from Comparative Examples 2 and 3 that the light output increases even when the surface of the sapphire substrate is flat, but this effect is remarkable when the surface of the sapphire substrate is a diffractive surface. It becomes.

FIG. 9 is a graph showing the reflectivity of the reflecting portion of the example. In the example, the dielectric multilayer film is a combination of ZrO ₂ and SiO _{2 and} the number of pairs is five, and an Al layer is formed on the dielectric multilayer film. As shown in FIG. 9, a reflectance of almost 100% is realized from 420 nm to 500 nm.

  FIG. 10 shows a light emitting device using a sapphire substrate (MPSS substrate) having a moth-eye process on the surface, a light emitting device using a flat sapphire substrate (FLAT substrate), and a relatively large surface. The light output of a light-emitting device using a sapphire substrate (PSS substrate) with concavo-convex processing when a dielectric multilayer film and an Al layer are formed on the back surface of the sapphire substrate is compared with the case where only the Al layer is formed on the back surface. It is a table showing how much has increased. For the MPSS substrate, the increase rate was obtained from the light output of the example and the comparative example 1, and for the FLAT substrate, the increase rate was obtained from the light output of the comparative example 2 and the comparative example 3. Further, as Comparative Example 4, a sample body of a light emitting element using a sapphire substrate in which convex portions having a height of 700 nm and a diameter of 5000 nm are formed on the surface with a period of 6800 nm and a dielectric multilayer film and an Al layer are formed on the back surface is manufactured. did. As Comparative Example 5, a sample body of a light-emitting element using a sapphire substrate in which convex portions having a height of 700 nm and a diameter of 5000 nm were formed on the surface with a period of 6800 nm and only an Al layer was formed on the back surface was manufactured. For the PSS substrate, the increase rate was obtained from the light output of Comparative Example 4 and Comparative Example 5.

  As shown in FIG. 10, the optical output of the MPSS substrate is increased by 26%, while the increase of the FLAT substrate is only 12%. Furthermore, the PSS substrate having a concavo-convex structure on the surface increases only 2%. This is presumably because the PSS substrate takes out light using a scattering action instead of a diffraction action.

FIG. 11 to FIG. 13 are graphs showing the reflectance when the reflecting portion is only a dielectric multilayer film. FIG. 11 shows the reflectance when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is 20. FIG. 12 shows the reflectance when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is 10. FIG. 13 shows the reflectivity when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is five.

As shown in FIG. 11, when the number of pairs is 20, the reflectivity can be almost 100% from 400 nm to 510 nm. Also, as shown in FIG. 12, when the number of pairs is 10, the reflectance can be almost 100% from 420 nm to 480 nm. That is, if the number of pairs is 10 or more, the same effects as those of the embodiment can be obtained even without the Al layer.
On the other hand, as shown in FIGS. 11 to 13, if the number of pairs of dielectric multilayer films is increased, the reflectance of the wavelength targeted by the dielectric multilayer films can be improved, but the wavelength range of high reflectance is high. Inconveniently, the reflectivity rapidly decreases outside the area.

  Further, as shown in FIG. 13, when the number of pairs is 5, the reflectance is less than 90%. In this case, by providing the Al layer in an overlapping manner, the reflectivity can be almost 100% from 420 nm to 500 nm as shown in FIG. 9, and the high reflectivity can be avoided while avoiding the inconvenience that the reflectivity rapidly decreases. Rate can be realized.

  Here, the metal film covering the dielectric multilayer film may have a configuration other than the Al layer. FIG. 14 is a graph showing the reflectivity of the reflection portion when Ag is used as the metal film. As shown in FIG. 14, a reflectance of almost 100% is realized from 420 nm to 530 nm.

  15 to 18 show a second embodiment of the present invention, and FIG. 15 is a schematic cross-sectional view of a light emitting element.

  As shown in FIG. 15, the light emitting device 100 is obtained by forming a semiconductor stacked portion 119 made of a group III nitride semiconductor layer on a sapphire substrate 102 having a diffractive surface 102a. The group III nitride semiconductor layer has a buffer layer 110, an n-type GaN layer 32, a multiple quantum well active layer 114, an electron block layer 116, and a p-type GaN layer 118 in this order from the sapphire substrate 102 side. A p-side electrode 120 is formed on the p-type GaN layer 118 and an n-side electrode 122 is formed on the n-type GaN layer 32. A dielectric multilayer film 124 is formed on the back side of the sapphire substrate 102. Further, an Al layer 126 is formed on the lower surface of the dielectric multilayer film 124.

  The sapphire substrate 102 has a diffractive surface 102a that is a c-plane ({0001}) on which a nitride semiconductor is grown. The diffractive surface 102a is formed with a flat portion 102b and a plurality of conical concave portions 102c periodically formed on the flat portion 102b. The shape of each recess 102c can be a cone, a polygonal pyramid, or the like. In the present embodiment, the diffraction action of light can be obtained by the concave portions 102c arranged periodically.

  The buffer layer 110 is formed on the diffraction surface 102a of the sapphire substrate 102 and is made of GaN. In the present embodiment, the buffer layer 110 is grown at a lower temperature than an n-type GaN layer 112 and the like which will be described later. In addition, the buffer layer 110 has a plurality of weight-shaped convex portions periodically formed along the concave portions 102c on the diffraction surface 102a side.

  The n-type GaN layer 112, the multiple quantum well active layer 114, the electron block layer 116, the p-type GaN layer 118, the p-side electrode 120, the n-side electrode 122 are the dielectric multilayer film 124, and the Al layer 126 is the first implementation. It is the structure similar to a form. Also in the present embodiment, the light transmitted by the diffractive action is incident again on the diffractive surface 102a, and is transmitted again by using the diffractive action on the diffractive surface 102a, thereby extracting the light in a plurality of modes to the outside of the element. Can do. The inventors of the present application have found that the light extraction efficiency of the light-emitting element 100 is dramatically improved by using the dielectric multilayer film 124 as the reflecting portion.

  Next, the sapphire substrate 102 will be described in detail with reference to FIG. 16A and 16B show a sapphire substrate, in which FIG. 16A is a schematic perspective view, and FIG. 16B is a schematic longitudinal sectional view showing a BB cross section.

As shown in FIG. 16A, the diffractive surface 102a is aligned with the intersections of the virtual triangular lattice at a predetermined period so that the center of each concave portion 102c is the position of the vertex of the regular triangle in plan view. Formed. The period of each recess 102c is larger than the optical wavelength of the light emitted from the multiple quantum well active layer 114 and smaller than the coherent length of the light. Here, the period refers to the distance between the peak positions of the depths in the adjacent recesses 102c. The optical wavelength means a value obtained by dividing the actual wavelength by the refractive index. Furthermore, the coherent length corresponds to a distance until the periodic vibrations of the waves cancel each other and the coherence disappears due to the difference in the individual wavelengths of the photon group having a predetermined spectral width. The coherent length lc is approximately lc = (λ ² / Δλ), where λ is the wavelength of light and Δλ is the half width of the light. Here, the period of each recess 102c is preferably larger than twice the optical wavelength of the light emitted from the multiple quantum well active layer 114. Moreover, it is preferable that the period of each recessed part 102c is below half of the coherent length of the light emitted from the multiple quantum well active layer 114.

  In the present embodiment, the period of each recess 102c is 500 nm. Further, since the refractive index of the group III nitride semiconductor layer is 2.4 and the refractive index of sapphire is 1.8, the refractive index when considering the coherent length in the diffraction surface 102a is 2 of the average value thereof. .1. In the present embodiment, since the wavelength of light emitted from the active layer 114 is 450 nm, the optical wavelength when considering the coherent length on the diffractive surface 2a is 214 nm. In addition, since the half-value width of the light emitted from the active layer 114 is 63 nm, the half-value width in consideration of the coherent length on the diffractive surface 2a is 30 nm. That is, the coherent length of the light is 1527 nm, and the period of the diffractive surface 102a is greater than twice the optical wavelength of the active layer 114 and less than or equal to half the coherent length.

  In the present embodiment, as shown in FIG. 16B, each recess 102c of the diffractive surface 102a is formed in a conical shape. Specifically, each recess 102c has a base end diameter of 200 nm and a depth of 500 nm. The diffractive surface 102a of the sapphire substrate 102 is a flat portion 102b in addition to the concave portions 102c, so that the lateral growth of the semiconductor layer is promoted.

  Here, a method for manufacturing the sapphire substrate 102 for the light emitting element 100 will be described with reference to FIGS. FIG. 17 is an explanatory diagram for processing a sapphire substrate, where (a) shows a state in which a first mask layer is formed on the diffraction surface, and (b) shows a state in which a resist layer is formed on the first mask layer. (C) shows a state in which the resist layer is selectively irradiated with an electron beam, (d) shows a state in which the resist layer is developed and removed, and (e) shows a state in which the second mask layer is formed. Indicates the state.

First, as shown in FIG. 17A, a flat sapphire substrate 102 is prepared, and a first mask layer 130 is formed on the surface of the sapphire substrate 102. The first mask layer 130 is made of, for example, SiO ₂ and is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like. Although the thickness of the 1st mask layer 130 is arbitrary, it is 1.0 micrometer, for example.

  For example, when forming the 1st mask layer 130 using a magnetron sputtering apparatus, Ar gas can be used and a high frequency (RF) power supply can be used. Specifically, for example, the first mask layer 130 of 600 nm can be deposited on the sapphire substrate 102 by setting Ar gas to 25 sccm and the power of the RF power source to 200 to 500 W depending on the material. At this time, the sputtering time can be appropriately adjusted.

  Next, as illustrated in FIG. 17B, a resist layer 132 is formed on the first mask layer 130 of the sapphire substrate 102. The resist layer 132 is made of, for example, an electron beam photosensitive material such as ZEP manufactured by Zeon Corporation, and is applied on the first mask layer 130. The thickness of the resist layer 132 is arbitrary, but is, for example, 100 nm to 2.0 μm.

  For example, when the resist layer 132 is formed by spin coating, a uniform film is formed with a spinner rotation speed of 1500 rpm, and then baked at 180 ° C. for 4 minutes to be cured, whereby a resist having a thickness of 160 to 170 nm is formed. Layer 132 can be obtained. Specifically, as a material of the resist layer 132, a mixture of ZEP manufactured by Nippon Zeon Co., Ltd. and diluent ZEP-A manufactured by Nippon Zeon Co., Ltd. in a ratio of 1: 1.4 can be used.

  Next, as shown in FIG. 17C, a stencil mask 134 is set apart from the resist layer 132. A gap of 1.0 μm to 100 μm is opened between the resist layer 132 and the stencil mask 134. The stencil mask 134 is made of, for example, a material such as diamond or SiC, and the thickness is arbitrary, but the thickness is, for example, 500 nm to 100 μm. The stencil mask 134 has an opening 134a that selectively transmits an electron beam.

  Here, the stencil mask 134 is formed in a thin plate shape having a constant thickness. For example, a stencil mask 134 is provided with a lattice-like shape or a thick portion of a ridge to partially increase the thickness to give strength. May be. In the present embodiment, a plurality of light emitting devices 100 are manufactured by forming recesses 102c corresponding to the plurality of light emitting devices 100 collectively on a wafer-like sapphire substrate 102 and dicing after epitaxial growth of a group III nitride semiconductor. To do. Therefore, the thick part of the stencil mask 134 can be formed corresponding to the passing position of the dicing blade. The thick portion may protrude toward the sapphire substrate 102, protrude toward the opposite side of the sapphire substrate 102, or may protrude toward both sides. When projecting to the sapphire substrate 102 side, a spacer function with the resist layer 132 can be imparted to the thick portion by bringing the tip of the thick portion into contact with the resist layer 132.

Thereafter, as shown in FIG. 17C, the stencil mask 134 is irradiated with an electron beam, and the resist layer 132 is exposed to the electron beam that has passed through each opening 134 a of the stencil mask 134. Specifically, for example, the pattern of the stencil mask 134 is transferred to the resist layer 132 using an electron beam of 10 to 100 μC / cm ² . Since the electron beam is irradiated in a spot shape on the stencil mask 134, the electron beam is actually irradiated over the entire surface of the stencil mask 134 by scanning the electron beam. The resist layer 132 is a positive type, and when exposed to light, its solubility in a developer increases. Note that a negative type resist layer 132 may be used. Here, when the resist layer 132 is exposed to light, the solvent contained in the resist layer 132 is volatilized. However, a volatile component is diffused due to a gap between the resist layer 132 and the stencil mask 134. It becomes easy to prevent the stencil mask 134 from being contaminated by volatile components.

  After the electron beam irradiation is completed, the resist layer 132 is developed using a predetermined developer. As a result, as shown in FIG. 17 (d), the portion irradiated with the electron beam is eluted into the developer, and the portion not irradiated with the electron beam remains to form the opening 132a. When ZEP manufactured by Nippon Zeon Co., Ltd. is used as the resist layer 132, for example, amyl acetate can be used as the developer. Whether or not to wash with a rinsing solution after development is arbitrary, but when ZEP manufactured by ZEON Corporation is used as the resist layer 132, for example, IPA (isopropyl alcohol) can be used as the rinsing solution.

  Next, as shown in FIG. 17E, a second mask layer 136 is formed on the first mask layer 130 on which the resist layer 132 is patterned. In this manner, the second mask layer 136 is patterned on the first mask layer 130 using electron beam irradiation. The second mask layer 136 is made of, for example, Ni, and is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like. Although the thickness of the 2nd mask layer 136 is arbitrary, it is 20 nm, for example. Similarly to the first mask layer 130, the second mask layer 136 can be formed using, for example, a magnetron sputtering apparatus.

  FIG. 18 is an explanatory view for processing a sapphire substrate, (a) shows a state where the resist layer is completely removed, (b) shows a state where the first mask layer is etched using the second mask layer as a mask, (C) shows a state where the second mask layer is removed, (d) shows a state where the diffraction surface is etched using the first mask layer as a mask, and (e) shows a state where the first mask layer is removed. .

  As shown in FIG. 18A, the resist layer 132 is removed using a stripping solution. For example, the resist layer 132 can be removed by immersing it in a stripping solution and irradiating with ultrasonic waves for a predetermined time. Specifically, for example, diethyl ketone can be used as the stripping solution. Further, whether or not to wash with a rinsing liquid after removing the resist layer 132 is arbitrary, but cleaning can be performed using, for example, acetone, methanol, or the like as the rinsing liquid. As a result, a pattern of the second mask layer 136 is formed on the first mask layer 130 by inverting the pattern of the openings 134 a of the stencil mask 134.

Next, as shown in FIG. 18B, the first mask layer 130 is dry-etched using the second mask layer 136 as a mask. Thereby, the opening 130a is formed in the first mask layer 130, and the pattern of the first mask layer 130 is formed. At this time, as the etching gas, the sapphire substrate 102 and the first mask layer 130 are more resistant than the second mask layer 136. For example, when the first mask layer 130 is SiO ₂ and the second mask layer 136 is Ni, when a fluorine-based gas such as SF ₆ is used, the etching selectivity of Ni to SiO ₂ is about 100. Thus, the patterning of the first mask layer 130 can be performed accurately.

Thereafter, as shown in FIG. 18C, the second mask layer 136 on the first mask layer 130 is removed. When the first mask layer 130 is SiO ₂ and the second mask layer 136 is Ni, it is immersed in hydrochloric acid and nitric acid diluted with water and mixed at about 1: 1, or Ni is removed by dry etching with argon gas. Can be removed.

Then, as shown in FIG. 18D, the sapphire substrate 102 is dry-etched using the first mask layer 130 as a mask. At this time, since only the portion of the sapphire substrate 102 from which the first mask layer 130 has been removed is exposed to the etching gas, the inversion pattern of each opening 134a of the stencil mask 134 can be transferred to the sapphire substrate 102. it can. At this time, since the first mask layer 130 has higher resistance to the etching gas than the sapphire substrate 102, a portion that is not covered with the first mask layer 130 can be selectively etched. Then, the etching is terminated when the etching depth of the sapphire substrate 102 reaches the desired depth. In the present embodiment, the opening 130a transferred to the first mask layer 130 in the initial stage of etching has a diameter of 50 nm. However, as the etching proceeds in the depth direction, the side etching also proceeds. A conical recess 102c having a base end diameter of 150 nm is formed. In the present embodiment, as etching progresses, the contact between the first mask layer 130 and the sapphire substrate 102 is lost, and the first mask layer 130 is removed from the outer edge. Here, as the etching gas, for example, a chlorine-based gas such as BCl ₃ is used. When a combination of the first mask layer 130 and the etching gas in which the side etching does not proceed is selected, the reverse pattern of the opening 134a of the stencil mask 134 is designed to have the same shape as the base end portion of each recess 102c. Good.

Thereafter, as shown in FIG. 18E, the first mask layer 130 remaining on the sapphire substrate 102 is removed using a predetermined stripping solution. As the stripper, for example, when SiO ₂ is used for the first mask layer 130, dilute hydrofluoric acid can be used.

  A group III nitride semiconductor is epitaxially grown on the diffractive surface 102a of the sapphire substrate 102 fabricated as described above using lateral growth, and after forming each electrode, the light emitting element 100 is divided by dicing. Thus, the light emitting device 100 is manufactured.

  When the light emitting device 100 is manufactured as described above, although the concave portion 102c is formed on the diffraction surface 102a of the sapphire substrate 102, the termination of dislocation occurs during planarization by lateral growth of the group III nitride semiconductor layer. A crystal having a relatively low dislocation density is obtained in the group III nitride semiconductor layer. As a result, the multiquantum well active layer 114 is also a crystal having a relatively low dislocation density, and the light emission efficiency is not impaired by the formation of the recess 102c in the diffraction surface 102a.

  Here, the inventors of the present application have found that the light extraction efficiency of the light emitting device 100 is remarkably increased by providing the reflective portion including the dielectric multilayer film 124 on the back surface of the sapphire substrate 102. Compared with the case where the reflection part is made of a single Al layer, the light output is improved by 20% or more by making the reflection part a reflectance of 90% or more. When the reflective part including the dielectric multilayer film 124 is provided on the back surface of the sapphire substrate 102, even if the reflectance of the reflective part is 90%, the reflectance of the Al layer is about 80%. If it sees, it is an improvement of about 10%. When the surface of the sapphire substrate 102 is flat, even if the reflectance of the back surface of the sapphire substrate 102 is improved by about 10%, the light output of the entire device is improved only by about 10%. However, when the diffractive surface 102a is formed on the surface of the sapphire substrate 102 and the semiconductor layer including the active layer 114 is formed on the diffractive surface 102a, the light output is improved by 20% or more, which is predicted by those skilled in the art. It can be said that this is a function and effect peculiar to the element in which the moth-eye structure is formed on the surface of the sapphire substrate 102 exceeding the above range.

  In the above embodiment, the diffractive surface 102a is formed with a plurality of concave portions 102c. For example, as shown in FIG. 19, the diffractive surface 102a of the sapphire substrate 102 has a plurality of prismatic convex portions 202c. May be formed. The light-emitting element 200 in FIG. 19 is obtained by changing the diffraction surface 202a of the light-emitting element 200 in FIG. 15. The prismatic convex portions 202c are formed in alignment with the intersections of virtual square lattices at a predetermined period. Furthermore, the concave portion or the convex portion may be a polygonal pyramid shape such as a triangular pyramid shape or a quadrangular pyramid shape, and it is needless to say that a specific detailed structure can be appropriately changed.

  20 and 21 show a third embodiment of the present invention, and FIG. 20 is a schematic cross-sectional view of a light emitting device.

  As shown in FIG. 20, the light emitting element 301 is obtained by forming the semiconductor stacked portion 19 made of a group III nitride semiconductor layer on the surface of the sapphire substrate 2. The light emitting element 201 is a flip chip type, and light is mainly extracted from the back side of the sapphire substrate 2. The semiconductor stacked unit 19 includes a buffer layer 10, an n-type GaN layer 12, an active layer 14, an electron block layer 16, and a p-type GaN layer 18 in this order from the sapphire substrate 2 side. A p-side electrode 327 is formed on the p-type GaN layer 18, and an n-side electrode 328 is formed on the n-type GaN layer 12. In addition, since the structure and manufacturing method of the sapphire substrate 2 and the semiconductor lamination part 19 are the same as that of the LED element 1 of 1st Embodiment, it is not explained in full detail here.

FIG. 21 is a partially enlarged schematic cross-sectional view of the light emitting element.
In the light emitting element 301, the p-side electrode 327 and the n-side electrode 328 form a reflecting portion.

As shown in FIG. 21, the p-side electrode 327 includes a diffusion electrode 321 formed on the p-type GaN layer 18, a dielectric multilayer film 322 formed in a predetermined region on the diffusion electrode 321, and a dielectric multilayer film. And a metal electrode 323 as a metal layer formed on 322. The diffusion electrode 321 is made of a conductive oxide, is entirely formed on the p-type GaN layer 18, and is made of a transparent material such as ITO (Indium Tin Oxide). The diffusion electrode 321 only needs to be transparent, and for example, other conductive oxides such as IZO (Indium Zinc Oxide), ZnO, and MgO can be used. The dielectric multilayer film 322 is configured by repeating a plurality of pairs of the first material 322a and the second material 322b having different refractive indexes. In the dielectric multilayer film 322, for example, the first material 322a may be ZrO ₂ (refractive index: 2.18), the second material 322b may be SiO ₂ (refractive index: 1.46), and the number of pairs may be five. it can. The dielectric multilayer film 322 may be formed using a material different from ZrO ₂ and SiO _2. For example, AlN (refractive index: 2.18), Nb ₂ O ₃ (refractive index: 2.4), Ta ₂ O ₃ (refractive index: 2.35) or the like may be used. The metal electrode 323 covers the dielectric multilayer film 322 and is made of an alloy material made of a plurality of metal elements such as Ag—Pd—Cu, or a pure metal material made of a single element such as Al or Ag. The metal electrode 323 is electrically connected to the diffusion electrode 321 through a via hole 322c formed in the dielectric multilayer film 325.

As shown in FIG. 21, the n-side electrode 328 is formed on the exposed n-type GaN layer 12 by etching the n-type GaN layer 12 from the p-type GaN layer 18. The n-side electrode 328 includes a diffusion electrode 324 formed on the n-type GaN layer 12, a dielectric multilayer film 325 formed in a predetermined region on the diffusion electrode 324, and a metal formed on the dielectric multilayer film 325. And a metal electrode 326 as a layer. The diffusion electrode 324 is made of a conductive oxide, is formed entirely on the n-type GaN layer 12, and is made of a transparent material such as ITO (Indium Tin Oxide). The diffusion electrode 321 only needs to be transparent, and for example, other conductive oxides such as IZO (Indium Zinc Oxide), ZnO, and MgO can be used. The dielectric multilayer film 325 is configured by repeating a plurality of pairs of the first material 325a and the second material 325b having different refractive indexes. In the dielectric multilayer film 325, for example, the first material 325a may be ZrO ₂ (refractive index: 2.18), the second material 325b may be SiO ₂ (refractive index: 1.46), and the number of pairs may be five. it can. The dielectric multilayer film 325 may be formed using a material different from ZrO ₂ and SiO _2. For example, AlN (refractive index: 2.18), Nb ₂ O ₃ (refractive index: 2.4), Ta ₂ O ₃ (refractive index: 2.35) or the like may be used. The metal electrode 326 covers the dielectric multilayer film 325 and is made of an alloy material made of a plurality of metal elements such as Ag—Pd—Cu, or a pure metal material made of a single element such as Al or Ag. The metal electrode 326 is electrically connected to the diffusion electrode 324 through a via hole 325 c formed in the dielectric multilayer film 325.

  Each via hole 322c, 325c is formed in alignment with the intersection of the virtual triangular lattice at a predetermined period so that the center of each via hole 322c, 325c is the position of the apex of the regular triangle in plan view. The arrangement of the via holes 322c and 325c is arbitrary. For example, the via holes 322c and 325c may be formed in alignment with the intersections of the virtual square lattice at a predetermined period. The via holes 322c and 325c may have any shape in plan view, but are circular, for example.

  In the light emitting element 301 configured as described above, the diffractive surface 2a in which the convex portions 2c are formed with a period larger than the optical wavelength of the light emitted from the active layer 14 and smaller than the coherent length of the light, and the diffractive surface 2a And a reflection part that reflects the diffracted light and re-enters the diffractive surface 2a, so that the light incident on the interface between the sapphire substrate 2 and the group III nitride semiconductor layer at an angle exceeding the total reflection critical angle. Also, the light can be extracted outside the element by utilizing the diffraction action. Specifically, the light reflected by the diffractive action is re-incident on the diffractive surface 2a, and transmitted again using the diffractive action on the diffractive surface 2a, so that the light can be extracted to the outside in a plurality of modes. it can. In the present embodiment, since light is extracted by the diffractive action, the light extraction efficiency of the light emitting element 301 can be drastically improved with an effect different from that of the light extracted by the scattering action.

  Moreover, in the light emitting element 301 of this embodiment, since the convex part 2c is formed in a short period, the number of the convex parts 2c per unit area increases. When the convex portion 2c exceeds twice the coherent length, even if the convex portion 2c has a corner portion as a starting point of dislocation, the dislocation density is small, so that the light emission efficiency is hardly affected. However, when the period of the convex portion 2c becomes smaller than the coherent length, the dislocation density in the buffer layer 10 of the semiconductor stacked portion 19 increases, and the light emission efficiency decreases significantly. This tendency becomes more prominent when the period is 1 μm or less. Note that the decrease in light emission efficiency occurs regardless of the manufacturing method of the buffer layer 10 and occurs regardless of whether it is formed by the MOCVD method or the sputtering method. In the present embodiment, since there is no corner that becomes the starting point of dislocation above each convex portion 2 c, dislocation does not occur starting from the corner when the buffer layer 10 is formed. As a result, the multiquantum well active layer 14 is also a crystal having a relatively low dislocation density, and the luminous efficiency is not impaired by forming the convex portion 2c on the diffractive surface 2a.

  Here, the inventors of the present application have found that the light extraction efficiency of the light emitting element 301 is remarkably increased by providing the reflective portion including the dielectric multilayer films 322 and 325 on the semiconductor laminated portion 19. Compared with the case where the reflection part is a single metal layer, the light output is improved by 30% or more by using a reflection part having a reflectance of 90% or more. When the reflective part including the dielectric multilayer films 322 and 325 is provided on the semiconductor multilayer part 19, even if the reflectance of the reflective part is 90%, the reflectance of the metal layer is about 80%. It is an improvement of about 10% at most. When the surface of the sapphire substrate 2 is flat, even if the reflectance on the semiconductor stacked portion 19 is improved by about 10%, the light output of the entire device is improved only by about 20%. However, when the diffractive surface 2a is formed on the surface of the sapphire substrate 2 and the semiconductor layer including the active layer 14 is formed on the diffractive surface 2a, the light output is improved by 30% or more, which is predicted by those skilled in the art. It can be said that the effect is unique to the element in which the moth-eye structure is formed on the surface of the sapphire substrate 2 that exceeds the above range.

  In addition, since the dielectric multilayer films 322 and 325 are not conductive, via holes 322c and 325c are formed in the dielectric multilayer films 322 and 325 so that the metal electrodes 323 and 326 are in contact with the semiconductor laminated portion 19 side. . At this time, if the metal electrodes 323 and 326 are brought into direct contact with the semiconductor stacked portion 19, current concentrates on the contact portions, and the light emitting area of the active layer 14 may be reduced. However, since the diffusion electrodes 321 and 324 for current diffusion are formed on the semiconductor stacked portion 19 and the metal electrodes 323 and 326 are brought into contact with the diffusion electrodes 321 and 324, current does not concentrate on the contact portion. .

  On the other hand, since the diffusion electrodes 321 and 324 are provided, there arises a new problem that light is absorbed by the diffusion electrodes 321 and 324. This problem is solved by using a transparent conductive oxide as the diffusion electrodes 321 and 324. That is, by making the diffusion electrodes 321 and 324 transparent, light absorption by the diffusion electrodes 321 and 324 can be minimized. Thereby, even if the absorption of the diffusion electrodes 321 and 324 is taken into consideration, the reflectivity of each of the electrodes 327 and 328 can be 90% or more.

  Here, the contact resistance of the diffusion electrodes 321 and 324 with the semiconductor stacked portion 19 is relatively lower directly below the formation region of the dielectric multilayer films 322 and 325 than directly below the contact portion with the metal electrodes 323 and 326. Can be high. As a result, the current flows preferentially directly below the formation region of the dielectric multilayer films 322 and 325, and the light emission amount of the active layer 14 is relatively increased immediately below the formation region of the dielectric multilayer films 322 and 325. Can be made. As a result, as compared with the case where the active layer 14 emits light uniformly, the amount of light incident on the formation region of the dielectric multilayer films 322 and 325 can be increased, and light can be extracted efficiently.

  Here, the contact resistance of the diffusion electrodes 321 and 324 with the semiconductor stacked portion 19 is relatively lower directly below the formation region of the dielectric multilayer films 322 and 325 than directly below the contact portion with the metal electrodes 323 and 326. As a method of increasing the thickness of the diffusion electrode 321, the dielectric multilayer films 322 and 325 having the via holes 322c and 325c are formed on the diffusion electrodes 321 and 324, and the diffusion multilayer films 322 and 325 are used as masks. It can be considered that the exposed portion of 324 is altered. Specifically, when the sputtering method is used to form the metal electrodes 323 and 326, Ag or the like that is formed into plasma during sputtering while the metal electrodes 323 and 326 are formed on the dielectric multilayer films 322 and 325 by the sputtering method. The metal electrodes 323 and 326 can be made to act on the diffusion electrodes 321 and 324 through the via holes 322c and 325c to increase the resistance.

  In the above-described embodiment, the dielectric multilayer film is formed on both the p-side electrode 327 and the n-side electrode 328. However, it is sufficient that the dielectric multilayer film is formed on at least one of them. If a dielectric multilayer film is formed on either one, it is preferable to form the dielectric multilayer film on the p-side electrode 327 having a relatively large area in plan view.

  FIG. 22 shows a flip-chip type light emitting element using a sapphire substrate (MPSS substrate) whose surface has been subjected to moth-eye processing by unevenness, and a flip-chip type light emission using a flat sapphire substrate (FLAT substrate). It is a table | surface which shows how much the optical output at the time of forming a dielectric multilayer film and a metal layer on a semiconductor laminated part of an element increased compared with the case where only a metal layer is formed on a semiconductor laminated part. The convex portion of the MPSS substrate and the dielectric multilayer film were the same as those of the face-up type described above. The metal layer was made of an Ag—Pd—Cu alloy material.

  As shown in FIG. 22, the optical output of the MPSS substrate is increased by 31%, while the increase of the FLAT substrate is only 21%. In addition, the increase rate is expected to be 10% or less in the PSS substrate that extracts light by utilizing the scattering action instead of the diffraction action.

FIG. 23 is a graph showing the reflectance when a metal layer is formed over a dielectric multilayer film. The solid line is a graph that does not consider the light absorption of the diffusion electrode, and the broken line is a graph that considers the light absorption of the diffusion electrode. Here, the dielectric multilayer film is a combination of ZrO ₂ and SiO ₂ , the number of pairs is 5, the metal layer overlapping the dielectric multilayer film is Ag, and the diffusion electrode is ITO. As shown in FIG. 23, if the light absorption of the diffusion electrode is not taken into consideration, a reflectance of almost 100% is realized from 420 nm to 530 nm. Even considering light absorption of the diffusion electrode, a reflectance of 90% or more is realized from 400 nm to 570 nm.

FIG. 24 to FIG. 26 are graphs showing the reflectance when the reflecting portion is only a dielectric multilayer film. The solid line is a graph that does not consider the light absorption of the diffusion electrode, and the broken line is a graph that considers the light absorption of the diffusion electrode. FIG. 24 shows the reflectance when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is 20. FIG. 25 shows the reflectance when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is 10. FIG. 26 shows the reflectance when the dielectric multilayer film is a combination of 51.6 nm ZrO ₂ and 76.76 nm SiO _{2 and} the number of pairs is 5.

  As shown in FIG. 24, when the number of pairs is 20, the reflectance can be almost 100% from 400 nm to 530 nm without considering the light absorption of the diffusion electrode. Even considering light absorption of the diffusion electrode, a reflectance of 90% or more is realized from 400 nm to 530 nm.

  As shown in FIG. 25, when the number of pairs is 10, the reflectance can be almost 100% from 420 nm to 510 nm without considering the light absorption of the diffusion electrode. Even considering light absorption of the diffusion electrode, a reflectance of 90% or more is realized from 400 nm to 530 nm. That is, if the number of pairs is 10 or more, the same effects as those of the embodiment can be obtained even without a metal layer.

  As shown in FIGS. 24 to 26, if the number of pairs of dielectric multilayer films is increased, the reflectance of the wavelength targeted by the dielectric multilayer films can be improved, but on the outside of the high reflectance wavelength range. There arises an inconvenience that the reflectivity rapidly decreases. As shown in FIG. 26, when the number of pairs is 5, the reflectance is less than 90% regardless of the presence or absence of the diffusion electrode. In this case, by providing the metal layer in an overlapping manner, it is possible to achieve a high reflectance while avoiding the disadvantage that the reflectance rapidly decreases as shown in the graph of FIG.

  FIG. 27 is a graph showing the reflectance when the reflective part is made of only a metal layer. FIG. 27 shows the reflectance when the metal layer is made of an Ag—Pd—Cu alloy material. As shown in FIG. 27, when the reflection portion is only a metal layer, the reflectance is less than 90% over the entire area.

  FIG. 28 is a graph showing the relationship between the pitch of via holes formed in the dielectric multilayer film and the light output. Here, in the sample body used for data acquisition, the diameter of each via hole was 10 μm, and each via hole was formed in a triangular lattice pattern. As shown in FIG. 28, when the pitch was set to 20 μm, 30 μm, and 40 μm, the light output was larger than that of an element that did not form a dielectric multilayer film (DBR). In FIG. 28, the light output of the element not forming the dielectric multilayer film is indicated by a broken line “without DBR”. That is, if the via hole pitch is 20 μm or more and 40 μm or less, the light output can be improved.

FIG. 29 is a graph showing the relationship between current and voltage for light emitting elements with and without a dielectric multilayer film. In the light emitting device provided with the dielectric multilayer film, a diffusion electrode made of ITO is formed on the semiconductor laminated portion, and a dielectric multilayer film of a combination of ZrO ₂ and SiO ₂ is formed on the diffusion electrode. An Ag—Pd—Cu-based metal electrode was formed on the film, and the metal electrode was brought into contact with the diffusion electrode through a via hole formed in the dielectric multilayer film. Here, the diameter of the via holes was 10 μm, and the pitch of the via holes was 20 μm. Further, in the light emitting element not provided with the dielectric multilayer film, a diffusion electrode made of ITO was formed on the semiconductor laminated portion, and an Ag—Pd—Cu based metal electrode was formed on the diffusion electrode. As shown in FIG. 29, even if a dielectric multilayer film is provided, the drive voltage hardly increases. That is, in this flip-chip type light emitting element, the light extraction efficiency is dramatically increased by using the reflection portion as a combination of the dielectric multilayer film and the metal layer without increasing the driving voltage.

  Since the semiconductor light emitting device and the method for manufacturing the same according to the present invention can improve the light extraction efficiency, they are industrially useful.

DESCRIPTION OF SYMBOLS 1 Light emitting element 2 Sapphire substrate 2a Diffraction surface 2b Flat part 2c Protrusion part 2d Side surface 2e Curved part 2f Upper surface 10 Buffer layer 12 n-type GaN layer 14 Multiple quantum well active layer 16 Electron block layer 18 p-type GaN layer 20 p side electrode 22 n-side electrode 24 dielectric multilayer film 24a first material 24b second material 26 Al layer 30 mask layer 31 SiO ₂ layer 32 Ni layer 40 resist film 41 concavo-convex structure 42 remaining film 43 convex part 50 mold 51 concavo-convex structure 91 plasma etching apparatus 92 Substrate holder 93 Container 94 Coil 95 Power supply 96 Quartz plate 97 Cooling control part 98 Plasma 100 Light emitting element 102 Sapphire substrate 102a Diffractive surface 102b Flat part 102c Concave part 110 Buffer layer 112 n-type GaN layer 114 Multiple quantum well active layer 116 Electronic block Layer 118 p-type GaN layer 120 p-side electrode 122 n-side electrode 124 dielectric multilayer film 130 first mask layer 130a opening 132 resist layer 132a opening 134 stencil mask 134a opening 136 second mask layer 200 light emitting element 202 sapphire substrate 202a diffraction surface 202c convex Part 301 LED element 321 Diffusion electrode 322 Dielectric multilayer 322a First material 322b Second material 322c Via hole 323 Metal electrode 324 Diffusion electrode 325 Dielectric multilayer 325a First material 325b Second material 325c Via hole 326 Metal electrode 327 P side electrode 328 n-side electrode

Claims (9)

A semiconductor laminate including a light emitting layer;
A sapphire substrate on which the semiconductor laminate is formed, and
On the surface of the sapphire substrate, concave portions or convex portions are formed with a period larger than the optical wavelength of the light emitted from the light emitting layer and smaller than the coherent length,
A semiconductor light-emitting element including a reflective portion including a dielectric multilayer film and having a reflectance of 90% or more in a wavelength region of light emitted from the light-emitting layer. The semiconductor light emitting device is a flip chip type,
Having a transparent diffusion electrode formed on the semiconductor laminate,
The reflective portion is
A dielectric multilayer formed on a part of the diffusion electrode;
The semiconductor light emitting element according to claim 1, further comprising: a metal electrode that covers the dielectric multilayer film and contacts the diffusion electrode in a portion where the dielectric multilayer film is not formed. In the dielectric multilayer film, a plurality of via holes are formed at predetermined intervals,
The semiconductor light emitting device according to claim 2, wherein the metal electrode is in contact with the diffusion electrode through the via hole.   The semiconductor light emitting element according to claim 3, wherein the predetermined interval between the plurality of via holes is 20 μm or more and 40 μm or less.   5. The contact resistance of the diffusion electrode with the semiconductor laminated portion is relatively higher immediately below the formation region of the dielectric multilayer film than immediately below the contact portion with the metal electrode. The semiconductor light emitting element as described.   The semiconductor light emitting element according to claim 5, wherein the diffusion electrode is made of a conductive oxide.   The semiconductor light emitting element according to claim 6, wherein the metal electrode is made of an Ag—Pd—Cu based alloy material. In manufacturing the semiconductor light emitting device according to claim 5,
Forming the dielectric multilayer film having the plurality of via holes on the diffusion electrode;
A method of manufacturing a semiconductor light emitting device, wherein the exposed portion of the diffusion electrode is altered using the dielectric multilayer film as a mask to change the contact resistance of the diffusion electrode with the semiconductor laminated portion.   9. The resistance of the metal electrode according to claim 8, wherein the metal electrode is formed on the dielectric multilayer film by a sputtering method, and the material of the metal electrode that has been converted to plasma during sputtering is applied to the diffusion electrode through the via hole to increase the resistance. A method for manufacturing a semiconductor light emitting device.

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