JPS6384070A - Field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the forward voltage drop of a diode, and to shorten the reverse recovery time by short-circuiting a second conductivity type semiconductor region in a gate wiring electrode section and a source electrode by a partially hole-shaped contact region. CONSTITUTION:A second conductivity type semiconductor region 2, a first conductivity type source region 3, a second conductivity type channel forming region 4 and a gate insulating film 5 are formed to the surface of a first conductivity type drain substrate 1a. A gate electrode 6 shaped onto the gate insulating film 5, a source electrode 7, a layer insulating film 8 and a drain electrode 9 are formed. The contact region 14 of a p-type semiconductor region 11 and the source electrode 7 is shaped partially so as not to increase gate wiring resistance. Accordingly, the contact region 14 with the source electrode 7 is formed to the p-type semiconductor region 11 under a gate bonding pad 13 and under a gate wiring electrode section 15 at the central section of a chip, thus increasing the effective area of a reverse parallel-connection diode incorporated into a power MOSFET, then reducing forward current density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical field effect semiconductor device, and in particular to the characteristics of built-in diodes connected in reverse parallel.

[Conventional technology]

Figure 3 shows the power M as a conventional field effect semiconductor device.
OS field effect transistor (hereinafter referred to as “power MO3FET”)
FIG.

In this example, an n-channel type power MO3FET will be explained. In FIG. 3, 1a is an n0 drain region, 1b is an n-drain region formed on the surface of the n9 drain region 1a, 2 is a plurality of p-type semiconductor regions formed on the surface of the n-drain region 1b, and 3 is a n-type semiconductor region formed on the surface of the n-drain region 1b. An n' source region 4 formed in each p-type semiconductor region 2 with an opening in the center is a channel forming region between the n- drain region 1b and the n' source region 3, and 5 is a gate covering the channel forming region 4. An insulating film, 6 a gate electrode formed on the gate insulating film 5, 7 a part of the surface of each n' source region and the p-type semiconductor region 2 in the center of the n' source region 3 are short-circuited and connected. 8 is an interlayer insulating film that insulates the source electrode 7 and gate electrode 6, 9 is a drain electrode formed on the back surface of the n' drain region 1a, and 2a is a p' semiconductor in each p-type semiconductor region 2. This is a convex area.

A power MOS FET has a large number of basic units having the above configuration connected in parallel.

FIG. 4 shows a schematic diagram of the chip pattern of the power MO3FET. In Fig. 4, 10 is the power MOS shown in Fig. 3.
Power M with many FET basic units connected in parallel
OS FET basic unit cell area, 11 is power M
A p-type semiconductor region (shaded area) formed to surround the O3FET basic unit cell region 10 and connected to the source electrode 7, 12 a source bonding pad region, 13 a gate bonding bathode region, 14 a p-type semiconductor region 11 is a contact region with the source electrode 7, and 15 is a gate wiring electrode portion as a p-type semiconductor region 11 extending from the gate bonding pad 13 to the center of the chip. The gate wiring electrode section 15 is provided to further reduce the wiring resistance of the gate electrode.

A cross section (cross section taken along the line V-V) of the gate wiring electrode section 15 is shown in FIG. This gate wiring electrode section 15 is formed not only at the center of the chip but also at the outer periphery so as to surround the power MOSFET basic unit cell region 10, so that a large number of power MO3FET basic units connected in parallel can operate uniformly. It is arranged like this. FIG. 6 shows a cross section (VI-VI line cross section) of the gate wiring electrode portion 15 on the outer periphery. In FIGS. 5 and 6, 6a is a gate wiring electrode.

Next, the operation will be explained using FIGS. 4 to 6. When a gate voltage is applied between the gate electrode 6 and the source electrode 7 while a drain voltage is applied between the drain electrode 9 and the source electrode 7, a channel is formed in the channel formation region 4, and a channel is formed between the drain electrode 9 and the source electrode 7. Drain current flows. At this time, by controlling the gate voltage applied between the gate electrode 6 and the source electrode 7, the drain current flowing between the drain electrode 9 and the source electrode 7 can be controlled. p-type semiconductor region 2 and n by source electrode 7
A short circuit with the source region 3 is essential for fixing the potential of the channel forming region 4.

The withstand voltage between the drain and source in the power MO3FET basic unit that performs such an operation is the gate electrode 6.
and source electrode 7 are short-circuited to form n-drain region 1b and p
This diode is connected anti-parallel to the power MOS FET and is built in. By diffusing heavy metals as a lifetime killer into the diode region or irradiating it with an electron beam or the like, a diode with a short reverse recovery time can be formed and used as a freewheeling diode.

[Problem that the invention seeks to solve]

When using reverse parallel connected diodes built into conventional field-effect semiconductor devices as freewheeling diodes, a lifetime killer is included to obtain a short reverse recovery time, so the forward voltage drop, which is in a reciprocal relationship, is reduced. There was a problem with getting bigger.

The present invention has been made in view of these points, and an object of the present invention is to obtain a field effect semiconductor device that can reduce the forward voltage drop of a built-in diode.

[Means for solving problems]

In order to achieve such an object, the present invention includes a drain substrate of a first conductivity type, a semiconductor region of a second conductivity type formed on the surface of the drain substrate, and a semiconductor region of the second conductivity type formed in the semiconductor region of the second conductivity type. A source region of the first conductivity type formed on the surface with a central part open, a channel formation region of the 21st conductivity type between the drain substrate and the source region, and a gate formed on the surface of the channel formation region. an insulating film, a gate electrode formed on the gate insulating film, a source electrode formed to short-circuit the source region and the semiconductor region, and an interlayer insulating film insulating between the source electrode and the gate electrode. In a field effect semiconductor device having a drain electrode formed on the back surface of a drain substrate and in which the main current flows in a vertical path, the drain electrode is located at the gate bonding pad and the gate wiring electrode portion extending toward the center of the chip. The semiconductor region of the second conductivity type and the source electrode are short-circuited through a partially hole-shaped contact region.

[Effect]

In the present invention, the forward current density of the diode is reduced, the forward voltage drop is reduced, and the reverse recovery time is shortened.

〔Example〕

A first embodiment of a field effect semiconductor device according to the present invention will be described below.
As shown in the figure. FIG. 1 is a chip pattern diagram, and FIG. 2 is a sectional view taken along the line ■--■ in the gate wiring electrode portion 15 of FIG. In FIGS. 1 and 2, the same or equivalent parts as in FIGS. 3 to 6 are given the same reference numerals. In this device, as shown in FIG. 1, a contact region 14 between the p-type semiconductor region 11 and the source electrode 7 is partially provided so that the gate wiring resistance does not become large.

In this way, in this device, the gate wiring electrode portion 15 under the gate bonding pad 13 and in the center of the chip is
A contact region 1 with the source electrode 7 is formed in the lower p-type semiconductor region 11.
4, the effective area of the backward parallel connected diodes built into the power MOS FET increases, and the forward current density can be reduced.

In the above embodiments, an n-channel type power MO3FET has been described, but a p-channel type power MO3FET may also be used (the same effects as in the above embodiments can be achieved).

〔Effect of the invention〕

As explained above, the present invention provides the gate bonding pad and the second gate wiring electrode portion extending toward the center of the chip.
By short-circuiting the conductive semiconductor region and the source electrode through a partially hole-shaped contact region, the effective area of the built-in reverse parallel-connected diode can be increased, and the forward voltage drop of this diode can be reduced. , which has the effect of shortening the reverse recovery time.

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram showing an embodiment of a field-effect semiconductor device according to the present invention, FIG. 2 is a cross-sectional view taken along the line n--n of FIG. 1, and FIG. 3 is a power diagram of a conventional field-effect semiconductor device. M.O.
4 is a pattern diagram showing a conventional field effect semiconductor device, FIG. 5 is a sectional view taken along the line VV in FIG. 4, and FIG. 6 is a sectional view taken along the line V-V in FIG. It is a sectional view taken along VI line. 1a...n+ drain region, lb-/n- drain region, 2...p-type semiconductor region, 2a...p'-type semiconductor region convex portion, 3...n' source region 4...channel formation region, 5... gate insulating film, 6... gate electrode,
7... Source electrode, 8... Interlayer insulating film, 9... Drain electrode, 10... Power MOS FET basic unit cell region, 11... P-type semiconductor region, 12...
- Source bonding pad, 13... Gate bonding pad, 14... Contact area, 15... Gate wiring electrode portion.

Claims (1)

[Claims] a drain substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the surface of the drain substrate; a conductivity type source region; a second conductivity type channel forming region between the drain substrate and the source region;
A gate insulating film formed on the surface of this channel forming region, a gate electrode formed on this gate insulating film, a source electrode formed to short-circuit the source region and the semiconductor region, and this source electrode. In a field effect semiconductor device, which has an interlayer insulating film that insulates between the gate electrode and the drain electrode formed on the back surface of the drain substrate, and in which the main current flows in a vertical path, the gate bonding pad and the chip center 1. A field-effect semiconductor device, characterized in that the second conductivity type semiconductor region located in a portion of a gate wiring electrode portion extending to a portion thereof and the source electrode are short-circuited through a partially hole-shaped contact region.