JPS6381660A - Magnetic memory controller - Google Patents

Abstract

PURPOSE:To hold an effective data transfer function and data verifying function by connecting a pair of buffer memories to a host side and magnetic memory device side selectively and detecting the coincidence/noncoincidence of a signal transmitted from the buffer memory. CONSTITUTION:A pair of buffer memories BUF 1, 2 have the memory capacity of an unit (one sector) part in a hard disk memory device DSK. BUFF 1, 2 are connected to the interface HINF corresponding to the host HS performing a data transfer at high speed selectively via a multiplexer MPX 1. The BUFF 1, 2 are connected as well to the interface DINF corresponding to the device DSK performing the transfer of data at comparatively low speed selectively via the MPX 2. An error check circuit ERC compares the corresponding data of the BUF 1, 2 and transmits an error signal ERR to the host HS in case of any noncoincidence. An effective transfer function and data verifying function can thus be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic memory control device, and relates to a technique effective for use in, for example, a hard disk memory control device.

[Conventional technology]

To provide efficient data transfer between a hard disk memory device that writes or reads data at a relatively low speed and a host such as a microcomputer that transfers data at a relatively high speed. , ×
An example of one with a two-sided data buffer is the rHD63463 (HDC), published by Hitachi, June 1985.
)-L-Saazmanial". In other words, in a write operation, while one sector of data transferred from the host side to one buffer memory is being written to the hard disk memory device, the next sector of data is transferred to the other buffer memory. It is something. In addition, in a read operation, while one sector of data read from the hard disk memory device is being transferred to one buffer memory, the data of the previous sector that has already been read to the other buffer memory is transferred. is transferred to the host side.

[Problem that the invention seeks to solve]

In the above disk memory control device, CRC (Cyclic Redundancy Clock) is used for error processing.
ode) detection/generation circuit is provided. However, since this error detection only involves reading data written in the hard disk memory device and checking its parity, complete error detection cannot be performed. The inventor of the present application considered adding a data conveyor check function without reducing the write/read speed by using the x2 buffer provided for improving data transfer efficiency.

An object of the present invention is to provide a magnetic memory TJ device that has both an efficient data transfer function and a data verification function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a pair of multiplexers selectively connect at least one pair of buffer memories having a storage capacity corresponding to the unit storage capacity of the magnetic memory device between an interface circuit on the host side and an interface circuit on the magnetic memory device side; A data comparison circuit is provided which receives signals from the pair of buffer memories and detects their match/mismatch.

[Function] According to the above means, data is efficiently transferred between the host side and the magnetic memory device side by complementary switching of a pair of multiplexers, and data is transferred to one of the buffer memories by controlling the multiplexers. It is possible to transfer data from the magnetic memory device, transfer write data from the host side to the other buffer memory, and use a data comparison circuit to detect whether or not they match until data is read from the next sector. .

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a magnetic memory control device according to the present invention. Although not particularly limited, the hard disk control device of this embodiment can be manufactured using known semiconductor integrated circuit manufacturing techniques, but is not particularly limited.
It is formed on a single semiconductor substrate such as single crystal silicon.

Although not particularly limited, the magnetic memory control device of this embodiment is intended for a hard disk control device. That is, the hard disk control device of this embodiment constitutes an interface in a broad sense between the hard disk memory device DSK and the HOTOS H3 consisting of a microcomputer or the like.

A pair of buffer memories BUF1. The BUF2 is configured to have a storage capacity equivalent to a unit (one sector) of storage data (for example, 256 bytes) in a hard disk memory device DsK (not shown). The pair of buffer memories BUF1. BUj2 is a host (H3) to which data transfer is selectively performed at high speed via multiplexer MPXI.
is connected to the corresponding interface HINF. Further, the pair of buffer memories BUF1. BUF2 is
A hard disk memory device D in which data is selectively transferred at a relatively low speed via a multiplexer MPX2.
Connected to interface DINF corresponding to SK.

In this embodiment, in order to perform a verify check, an error check circuit ERC is provided which compares corresponding data in the buffer memories BUFI and BUF2 and detects coincidence/mismatch.

If there is a mismatch between the corresponding data in the buffer memories BUF1 and BUF2, the error check circuit ERC generates an error signal ERR and transmits it to the host H3 via the interface circuit HINF. host h
3 performs data processing such as rewriting upon receiving the error signal ERR.

Note that the multiplexer MPX1. Switching of MPX2, selection of buffer memories BUFI and BUF2, and control of their write or read operation modes, as well as control necessary for the operation of interface circuits HINF and HINF2, are performed by control circuit C0NT. Although not particularly limited, this control circuit C0NT generates operation control signals and timing signals corresponding to various commands using a microprogram method. In the figure, the control signals and timing signals are omitted because the control circuit is not directly related to the present invention and to avoid complicating the drawing.

Each of the above circuit blocks is the error check circuit ER.
Except for C and the signal path for supplying signals thereto, it can basically be configured with the same circuit as the hard disk control device (HO23463).

Next, an example of a write operation will be described with reference to the operational conceptual diagram shown in FIG.

For example, from the host H8 side such as a microcomputer to the hard disk memory device? &DSK, the first multiplexer MPXI writes to the buffer memory BU
Fl can be switched to the l side. As a result, one sector worth of data DO supplied from the host H3 is written to the buffer memory MUFI at high speed via the interface circuit HINF. And what about hard disk memory?
! In the DSK, when the selection of the designated sector O of the designated trunk is made, the second multiplexer MP
X2 is switched to the buffer memory BUFI side, and the data DO transferred to the buffer memory BUFI is converted into serial data and written to the sector O via the interface DINF. In this example,
Using this writing time to the hard disk memory device DsK, one multiplexer MPXI is switched to the buffer memory BUFZ side. As a result, the next data D1 for one sector supplied from the host H3 is
The data is written to the buffer memory MUF2 at high speed via the interface circuit HINF.

The host H3 and the buffer memory BUFI.

Data transfer to and from BUF2 can be performed at high speed (in a short time) compared to the access time for 1 sector in the hard disk memory device DSK, so the host system can utilize free time to perform operations other than disk data transfer operations. Can run jobs. This allows the throughput of the system to be improved.

When writing of data to the first sector 0 of the hard disk memory device fiDsK is completed and the next sector 1 is selected, the second multiplexer MPX2 is switched to the buffer memory BUF2 side and data is transferred to the buffer memory BUF2. The converted data DI is converted into serial data via the interface DINF and written to the sector 1. Using this time, the first multiplexer MPXI is switched to the puffer memory BUF1 again. As a result, one sector of the next data D2 supplied from the host H3 is written to the buffer memory MUFI at high speed via the interface circuit HINF.

For example, if the write data from the host H3 consists of three sectors, the data D2 transferred to the buffer memory BUF1 will be transferred to the same second sector when the hard disk memory device WDSK accesses the next sector 2.
It is written in the same way by switching the multiplexer MPX2.

When the above writing is completed, a write check as described below is executed.

FIG. 3 shows a conceptual diagram for explaining the write check operation.

For the hard disk memory device ffDsK, when the disk rotates once and sector O is selected again, reading is instructed. At this time, for example, the second multiplexer MP
X2 is switched to the buffer memory BUF1 side, and the read data RDO is written to the buffer memory BUF1 via the interface circuit DTNF. While this one sector worth of data RDO is being read, the first multiplexer MPXI is switched to buffer memory BUF2 (tJ), and the recessed data DO corresponding to sector 0 is transferred from the host H3 again. When the reading of the first sector O is completed, the control circuit CONT reads the data from the two buffer memories L3U.
Instructs simultaneous read operation of F1 and BUF2. That is, this read signal, which specifies the same address and reads data from the buffer memories BUFI and BtJF2, is supplied to the error check circuit ERC in byte units, for example. The error check circuit has a digital comparator circuit, and compares each bit in units of bits to detect whether it is a failure or not. Such a buffer memory BIJFI
The read 0 operation for data comparison between and BUF2 is performed by the error check circuit ERC provided in the internal circuit, so it can be performed at extremely high speed. In other words, while reading the space provided between sectors and the index section inserted at the beginning of the next sector 1, the ratio of the above data! I can finish the 52vJ work with plenty of time.

When reading of the data area in the next sector 1 is started, writing is instructed to the buffer memory BUF L, and the data RD1 of the next sector 1 read out via the interface circuit DINF is transferred to the buffer memory BUF.
Transferred to F1. While this one sector worth of data RDI is being read, the first multiplexer M
The write data DI corresponding to sector 1 is transferred again from the host HS to the buffer memory BUF2 via PXI. When the reading of the second sector 1 is completed, the control circuit C0NT instructs the simultaneous reading operation of the two buffer memories BUF1 and BUF2, and supplies the read data to the error check circuit ERC. This is for determining whether there is a match or a non-match. Thereafter, the same operation is performed for the last sector 2 as well.

As mentioned above, the data transfer time from the Hotos H3 can be shortened. Therefore, even if the data transfer operation is performed for the data comparison operation as in this embodiment, the decrease in the throughput of the host system is minimized and does not pose a major problem. In this case, the same reading as above is performed. Therefore, data verification in this embodiment is performed using conventional CR
This can be done by accessing the hard disk memory for C checking. Therefore, the write time including the verification mode is not increased.

Note that in a read operation, data in one sector is transferred to one data buffer BUFI (or BUF2), and data in the next sector is transferred to the other data buffer BUF2, although it is not shown in the figure since it is not directly related to this application.
(or BUF 1), the data in one of the data buffers BUF 1 (BUF 2) is transferred to the host side. Such a buffer memory BUFI.

The alternating switching of BUF2 allows efficient data reading without sacrificing throughput on the host system side. In such a read operation, the CRC included in the interface circuit DINF
Error detection is performed by the tick circuit, and error correction is performed by the ECC circuit.

The effects obtained from the above examples are as follows. That is, (1) Description of units of hard disk memory device 1.1 volume 1
A pair of multiplexers to selectively connect at least one pair of buffer memories having a storage capacity corresponding to C1 between an interface circuit on the host side and an interface circuit on the hard disk memory device side, and signals from the pair of buffer memories. By providing a data comparison circuit that detects the match/mismatch of the received data, it is possible to efficiently transfer data between the host side and the hard disk memory device side. It is possible to transfer read data from the hard disk memory device, transfer write data from the host side to the other buffer memory, and use a data comparison circuit to detect coincidence/mismatch between the two until data is read from the next sector. You can get the effect that you can.

(2) Since the 2-sided buffer memory for efficient data transfer is used as is, a data verification function can be added by simply adding an error check circuit and an internal bus that transmits signals. You can get the effect that you can.

(3) According to the above (1), since the reliability of data writing can be increased, it is possible to obtain the effect that the hard disk memory can also be used for storing important data.

Although the invention made by the inventor of the present application has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it goes without saying that various changes can be made without departing from the gist of the invention. Nor. For example, the number of buffer memories may be three or more for more efficient data transfer. In this case, one buffer memory is used to store read data from the hard disk memory device, and the remaining buffer memory is used to store data for triple check from the host side. As a result, the amount of data transferred in one bus cycle can be increased, so that the throughput on the host system side can be improved.

This invention relates to magnetic memory devices that write/read data at a relatively low speed, such as hard disk memory devices, floppy disk memory devices, and magnetic bubble memory devices, and to magnetic memory devices that transfer data at high speeds, such as computers. It can be widely used in magnetic memory control devices that have a data transfer function with a host.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a pair of multiplexers selectively connect at least one pair of buffer memories having a storage capacity corresponding to the unit storage capacity of the magnetic memory device between an interface circuit on the host side and an interface circuit on the magnetic memory device side; By providing a data comparison circuit that receives signals from the pair of buffer memories and detects their coincidence/mismatch, data can be efficiently transferred between the host side and the magnetic memory device side, and
Under the control of the multiplexer, read data from the hard disk memory device is transferred to one buffer memory, write data is transferred from the host side to the other buffer memory, and the data comparison circuit is used until the next sector data is read. Matching/mismatching between the two can be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a conceptual diagram for explaining an example of the write operation, and FIG. 3 is a conceptual diagram for explaining the verify tick operation. It is.

Claims (1)

[Claims] 1. At least a pair of buffer memories having a storage capacity corresponding to the unit storage capacity of the magnetic memory device, and a first buffer memory that selectively connects the pair of buffer memories to an interface circuit on the host side. a multiplexer; a second multiplexer for selectively connecting the pair of buffer memories to an interface circuit on the magnetic memory device side;
A magnetic memory control device comprising: a data comparison circuit that detects a mismatch. 2. The disk memory according to claim 1, wherein the magnetic memory device is a hard disk memory device, and the unit storage capacity is a storage capacity corresponding to one sector of data. Control device.