JPS6365633A - Film carrier for semiconductor device - Google Patents
Film carrier for semiconductor deviceInfo
- Publication number
- JPS6365633A JPS6365633A JP61209248A JP20924886A JPS6365633A JP S6365633 A JPS6365633 A JP S6365633A JP 61209248 A JP61209248 A JP 61209248A JP 20924886 A JP20924886 A JP 20924886A JP S6365633 A JPS6365633 A JP S6365633A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- film
- lead
- film carrier
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000011889 copper foil Substances 0.000 claims abstract description 21
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 20
- 239000000956 alloy Substances 0.000 claims abstract description 20
- 238000007747 plating Methods 0.000 claims description 33
- 229910020938 Sn-Ni Inorganic materials 0.000 claims description 5
- 229910008937 Sn—Ni Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 abstract description 23
- 238000005452 bending Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 230000005496 eutectics Effects 0.000 abstract description 4
- 229910015363 Au—Sn Inorganic materials 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 26
- 239000004020 conductor Substances 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000011056 performance test Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920013716 polyethylene resin Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〈従来の技術〉
半導体素子の実装技術においては、一定水準以トの性能
を持つ製品を高速で量産するために、自動化が図られて
いる。[Detailed Description of the Invention] <Prior Art> In semiconductor element packaging technology, automation has been attempted in order to mass-produce products with performance above a certain level at high speed.
この自動化を目的として開発されたもののへ一つに、長
尺のスプロケットホール付きフィルムキャリアにワイヤ
レスボンディングにより半導体素子（以下ＩＣチップと
いう）を連続的に組み込んでゆくフィルムキャリア方式
（Ｔａｐｅ Ａｕｔｏｍａｔ、ｅｄｔｌｏｎｄｉｎｇ（
ＴＡＢと略称される））がある。One of the methods developed for the purpose of automation is the film carrier method (Tape Automat, edtlonding), in which semiconductor elements (hereinafter referred to as IC chips) are successively incorporated into a long film carrier with sprocket holes by wireless bonding.
(abbreviated as TAB)).
このフィルムキャリア方式は、ＩＣチップ上に形成され
た微小の電極にフィルムキャリア上の対応するインナー
リードを、加熱されたボンディングツールにより熱圧着
し、インナーリードボンディング（ギヤングボンディン
グ）を行う。この熱圧着操作は、ボンディングツールの
上下運動、フィルムキャリアの送りおよびＩＣチップを
列状に配置したＩＣチップホルダーの送り等を連動さこ
のフィルムキャリア方式に用いられるフィルムキャリア
は、通常ポリイミド樹脂、ポリエステル樹脂等の可とう
性の絶縁フィルムにデバイスホールやスプロケットホー
ル等の必要なｎ通孔を打ち抜きにより形成し、そのフィ
ルムに銅箔を貼着し、次いで該銅箔にフォトレジストを
塗布、乾燥し所定パターンのフォトマスクを通して露光
し、現像して所定のパターン形状のフォトレジスト層を
形成した後、前記フォトレジスト層をマスクとしてエツ
チングを行い、所望の銅箔パターンによるリードを形成
する方法により製造される。In this film carrier method, corresponding inner leads on a film carrier are thermocompression bonded to minute electrodes formed on an IC chip using a heated bonding tool, thereby performing inner lead bonding (guyang bonding). This thermocompression bonding operation involves the vertical movement of a bonding tool, the feeding of a film carrier, and the feeding of an IC chip holder in which IC chips are arranged in a row.The film carrier used in this film carrier method is usually made of polyimide resin or polyester. Necessary N through-holes such as device holes and sprocket holes are formed by punching in a flexible insulating film made of resin, etc., copper foil is pasted on the film, and then photoresist is applied to the copper foil and dried. It is manufactured by a method in which a photoresist layer with a predetermined pattern shape is formed by exposure through a photomask with a predetermined pattern and development, and then etching is performed using the photoresist layer as a mask to form leads with a desired copper foil pattern. Ru.
また、ＩＣチップ■の電極上に設けられた静バンブとＡ
ｕ〜Ｓｎ共晶接合せしめるために、銅箔り−ドの表面に
Ｓｎめっき（通常０．ｔ〜０．５Ｐ厚の無電解錫めっき
）が施されることもある。In addition, the static bump provided on the electrode of the IC chip
In order to achieve u-Sn eutectic bonding, Sn plating (usually electroless tin plating with a thickness of 0.t to 0.5P) is sometimes applied to the surface of the copper foil wire.
しかしながら、このようなフィルムキャリアにはＩＣパ
ッケージへの組立工程または電子部品の実用時において
、以下のような問題点が生じる。However, the following problems arise with such a film carrier during the assembly process into an IC package or during the practical use of electronic components.
（１） リードの機械的強度が不足し、フィルムキャリ
アの製造時またはＩＣパッケージの組立時の取扱いにお
いて、リードの曲りや断線が生じ、歩留りを低下させる
。(1) The mechanical strength of the leads is insufficient, leading to bending and breakage of the leads during handling during production of film carriers or assembly of IC packages, reducing yield.
（２）銅箔リードにｂｂす５口めっきは、通常厚さ０．
１〜０．５−と薄いために、ウィスカー（「ヒゲ」と呼
ばれる針状結晶）が異常な早さで成長する（通学室内放
置で２週間以内）。(2) BB 5-hole plating on copper foil leads usually has a thickness of 0.
Because they are thin (1 to 0.5), whiskers (needle-shaped crystals called whiskers) grow at an abnormally fast rate (within two weeks if left in a school room).
（３）リードの強度が不足し、実用時の湿度サイクルに
よりリードに熱応力が付加し断線が生ずる。(3) The strength of the leads is insufficient, and thermal stress is applied to the leads due to humidity cycles during practical use, resulting in wire breakage.
（４）ギヤングボンディング前の取扱いにおいて、リー
ドの曲り、変形が生じ易い（例えばリードの浮き七がり
、沈みこみ、横方向の移動等）。(4) During handling before gigantic bonding, the lead is likely to be bent or deformed (for example, the lead may float, sink, move in the lateral direction, etc.).
（５）最終的な樹脂封止時に腐食生成物の作用によりリ
ードの腐食、および応力腐食破断の危険性かある。(5) There is a risk of lead corrosion and stress corrosion rupture due to the action of corrosion products during final resin sealing.
（６）フィルムと銅箔リードとの密着性が悪く、エツチ
ングによりリードを形成する際等にリートがフィルムか
ら剥離することがあり、歩留りが低下する。そのため、
フィルムキャリアのリードパターンを微細化することが
できず、高密度多ピン化に対応できない。(6) Adhesion between the film and the copper foil lead is poor, and the lead may peel off from the film when forming the lead by etching, resulting in a decrease in yield. Therefore,
It is not possible to miniaturize the lead pattern of the film carrier, and it is not possible to support high-density and high-pin count.
このような欠点によりＩＣパッケージの信頼性の低下を
招いていた。Such defects have led to a decrease in the reliability of the IC package.
〈発明が解決しようとする問題点〉
本発明の目的は、卜述した従来技術の欠点を解消し、フ
ィルムキャリアのリードの機械的強度の増加、リードの
ウィスカーの発生防止およびリードの剥離強度の増加を
図ることによりＩＣパッケージの信頼性を向上すること
ができる半導体フィルムキャリアを提供する。<Problems to be Solved by the Invention> An object of the present invention is to solve the above-mentioned drawbacks of the prior art, increase the mechanical strength of the leads of a film carrier, prevent the generation of whiskers on the leads, and reduce the peel strength of the leads. Provided is a semiconductor film carrier that can improve the reliability of an IC package by increasing the reliability of an IC package.
く問題点を解決するための手段〉 このような目的は、以下の本発明によって達成される。Means to solve problems〉 Such objects are achieved by the following invention.
即ち、本発明は、可とう性絶縁フィルム上に所望のパタ
ーンの導体膜を貼着し、リードを形成してなる半導体装
置用フィルムキャリアにおいて、前記導体膜は、銅箔の
表面に厚さ０．３〜５戸のＮｉまたはＮｉ系合金めっき
を施したものであることを特徴とする半導体装置用フィ
ルムキャリアを提供するものである。That is, the present invention provides a film carrier for a semiconductor device in which a conductive film of a desired pattern is adhered on a flexible insulating film to form a lead, in which the conductive film is formed on the surface of a copper foil with a thickness of 0. The present invention provides a film carrier for semiconductor devices, characterized in that it is plated with 3 to 5 layers of Ni or Ni-based alloy.
この発明において、銅箔の表面に施すＮｉ系合金めっき
は、Ｓｎ−Ｎｉ合金めっきであるのがよい。In this invention, the Ni-based alloy plating applied to the surface of the copper foil is preferably Sn--Ni alloy plating.
また、可とう性絶縁フィルム上に所望のパターンの導体
膜を貼着し、リードを形成してなる゛１体装置用フィル
ムキャリアにおいて、前記導体１摸は、銅箔の表面に厚
さ０．３〜５−のＮｉまたはＮｉ系合金め７きを施し、
さらにその上にＳｎめっきを施したものであることを特
徴とする半導体装置用フィルムキャリアを提供するもの
である。In addition, in a film carrier for a one-piece device in which a conductor film with a desired pattern is adhered on a flexible insulating film to form leads, the conductor 1 is placed on the surface of a copper foil with a thickness of 0.5 mm. 3-5-Ni or Ni-based alloy plating is applied,
Furthermore, the present invention provides a film carrier for a semiconductor device, characterized in that Sn plating is applied thereon.
以Ｆ、本発明の半導体装置用フィルムキャリアを添ｆ・
１図面に示す好適実施例について詳細に説明する。Hereinafter, the film carrier for semiconductor devices of the present invention is attached.
A preferred embodiment shown in FIG. 1 will be described in detail.
第１図は、本発明の半導体装置用フィルムキャリア！の
部分平面図である。同図に示すように、フィルムヤリア
１は、ポリイミド樹脂、ポリエチレン樹脂、ポリエステ
ル樹脂、可とう性エポキシ樹脂等の樹脂類や、紙類等の
可とう性、絶縁性を有する材料で構成されるフィルム２
」二に所望のパターンの導体膜によるり−ト５が接着剤
等により１１古着さ打ている。Figure 1 shows the film carrier for semiconductor devices of the present invention! FIG. As shown in the figure, the film Yaria 1 is made of resins such as polyimide resin, polyethylene resin, polyester resin, and flexible epoxy resin, and flexible and insulating materials such as paper. film 2
''Secondly, the strip 5 of the conductor film in the desired pattern is glued 11 with adhesive or the like.
フィルムキャリア１には、中央部付近にＩＣチップ９を
マウントするためのデバイスホール４が形成されている
とともに、両側端に沿ってフィルム送りのギヤー（スプ
ロケット）がかみ込むためのスプロケットホール３が形
成されている。なお、フィルムキャリアは通常長尺物で
あるが、第１図には、１個のＩＣチップを装着する１単
位が部分的に示されている。A device hole 4 for mounting an IC chip 9 is formed near the center of the film carrier 1, and sprocket holes 3 are formed along both side edges for engagement with film feeding gears (sprockets). has been done. Although the film carrier is usually a long object, FIG. 1 partially shows one unit on which one IC chip is mounted.
このフィルムキャリア１のデバイスホール４の周囲には
、銅箔によるリード５が互いに電気的に接続しないよう
に形成されており、各リードの先端のインナーリード６
は、フェイスアップで位置合せしてボンディングするこ
とができるようデバイスホール内に突出している。この
インナーリード６の先端が、第２図に示すようにＩＣチ
ップ９上の対応する各電極１０にボンディングされる。Around the device hole 4 of this film carrier 1, leads 5 made of copper foil are formed so as not to be electrically connected to each other, and an inner lead 6 at the tip of each lead is formed.
protrudes into the device hole for face-up alignment and bonding. The tips of the inner leads 6 are bonded to corresponding electrodes 10 on the IC chip 9, as shown in FIG.
本発明のフィルムヤリア１においては、リード５を構成
する導体膜の構造に特徴を有する。第３図および第４図
は、本発明のフイルムヤリアにおけるリード５の断面構
造を示す部分断面側面図である。The film YARIA 1 of the present invention is characterized by the structure of the conductive film constituting the lead 5. 3 and 4 are partial cross-sectional side views showing the cross-sectional structure of the lead 5 in the film carrier of the present invention.
第３図に示すように、リード５は、銅箔５１の表面にＪ
ｌメさ０．３〜５−のＮｉまたはＮｉ系合金めっき層５
２を形成したものである。また第４図に示すように、リ
ード５は銅箔５１の表面に厚さ０．３〜５−のＮｉまた
はＮｉ系合金めっき層５２を形成し、さらにその上層に
ＩＣチップ９の電極！０上のＡｕバンブ１１と＾ｕ−Ｓ
ｎ共晶接合せしめるためにＳｎめっき層５３を形成した
ものでもよい。このＳｎめっき層の形成はり一ド５の全
面でも部分的（例えばインナーリード６のボンディング
部付近）でもよい。As shown in FIG.
Ni or Ni-based alloy plating layer 5 with a diameter of 0.3 to 5
2 was formed. Further, as shown in FIG. 4, the leads 5 are formed by forming a Ni or Ni-based alloy plating layer 52 with a thickness of 0.3 to 5 mm on the surface of a copper foil 51, and further forming an electrode of the IC chip 9 on the upper layer. Au bump 11 on 0 and ^u-S
A Sn plating layer 53 may be formed for n-eutectic bonding. This Sn plating layer may be formed on the entire surface of the beam 5 or on a portion thereof (for example, near the bonding portion of the inner lead 6).
なお、Ｓｎめっき層５３の厚さは特に限定されず、Ａｕ
バンブ１１との共晶接合に必要な川のＳｎを確保しつる
程度、例えば０．３〜１．０ ｐ程度であればよい。Note that the thickness of the Sn plating layer 53 is not particularly limited, and the thickness of the Sn plating layer 53 is not particularly limited.
It is sufficient that the amount of Sn necessary for eutectic bonding with the bump 11 is secured, for example, about 0.3 to 1.0 p.
このようなり一ド５のＮｉまたはＮｉ系合金めっき層の
厚さを０．３〜５Ｉｊ１１とした理由は、厚さが０．３
−未満ではめっきのピンホールからの銅の拡散により表
面に加熱黒点が発生し、厚さが５戸を超えるとめっきが
素材の銅より硬い為、リードの曲げ時にクラックが発生
して、ノツチ効果によりリード折れが生じるからである
。The reason for setting the thickness of the Ni or Ni-based alloy plating layer of 1-do 5 to 0.3 to 5Ij11 is that the thickness is 0.3 to 5Ij11.
If the thickness is less than -, heating black spots will occur on the surface due to the diffusion of copper from pinholes in the plating, and if the thickness exceeds 5, cracks will occur when bending the lead because the plating is harder than the copper material, causing a notch effect. This is because lead breakage occurs.
また、第３図に示すフィルムキャリア１において、Ｎｉ
、１％金合金つき層５２をＳｎ−Ｎｉ合金めっきで構成
すれば、へｕバンブ１１とのＡｕ−Ｓｎ共晶接合が良好
になされるとともにリード５とフィルム２との接着強度
が高まるのでフォトエツチングによりリード５を形成す
る際等にリード５の剥離が生じにくくなり、リードパタ
ーンを微細なパターンとする場合に好適である。Furthermore, in the film carrier 1 shown in FIG.
If the layer 52 with 1% gold alloy is formed of Sn-Ni alloy plating, good Au-Sn eutectic bonding with the U-bump 11 can be achieved and the adhesive strength between the lead 5 and the film 2 can be increased. This makes it difficult for the leads 5 to peel off when the leads 5 are formed by etching, and is suitable for making the lead pattern into a fine pattern.
なお、リード５を形成する銅箔は純銅箔に限らず、例え
ばＣｕ−Ｚｎ合金、ＣＩＪ−Ｓｎ合金等の銅系合金の箔
であってもよい。Note that the copper foil forming the leads 5 is not limited to pure copper foil, and may be a foil of a copper-based alloy such as a Cu-Zn alloy or a CIJ-Sn alloy.
また、リード５の厚さも特に限定されない。Further, the thickness of the lead 5 is not particularly limited either.
〈実施例〉
（実施例１）
厚さ３５戸、幅２４ｍｍの粗化圧延銅箔の表面に厚さが
各々０，０．３．１，２，３，５．１０戸のた。なお、
ニッケルめっきは、低ｐｌ＋のワットニッケル浴を用い
て行った。<Example> (Example 1) The surface of a roughened rolled copper foil having a thickness of 35 mm and a width of 24 mm was coated with thicknesses of 0, 0.3.1, 2, 3, and 5.10 mm, respectively. In addition,
Nickel plating was done using a low pl+ Watt nickel bath.
この導体膜を、厚さ１２５−１幅３５ｍｍのポリイミド
フィルム（デバイスホール、スプロケットホール付）に
エポキシ系接着剤を用いて接着した。This conductor film was adhered to a polyimide film (with device holes and sprocket holes) having a thickness of 125 mm and a width of 35 mm using an epoxy adhesive.
その後、フォトエツチング法により所望のリードパター
ン（２０ビン）を形成し、さらに各リードの表面全面に
０．５．１ＩＩｎ厚の無電解錫めつきを施した。Thereafter, a desired lead pattern (20 bins) was formed by photoetching, and electroless tin plating was applied to the entire surface of each lead to a thickness of 0.5.1 IIn.
かくして得られたＴＢＡ用フィルムキャリアのインナー
リードをＩＣチップにギヤングボンディングしく第２図
および第４図に示す状態）１次いで、エポキシ樹脂によ
り樹脂封止を行ってＩＣパッケージを作成した。これら
各ＩＣパッケージについて、各種性能試験を行った。そ
の結果を表１に示す。The inner leads of the TBA film carrier thus obtained were bonded to the IC chip (states shown in FIGS. 2 and 4) (1) and then resin-sealed with epoxy resin to create an IC package. Various performance tests were conducted on each of these IC packages. The results are shown in Table 1.
利 リード引張強度は、インナーリード１本（リード幅
０．１５ａｎ）当りの値を示す。The lead tensile strength indicates the value per one inner lead (lead width 0.15 an).
＊２ リート引剥し強度は、インナーリート１本（リー
ド幅０ 、１．５ｍｍ）当りの値を示す。*2 Reed peel strength indicates the value per one inner reet (lead width 0, 1.5 mm).
本３ リード繰り返し曲げは、０．５Ｒ治具の曲げ回数
（片道曲げ戻しを２回とし数える）を示す。Book 3: Lead repeated bending indicates the number of times the 0.5R jig is bent (one-way bending back is counted as two times).
祠 耐湿試験は、８５℃、Ｒ８８５％、１０００時間後
の不良発生率を示す。The humidity test shows the failure rate after 1000 hours at 85°C and R885%.
ネ５ 温度サイクル試験は一５０℃〜１５０℃を１００
０サイクル実施後の不良発生率を示す。5 Temperature cycle test - 50℃~150℃ 100℃
The defect occurrence rate after 0 cycles is shown.
本６ 輸送時、組立時の全不良発生率を示す。Book 6: Shows the total defectiveness rate during transportation and assembly.
表１に示すように、ニッケルめっきのＱさが０゜３戸以
上でＩＣパッケージの不良発生率は１７３以下に低減し
、特にめっき厚が３−以上では不良発生率が１７１０程
度まで低減する。また、組立時のリード曲り発生率もニ
ッケルめっきの厚さが３−以上で特に減少している。さ
らに、ニッケルめっきを厚さ０．３−以上施したものは
、ウィスカーの発生が全く見られない。As shown in Table 1, when the Q of the nickel plating is 0°3 or more, the failure rate of the IC package is reduced to 173 or less, and especially when the plating thickness is 3- or more, the failure rate is reduced to about 1710. Furthermore, the incidence of lead bending during assembly is particularly reduced when the thickness of the nickel plating is 3-3 or more. Furthermore, no whisker generation is observed in those coated with nickel plating to a thickness of 0.3 mm or more.
（実施例２）
実施例１と同様の銅箔表面に厚さ０．３ 、１．０−の
３０％Ｓｎ−Ｎｉ合金めっきを施した導体膜を実施例１
と同様のフィルムに同接着剤を用いて接着し、次いでフ
ォトエツチング法により所望のリードパターン（２０ビ
ン）を形成してＴＢＡ用フィルムキャリアを得た。(Example 2) In Example 1, a conductor film was plated with 30% Sn-Ni alloy at a thickness of 0.3 and 1.0 on the same copper foil surface as in Example 1.
A film carrier for TBA was obtained by adhering the same film to the same film using the same adhesive, and then forming a desired lead pattern (20 bins) by photo-etching.
これらのＴＩＩＡ用フィルムキャリアに実施例１と同様
の方法によりＩＣチップを実装してＩＣパッケージを作
成し、これらについて同様の各種性能試験を行った。IC chips were mounted on these TIIA film carriers in the same manner as in Example 1 to create IC packages, and various similar performance tests were conducted on these.
各種性能試験の評価結果は、いずれの項目についても実
施例１の厚さ０．３戸以りのニッケルめっきを施したも
のと同様、優れたものであったが、特にリード引き剥が
し強度が実施例！では３２．５ｇであるのに対し、実施
例２ではいずれも４０．５ｇであり、リードの密着性が
高いことが確認された。The evaluation results of various performance tests were excellent in all items, similar to those of Example 1 with nickel plating with a thickness of 0.3 mm or more, but in particular the lead peel strength was evaluated. example! In Example 2, the lead weight was 32.5 g, whereas in Example 2 the lead weight was 40.5 g, confirming that the lead had high adhesion.
〈発明の効果〉
本発明の半導体装置用フィルムキャリアによりば、リー
ドを構成する導体膜を銅箔の表面に厚さ０．３〜５−の
ＮｉまたはＮｉ系合金めワきを施したもの、さらにはそ
の上にＳｎめっきを施したものとすることにより、以下
のごとき効果を発揮する。<Effects of the Invention> According to the film carrier for a semiconductor device of the present invention, the conductive film constituting the lead is formed by coating the surface of a copper foil with Ni or Ni-based alloy to a thickness of 0.3 to 5 mm, Furthermore, by applying Sn plating thereon, the following effects are exhibited.
（１）リードの機械的強度が増加することにより、加工
時の諸応力、実用時の熱応力が付加された場合でもリー
ドのねじれ、曲り等の変形やリードの破断が生じにくく
、よってＩＣパッケージの信頼性が向上する。(1) By increasing the mechanical strength of the leads, even when various stresses during processing and thermal stress during practical use are applied, deformation such as twisting or bending of the leads and breakage of the leads are less likely to occur, and therefore the IC package reliability is improved.
（２）リードに５口めっきを施す場合、ウィスカーの発
生が防止されるので、短絡事故等を防止し、ＩＣパッケ
ージの信頼性が向上する。(2) When five-hole plating is applied to the leads, the generation of whiskers is prevented, thereby preventing short circuit accidents and improving the reliability of the IC package.
（３）鋼箔の裏面Ｌ”Ｓｎ−Ｎｉ合金めっ矢を施１７た
４抹１１１２によるリードとした場合には、Ｓｎ−Ｎｉ
合金めっきが樹脂との密着性が良いためにフィルムに対
するリードの密着性が高くなり、ＩＣパッケージの信頼
性をより向上することができるとともに２ フォトエツ
チングによりリードを形成する際に、リードの剥離が生
じにくくなるため、リードパターンをより微細なパター
ンとすることができ、膜用の範囲が広がる。(3) When the back side of the steel foil is made of 4mm 1112 with a Sn-Ni alloy plated on the back side, the Sn-Ni
Since the alloy plating has good adhesion to the resin, the adhesion of the lead to the film is high, which can further improve the reliability of the IC package. Since it is less likely to occur, the lead pattern can be made into a finer pattern, and the range of film applications is expanded.
第１図は、本発明の半導体装置用フィルムキャリアの部
分平面図である。
第２図は、インナーリードポンディングを行った状態の
本発明の半導体装置用フィルムキャリアの部分斜視図で
ある。
第３図および第４図は、各々本発明の半導体装置用フィ
ルムキャリアの部分断面側面図である。
符号の説明
ｌ・・・半導体装置用フィルムキャリア、２・・・フィ
ルム、 ３・・・スプロケットホール、４・・・
デバイスホール、５・・・リード、５１−・・銅箔、
５２・−ＮｉまたはＮｉ系合金めっき層、５３・・・Ｓ
ｎめつき層、 ６・・・インナーリード、９・・−Ｉ
Ｃチップ、 １０・・・電極、１１・−ＡｕバンブFIG. 1 is a partial plan view of a film carrier for a semiconductor device according to the present invention. FIG. 2 is a partial perspective view of the film carrier for a semiconductor device of the present invention in a state where inner lead bonding has been performed. 3 and 4 are partial cross-sectional side views of a film carrier for a semiconductor device according to the present invention, respectively. Explanation of symbols 1...Film carrier for semiconductor device, 2...Film, 3...Sprocket hole, 4...
Device hole, 5...Lead, 51--Copper foil, 52--Ni or Ni-based alloy plating layer, 53...S
n plating layer, 6...inner lead, 9...-I
C chip, 10...electrode, 11--Au bump
Claims (3)
膜を貼着し、リードを形成してなる半導体装置用フィル
ムキャリアにおいて、 前記導体膜は、銅箔の表面に厚さ０．３〜５μｍのＮｉ
またはＮｉ系合金めっきを施したものであることを特徴
とする半導体装置用フィルムキャリア。(1) In a film carrier for a semiconductor device in which a conductive film with a desired pattern is adhered on a flexible insulating film to form leads, the conductive film is coated on the surface of a copper foil with a thickness of 0.3 to 5 μm Ni
Or a film carrier for a semiconductor device, characterized in that it is plated with a Ni-based alloy.
である特許請求の範囲第１項に記載の半導体装置用フィ
ルムキャリア。(2) The film carrier for a semiconductor device according to claim 1, wherein the Ni-based alloy plating is Sn-Ni alloy plating.
膜を貼着し、リードを形成してなる半導体装置用フィル
ムキャリアにおいて、 前記導体膜は、銅箔の表面に厚さ０．３〜５μｍのＮｉ
またはＮｉ系合金めっきを施し、さらにその上にＳｎめ
っきを施したものであることを特徴とする半導体装置用
フィルムキャリア。(3) In a film carrier for a semiconductor device in which a conductive film with a desired pattern is adhered on a flexible insulating film to form leads, the conductive film is coated on the surface of the copper foil with a thickness of 0.3 to 5 μm Ni
Alternatively, a film carrier for a semiconductor device, characterized in that it is coated with Ni-based alloy plating and further coated with Sn plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61209248A JPH061789B2 (en) | 1986-09-05 | 1986-09-05 | Film carrier for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61209248A JPH061789B2 (en) | 1986-09-05 | 1986-09-05 | Film carrier for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6365633A true JPS6365633A (en) | 1988-03-24 |
| JPH061789B2 JPH061789B2 (en) | 1994-01-05 |
Family
ID=16569810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61209248A Expired - Fee Related JPH061789B2 (en) | 1986-09-05 | 1986-09-05 | Film carrier for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061789B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0468787A2 (en) * | 1990-07-27 | 1992-01-29 | Shinko Electric Industries Co. Ltd. | Tape automated bonding in semiconductor technique |
| US5384204A (en) * | 1990-07-27 | 1995-01-24 | Shinko Electric Industries Co. Ltd. | Tape automated bonding in semiconductor technique |
| US6518649B1 (en) * | 1999-12-20 | 2003-02-11 | Sharp Kabushiki Kaisha | Tape carrier type semiconductor device with gold/gold bonding of leads to bumps |
| KR100568496B1 (en) | 2004-10-21 | 2006-04-07 | 삼성전자주식회사 | Film circuit substrate having sn-in alloy layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55111142A (en) * | 1979-02-20 | 1980-08-27 | Nec Corp | Manufacturing method of lead wire for semiconductor device |
-
1986
- 1986-09-05 JP JP61209248A patent/JPH061789B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55111142A (en) * | 1979-02-20 | 1980-08-27 | Nec Corp | Manufacturing method of lead wire for semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0468787A2 (en) * | 1990-07-27 | 1992-01-29 | Shinko Electric Industries Co. Ltd. | Tape automated bonding in semiconductor technique |
| US5384204A (en) * | 1990-07-27 | 1995-01-24 | Shinko Electric Industries Co. Ltd. | Tape automated bonding in semiconductor technique |
| US6518649B1 (en) * | 1999-12-20 | 2003-02-11 | Sharp Kabushiki Kaisha | Tape carrier type semiconductor device with gold/gold bonding of leads to bumps |
| KR100568496B1 (en) | 2004-10-21 | 2006-04-07 | 삼성전자주식회사 | Film circuit substrate having sn-in alloy layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH061789B2 (en) | 1994-01-05 |
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