JPS6358547A - Portable medium - Google Patents

Abstract

PURPOSE:To effectively use a ROM by storing a program for self-diagnosis supplied from outside in a nonvolatile memory and executing the processing in accordance with a program using a control element. CONSTITUTION:A contact part 11, a keyboard 12 and a display part 13 are provided on the surface of an IC card 10. This card 10 contains an on-line function that functions together with a terminal equipment, an off-line function that works independently, and a timepiece function. In a self-diagnosis mode a contact probe 131 of a check device 130 is connected to the part 11 and transmission changing command is sent to a CPU 28. The CPU 28 selects a loader program out of a program ROM 29 and delivers a program load command to the device 130. The device 130 loads a self-diagnosis program into a data memory 31 containing a nonvolatile memory. The CPU 28 carries out the diagnosis processing corresponding to the self-diagnosis program stored in the memory 31. In such a way, a ROM is used effectively.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention has a built-in CPU, data memory, etc., and can be used as a card 111 in a calculator, a time display, etc.
The present invention relates to portable media such as IC cards that are used by inserting them into terminals.

(Prior art) Conventionally, multi-functional IC cards have a built-in CPU, data memory, etc., and have a keyboard, display, etc., and can be used as a standalone card in calculators, time displays, etc., or by being inserted into terminals. is being developed.

In such IC cards, at the time of manufacture,
It is necessary to confirm that all elements within the IC card operate normally. As a method for this confirmation, there is a method in which a standard command (for example, a read/write command) provided in the IC card is used to actually read from and write to the memory in the IC card. However, although this kind of device is effective for an IC card with a simple configuration consisting of two chips, a one-chip CPU and an EEPROM, it is not compatible with a multi-function IC card with a keyboard and display section as mentioned above. It was difficult.

Therefore, the mask R as a read-only memory in the CPU
One possible method is to include a self-diagnosis program in the OM, start and execute the self-diagnosis program in response to an external command, and thereby perform self-diagnosis.

However, when such a device is used for a multi-function IC card, the self-diagnosis program becomes quite large, and the C
Although it occupies a large portion of the mask ROM in the PU, there is a problem in that it is not used at all after the manufacturing test and becomes wasted.

(Problems to be Solved by the Invention) As described above, it is an object of the present invention to provide a portable medium that can effectively utilize the read-only memory, thereby eliminating the disadvantage that the read-only memory cannot be used effectively.

[Structure of the Invention] (Means for Solving the Problems) The portable medium of the present invention has a function of communicating with the outside via a contact part, and has a control element, and is capable of storing data in a non-volatile state. a memory section that stores a loader program that loads a self-diagnosis program supplied from the outside into the nonvolatile memory; and a memory section that stores the self-diagnosis program in the nonvolatile memory by the loader program. , means for executing processing according to the program using the control element.

(Function) This invention stores only a loader program for loading a self-diagnosis program into a non-volatile memory in addition to a processing program for a control element in a read-only memory. It is designed to run a program.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 2, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The offline functions mentioned above include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the clock being used by the user, a time change mode that changes the time of the clock that the user is using, and an address mode. , an electronic width mode in which names, telephone numbers, etc. are registered and read, and a shopping mode in which the IC card 10 is used as a credit card or cash card.

On the surface of the IC card 10, a contact section 11 is arranged at a position that matches the card specifications.A keyboard section 12 consisting of 20 keys is arranged on the top surface of the keyboard section 12, and a display section is formed of a liquid crystal display element. 13, and a magnetism generating member 14 are provided.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11a.
llh. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11C is for a clock signal, the terminal 11d is for a reset signal, and the terminals 11e to 11h are for data input/output.

The keyboard section 12 has mode keys (Ml, M2, M3, M4) 12a for specifying processing modes.

It is composed of a numeric keypad 12b1 and four arithmetic operation keys (function keys) 12C.

The mode keys 12a are used to select calculator mode (Ml), time display mode (M2), electronic passbook mode (M3), when offline, that is, when processing only with the IC card 10.
Alternatively, the process for shopping mode (M4) is selected. In addition, in the above shopping mode, M4
Depending on the combination of the keys and the numeric keypad 12b, a process corresponding to the type of card, ie, various credit cards, cash cards, etc., is selected.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating member 14 is inserted into the IC in accordance with the track position of a magnetic card reader (magnetic head) on the reading side (not shown).
It is embedded inside the card 10.

FIG. 3 shows an IC card reading/writing unit 1 used in a terminal device such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the two-legged contact section 11, the communication control circuit 21, the reset control circuit 22, the power supply control circuit 23, the internal battery (built-in power supply) 25 of, for example, 3 volts, and whether or not the voltage value of the internal battery 25 is higher than the specified value. Battery check circuit 24 that checks whether
, a clock control circuit 26, an oscillator 27 that outputs a signal of the oscillation frequency of the IMH2, a control CPU (sens I pull processing unit) 28, and a read-only memory, which stores a program for operating the CPU. It also includes a program ROM (memory section) 29 as a mask ROM that stores a load program for loading a self-diagnosis program supplied from the outside into the data memory 31, a program working memory 30, and a non-volatile memory such as a RAM. A data memory 31 stores data, that is, a self-diagnosis program supplied from an external terminal 16, in a non-volatile state, a timer 32 used for timing during processing operations, a calendar circuit 33, and a crystal oscillation for basic clock oscillation. child, always 32.76
An oscillator 34 outputting a signal with an oscillation frequency (low frequency) of 8KH2, a display control circuit 35, a display driver 36 for driving the display 13, a keyboard interface 38 as a key input circuit for the keyboard 12,
and a magnetism generating member control circuit 40 that controls the magnetism generating member 14.

The communication control circuit 21, CPU 28, two ROMs, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and a magnetism generating member that controls the magnetism generating member 14. The control circuit 40 is connected via the data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, ie, parallel data supplied from the data bus 20 is converted into a serial input/output signal and output to the terminal ja16 via the contact section 11. In this case, ,
The format contents of the conversion are as follows:
It is defined in C Card 10 etc.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. This is to switch to driving by the battery 25.

The clock control circuit 26 stops an oscillation circuit 67 that outputs a signal at an oscillation frequency (high frequency) of the IMH 2, which will be described later, during standby, that is, when the key is in standby mode, in an offline mode in which the card operates with the internal battery 25.
Furthermore, the clock supply to the CPO 28 is also stopped, and the CPO 28 stands by in a completely stopped state. In addition, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 operates for 500 to 600 msec until stable oscillation is performed.
During the period c, the clock is outputted as a clock for the CPO 28, and the first person's key is processed.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the watch clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation occurs, and then It is designed to output the IMH2 clock.

The data memory 31 records information corresponding to a plurality of contracted credit cards (companies) and information corresponding to cash cards, and corresponds to the type of card determined by the combination of the M4 key and the numeric keypad 12b. It is read out as follows. The above information is the same as the information recorded on the conventional magnetic stripe for each card.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, the standard time of the financial world at the time of card issuance and cannot be changed thereafter. ing.

The data memory 31 also records data such as passwords for manufacturers, issuers, users, etc. in areas that are not erased.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern on the display unit 13 using a display unit driver 36. It is to be displayed.

The keyboard interface 38 converts keys input on the keyboard section 12 into human input signals corresponding to keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data and reading device supplied from the data memory 31 via the data bus 20 in accordance with the card type. By controlling the drive of the magnetism generating member 14 and outputting magnetic information according to the drive rate corresponding to manual reading or automatic reading, the state is the same as when a conventional magnetic stripe exists. It is something that

The power supply control circuit 23 will be explained in detail using FIG. 4. That is, inverter circuit 51.54.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the power supply voltage Vcc from the outside decreases, the power supply voltage Vout will not drop even if the power supply voltage Vcc drops below the memory drive voltage before the semiconductor switch 56 is turned on. As shown, it is protected by an internal battery 25.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage VCC is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. Due to the set output Q of the FF circuit 53, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned on.
turns off. Therefore, the external power supply voltage Vcc is applied to the output V of the power supply control circuit 22 via the semiconductor switch 58.
It is applied to each part as out.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external mains voltage Vcc decreases. Thereby, the counter 52 and the FF circuit 53 are reset by the reset signal. Then, a "1" signal is supplied to the gate of the semiconductor switch 58, a "0" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, the voltage ffL of the internal battery 25? 1i pressure is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 6. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with a clock of 32.763KH2 from the calendar circuit 3B. . The reset output of the FF circuit 64 is supplied to the data input end of the FF circuit 65,
A clock input terminal ck of the FF circuit 65 is supplied with a clock of 32.763 KH2 from the calendar circuit 33. The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

Further, the key human interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62, 63, and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes the oscillator 27 having an oscillation frequency of 1 MH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock input terminal ck of this FF circuit 76 is supplied with an OR circuit 84, which will be described later.
output is supplied.

Further, a clock selection signal from the CPU 28 is supplied to the data input terminal D1 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is FF
It is supplied to the data input end of the circuit 77, and this FF circuit 7
A clock of 32.763 KH2 from the calendar circuit 33 is supplied to the clock input terminal ck of No. 7.

The set output of the FF circuit 77 is supplied to one end of the NAND circuit 79, and the clock of 32.763 KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via the inverter circuit 78. be done. The output of the NAND circuit 79 is supplied to one end of a NAND circuit 80.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the FF circuit 740
The set output is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal c k of the FF circuit 8.
The set output of the FF circuit 63 is supplied to the data input terminal of No. 1 via the inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output No. 3 is outputted to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. As a result, the FF circuits 76 and 77 are set. Thereby, the watch clock (32,768KH2) is guided to the FF circuits 81.82 and the inverter circuit 85 via the inverter circuit 78 and the NAND circuits 79.80.

Next, restarting from a stopped state will be explained.

That is, a key human interrupt signal is supplied from the CPO 28. Then, the FF circuits 62, 63, and 64 are reset, and the FF circuit 65 is set.

The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 resumes oscillation.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
“1” is supplied to the data input end of “1”. As a result, the output of the NAND circuit 80 causes the FF circuit 8 to
1.83 is set and opens the gate of NAND circuit 86.

Therefore, the clock from the inverter circuit 85 is output to the CPU 2g via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0~600m5ec is required.

Thereby, the CPU 28 supplies "0" as a clock selection signal to the data input end of the FF circuit 76 500 to 600 m5ec after outputting the key human interrupt signal. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the "1" signal is
It is applied to the data input end of circuit 74.

Also, at this time, the clock (IMH2
) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (IMH2) generated by the oscillation circuit 67 is transmitted to the inverter circuit 72, '73, and the NAND circuit 75.80.
．． The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

Thereby, by setting the clock selection signal to "0", synchronization is achieved in the FF circuit 74, and the clock is switched from the clock for high-speed processing to the clock for high-speed processing.

Next, a case will be described in which the processing is ended and the system is placed in a stopped state (standby state). That is, by setting the clock selection signal to #1'', the FF circuits 76 and 77 are set, the set output of the FF'' circuit 77, that is, the ``1'' signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is set. is open. Therefore, the watch clock is transmitted to the CPU 28 through the inverter circuit 78, the NAND circuit 79, 80, the inverter circuit 85, and the NAND circuit 86.
is output to.

As a result, the watch clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input terminal p of the FF circuit 81. As a result, the set output of the FF circuit 63 is changed to the set output of the FF circuit 81.8.
After sending two pulses in step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CF'U 28. This brings the CPO 28 into a stopped state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of crystal oscillation caused by this, the clock for the watch and the clock for the IMH2 are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 7. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the frequency dividing circuit 9.
By counting the signals from the output end of 1, a, 10
A counter 92 that outputs a signal every second, this counter 9
A counter 93 that outputs a signal every 60 seconds, that is, every minute by counting the signals from 2;
A counter 94 that outputs a signal every 10 minutes by counting the signal from this counter 94, a counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 94; A counter 96 outputs a signal every 24 hours, that is, every day, by counting the signals from the frequency dividing circuit 91, and a counter 97 outputs a signal every 10 seconds by counting the signals from the output terminal of the frequency dividing circuit 91. , a counter 98 that outputs a signal every 60 seconds, that is, one minute, by counting the signal from this counter 97, a counter 99, which outputs a signal every 10 minutes by counting the signal from this counter 98, By counting the signals from this counter 99, a counter 100 outputs a signal every 60 minutes, that is, every hour.By counting the signals from this counter 100, a counter outputs a signal every 24 hours, that is, every day. It is composed of 101.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, while the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. Based on the signal from 101, an interrupt request is output to the CPU 28. Thereby, the CPU 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. In addition, the two clocks are as shown in Figure 8.
Because the phase of the standard 1 second clock is shifted,
Interrupts are not generated at the same time.

The magnetism generating member control circuit 40 will be explained in detail using FIG. 9. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 11
0 consists of four FF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or a start signal is output from the output terminal 110c. A clock selection signal corresponding to the drive rate for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

The clock input terminal cp of the FF circuit 110 has the above C
A command write start signal from the PU 28 is supplied. The clock selection signal corresponding to the drive rate indicates whether the terminal type is manual reading or automatic reading.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. A signal with a frequency of 8KH2 is supplied from an oscillator (not shown) to the input terminal A of this selection circuit 111, and the input terminal B
A signal with a frequency of 4KH2 is supplied from an oscillator (not shown).

In response to the clock selection signal from the FF circuit 110, the selection circuit 111 selects the signal at the input terminal A and outputs it from the output terminal Y when the terminal type is a manual reading type.
If the type of terminal is automatic reading, the signal at input terminal B is selected and output from output terminal Y.

The start signal output from the output end 110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal c of parallel/serial conversion circuit 115
The first clock d1 is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has data “0”.
circuit 116 for selecting the clock for data “1” and the clock for data “1”
is supplied to.

Further, the magnetic data (the size is small depending on the type of card selected) supplied from the CPU 28 via the data bus 20 is supplied to the data latch circuit 113. Start signal is supplied. The data latch circuit 113 latches 7 bits of magnetic data supplied from the data bus 20 when a data write start signal is supplied from the CPU 28.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
The signal is converted into a "1" signal or a "0" signal and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the data "1" clock supplied from the timing circuit 112 when a "1" signal is supplied to the input terminal S, and when a "0" signal is supplied to the input terminal S:; In this case, the clock for data "0" supplied from the timing circuit 112 is selected and output. The output of the selection circuit 116 is supplied to a J-KFF circuit 117, and the set output and reset output of this J-KFF circuit 117 are supplied to a driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 41a in response to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycle ratio for data "1" and "0" is 1:2. J-K with this clock
By operating the FF circuit 117 in the inversion mode, "1" and "0" signals in the format required as magnetic data are obtained and drive the magnetism generating member 41.8.

Further, the data write start signal from the CPO 28 is inverted and supplied to the set input terminal of the empty detection FF circuit 114, and the reset input terminal of this FF circuit 114 receives the first clock from the timing circuit 112. It is supplied inverted. As a result, when the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF circuit 114 is set and the FF circuit 1
14 set outputs, ie, buffer empty signals, are supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be read, and outputs the next data to the data latch circuit 113. In this way, the CPU 28 sets the data in order while sensing the output of the air detection FF circuit 114, and after outputting all the data, turns off the command write start signal and the data write start signal. ing. As a result, the timing circuit 11
2 stops generating the signal, and the operation ends.

The circuits 111 to 118 described above are for the first track, and the circuits for the second track also include a selection circuit 119, a timing circuit 120, a data latch circuit 121, an FFM path for empty detection 122, Parallel/serial conversion circuit 123, selection circuit 124, J-KFF circuit 12
5, and a driver 126. However, the location where the timing circuit 120 operates in quinary is different.

As described above, the magnetism generating member control circuit 40 generates a magnetic field in accordance with the magnetic data of a predetermined credit card or cash card selectively read out from the data memory 31, thereby generating a magnetic field on the reading device side. A head (not shown) is provided with the same signals as when reading a conventional magnetic stripe.

Next, the inspection device will be explained using FIG. 12.

That is, the inspection device 13 has a contact probe 131.
By bringing the contact portion 11 into contact with the contact portion 11, the IC card 10 is connected to the internal circuit. This inspection device 130 diagnoses whether the internal circuit within the IC card 10 operates normally during manufacturing.

In such a configuration, the inspection process will be explained.

First, the internal circuit of the IC card 10 and the inspection device 130 are connected by bringing the contact probe 131 into contact with the contact section 11 . Then, the inspection device 13
A power supply voltage, a clock signal, and a reset signal are supplied from 0.

Next, the inspection device 130 outputs a transmission change command to the CPU 28 before loading the self-diagnosis program. As a result, the CPU 28 selects a sufficiently high transmission speed and also selects the loader program in the program ROM 29.

The reason for selecting the sufficiently high transmission speed is that a fairly large self-diagnosis program is transferred from the inspection device 130 to the IC.
This is to save loading time for loading data into the data memory 31 in the card 10. In this case, the electric circuit in the IC card 10 includes a communication control circuit 2.
1 and a baud rate generator, enabling high-speed communication of several Kpps.

Then, the CPU 28 outputs a program load command to the inspection device 130 using the loader program.

Then, the inspection device 130 reads the self-diagnosis program from an internal memory (not shown) and loads it into the data memory 31 in the IC card 10. Then, when the loading is completed, the inspection device 130 sends the self-diagnosis command to the CP.
Output to U28. Thereby, the CPU 28 executes diagnostic processing corresponding to the self-diagnosis program on the data memory 31. The results of the self-diagnosis are sent to the inspection device 1 as a response to the self-diagnosis start command from the CPO 28.
30.

In the above example, when loading the self-diagnosis program, no special qualification check is performed. By disabling the loading of , this feature will not be misused and will be safe.

As described above, the contents of the program ROM can be used for any purpose, and the contents of the loaded program can be changed freely, making it possible to construct a flexible system.

Next, the operation in such a configuration will be explained. First, we will explain the offline function used by the card alone. That is, by pressing the mode key 123, that is, the M1 key,
When the calculator mode is specified, it can be used as a calculator with the numeric keypad 12b and the four arithmetic operation keys 12.

Also, by pressing the mode key 12a, that is, the M2 key,
When the time display mode is specified, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and also reads the seconds, minutes, and hours from the counters 97 to 101 in the calendar circuit 33, and
The year, month, day, and day of the week for the display clock are read from , converted into a specified format, and output to the display control circuit 35 . As a result, the display unit control circuit 35 uses an internal character generator (not shown) to convert the character pattern into a character pattern, and uses the display unit driver 36 to convert the display unit 1 into a character pattern.
Display in 3.

Further, when the electronic width mode is specified using the mode key 12a, that is, the M3 key, the CPU 28 uses the data memory 31
The address, name, telephone number, etc. stored in the computer are read out and displayed on the display section 13. Further, when registering the above-mentioned address, name, etc. in the electronic space, the user uses, for example, the numeric keypad 12b. That is, rAJ is "1.1", rBJ is "1.2", rcJ is "1.3", and rDJ is "2.1".
,... can be specified by entering.

When the shopping mode is specified using the mode key 12a, that is, the M4 key, the type of contracted credit card or cash card is selected using the numeric keypad 12b.
and the type of output terminal, that is, whether the reading is manual or automatic. Then, the CPU 28 reads the data memory 31
The data (72 characters) corresponding to the selected credit card or cash card are read out and output to the magnetism generating member control circuit 40. Also, C.P.
U28 outputs a drive rate corresponding to the selection of manual type or automatic type to the magnetism generating member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40. As a result, the magnetism generating member control circuit 40 causes the magnetic head (not shown) on the reading device side to read a conventional magnetic stripe by generating a magnetic field from the magnetism generating member 41a according to the magnetic data of the credit. The same signal is provided as in the case. As a result, in shopping mode, it can be used as a conventional credit card.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. Accordingly, when an external power supply voltage is supplied via the contact portion 11, the power supply control circuit 23 switches from driving by the internal battery 25 to driving by the external power supply voltage, as described above. In addition, the reset control circuit 2
2 generates a reset signal and starts the CPU 28. After this activation, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. This online processing involves exchanging data and writing new data into the IC card 10 by updating data between the terminal 16 and the IC card 10.

As mentioned above, in the CPU program ROM,
Since only the load program for loading the self-diagnosis routine into the data memory in the IC card is stored and the self-diagnosis program is executed on the data memory, the ROM has a relatively small capacity loader program. ROM can be used effectively.

Although an IC card is used in the above embodiment, the IC card is not limited to these, and any card that has a data memory and a control element and selectively performs input/output from the outside may be used, and the shape is not card-like. , or other shapes such as a rod shape.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a portable medium that can effectively utilize a read-only memory in which a program for a control element is stored.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a diagram showing a schematic configuration of an electric circuit of an IC card, FIG. 2 is a plan view showing the configuration of an IC card, and FIG. 3 is a diagram showing an IC card. A diagram showing a terminal that handles cards, FIG. 4 is a diagram showing an example of the configuration of a power supply control circuit, FIG. 5 is a timing chart for explaining the operation of the main parts in FIG. 4, and FIG. 6 is a clock control circuit. 7 is a schematic block diagram of the calendar circuit, FIG. 8 is a diagram showing the output timing of signals from the frequency dividing circuit, and FIG. 9 is a diagram showing an example of the configuration of the magnetism generating member control circuit. , FIG. 10 and FIG. 11 are timing charts for explaining the operation of the main parts in FIG. 9, and FIG. 12 is a perspective view for explaining the relationship between the inspection device and the IC card. 10... IC card (portable medium), 11... Contact section (connection means), 12... Keyboard section (input means), 13... Display section (display means), 14...
Magnetism generating member, 16... terminal device (external device), 21.
...Communication control circuit, 23...Power supply control circuit, 25...
・Internal battery, 26... Clock control circuit, 27.
...Oscillator, 28...CPU (control element), 29.
...Program ROM (memory section), 31...Data memory (storage means), 33...Calendar circuit, 34
... Oscillator, 38 ... Keyboard interface, 40 ... Magnetism generating member control circuit (driving means), 67
...Oscillation circuit, 130...Inspection device, 131...
Contact probe. Applicant's agent Patent attorney Takehiko Suzue 10 Figure 3 Figure 4 Figure 5 Figure 70, Selection grid wo, trust '@10 Figure 11 Figure 2g12

Claims (2)

[Claims] (1) A portable medium that has the function of communicating with the outside via a contact part and has a control element, which includes a nonvolatile memory that stores data in a nonvolatile state, and a self-diagnosis program supplied from the outside. a memory unit storing a loader program to be loaded into a non-volatile memory; and means for storing the self-diagnosis program in the non-volatile memory using the loader program, and executing processing according to the program using the control element. A portable medium comprising: (2) The portable medium according to claim 1, wherein the self-diagnosis program is loaded after password verification.