JPS6352240A - Data processor - Google Patents

Abstract

PURPOSE:To process data at high speed via a context switching action or return by switching designation of register groups in response to a context switch and at the same time performing the saving control of contents so that at least one register group is always set in an idle state. CONSTITUTION:The using states of three register groups A-C are shown by a condition register CR. When a context switching action is carried out in application modes of both register groups A and B and in a non-application mode of the register group C, this group C is immediately used for execution of a program. In this case, the contents of the group B are held as they are and a direct memory access control circuit DMAC is started since all groups A-C are used. Thus the contents of the group A are saved to an external memory. These saved contents are sent back to the group A when the group C becomes idle.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, for example, a built-in RA
The present invention relates to a technique effective for use in a microprocessor having M.

[Conventional technology]

When a context skift occurs due to an interrupt or task switch, the microprocessor saves the contents of various registers used to execute the program before the above conskist switch occurs, or vice versa. Performs data processing to restore the contents of to the original register. Such data processing is performed using a stack (memory) and a stack pointer. Regarding saving/restoring such a register group,
For example, CQ Publishing ■ Published September 15, 1980 r Internal structure of microcomputer and machine language j Written by Kunio Fukunaga, page 1
63-196.

(Problem to be Solved by the Invention) When executing a program in which the above context switches occur frequently, time is spent saving and restoring the contents of the various registers, which slows down the actual data processing speed. Put it away.

An object of the present invention is to provide a microprocessor that improves data processing speed with context switching.

The above and other objects and novel features of this invention will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a register group consisting of multiple sets required for instruction execution, a pointer that specifies one register group used for instruction execution among the multiple sets, and information on the above register group is saved to an external storage device. The direct memory access control circuit has a built-in direct memory access opening circuit that switches the designation of the register group in response to a context switch, and also transfers the contents of the previously used register group to external memory using the direct memory access control circuit. This is done so that there is always a group of empty registers.

[For production]

According to the above-mentioned means, there is always one free register group as a result of the built-in direct memory access control circuit saving and restoring the contents between the external storage device and the register group. Data processing associated with switches and returns can be performed at high speed.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a microprocessor according to the present invention. Each of the circuit blocks constituting the microprocessor MPU (LSI) surrounded by dotted lines in the figure is a 5! of a known semiconductor integrated circuit. It is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon, depending on the manufacturing technology.

In this embodiment, in order to enable data processing with high-speed context switching, three sets of registers consisting of A to C are provided, although not particularly limited thereto. Each of these register groups A to C is divided and configured within an area of a built-in RAM. The above register groups A to C are program counters PCA to pcc, stack pointers SPA to spc, and various registers REA to RE necessary for executing instructions of a predetermined program, respectively.
C and pointers A to C.

Each of these register groups is connected to three internal buses B1 to B3.
It is connected to each of the following circuit units by a bus.

The arithmetic and logic operation unit (ALU) receives data from the bus B1 and a signal from a latch (accumulator) FF that takes in the data supplied via the bus B1, and performs control formed by decoding a command word. Perform arithmetic or logical operation according to the signal. This calculation result is the bus B2
is output to and taken into each of the above register groups.

Further, a data buffer DBI is provided for exchanging data with an external memory and the like. This data buffer DB
Although not particularly limited, data is transferred between bus B1 and bidirectional data buffer DAB. That is, data on the external data bus read from an external memory or the like is taken in by the bidirectional data buffer DAB. Signal D of this bidirectional data buffer DAB
I is connected to the internal bus B1 via the data buffer DBI.
sent to. Conversely, the arithmetic operation unit A as above
Data on the internal bus Bl generated by calculations by the LU and to be sent to an external memory device or the like is taken into the data buffer DBI. The data is then sent onto the external bus via the bidirectional data buffer DAB. On the other hand, the address signal on bus Bl is sent to address buffer A.
B2 and the address output circuit ADB to the external bus. This allows access to external memory devices and input/output devices.

Further, the command words of the program stored in the external memory device are taken into the bidirectional data buffer DAB. This instruction word is sent to the instruction register IR. The instruction word taken into the instruction register IR is supplied to a microprogram ROM (hereinafter simply referred to as mROM).

This mROM is used to read microinstructions consisting of a plurality of steps according to the instruction word.

This microinstruction is fed on the one hand to the decoder DCR, which transfers the data via the internal bus,
Generates various control signals and timing signals necessary for operation of various registers and operation of arithmetic and logic unit (ALU). Furthermore, the microinstructions mentioned above are fed back to the input side on the other hand and are used for conditional jumps and next address designation. In this way, a macroinstruction supplied from an external memory or the like is executed by a microinstruction consisting of multiple steps stored in the mROM.

Also, when the interrupt circuit INT receives the interrupt,
Access condition register CR. The condition register CR holds the following three states, respectively, corresponding to the register groups 1 to C, and instructs the execution of instructions according to the states. One of the above states is currently in use, another is in use immediately before the currently running program, and yet another is free. be.

When there is an interrupt from the interrupt circuit INT, the condesidine register CR instructs the instruction decoder DCR to access the vacant register group according to the state.

In this embodiment, a direct memory access control circuit DMAC is included in order to create one register group that is always empty among the three register groups. This direct memory access control circuit DMAC uses address buffer AB2 to save the contents of the register group to be made vacant to an external memory (stack area) or restore the saved contents to the register group. A data buffer DB2 and an internal bus B3 are provided.

That is, the internal bus B3 connects each of the register groups A to C with the address buffer AB2 and data buffer DB2. These address buffers AB2
and data buffer DB2 output the address output circuit A according to instructions from the direct memory access control circuit DMAC.
DB and bidirectional data buffer DB2.

The operation of the microprocessor according to this embodiment with context switching due to interrupts, task switching, etc. will now be described with reference to the operational schematic diagram shown in FIG.

Initially, all three register groups are empty, so
For example, assume that register group A is in use. In this state, the condition register CR indicates that register group A is currently in use and the other two register groups B and C are free.

Next, when the first context switch occurs,
Since there are two free register groups B and C, the program is immediately executed using register group B in a predetermined order. At this time, the contents of the register group A used for the previous program execution are retained as they are, and the condesidine register CR contains the following information:
A state (old) in which the contents of the previous program during execution are saved is written to register group A. In this way, the state of the register group as shown in the figure is created.

If a second context switch occurs in this state, since there is one free register group C, the program is immediately executed using this register group C. At this time, the contents of register group B that were used to execute the previous program are retained as they are, and the condition register CR is in a state where the contents of register group B during the previous program execution are saved. (old) becomes obsolete. Then, in order to create a group of empty registers, the microprocessor MPU opens the external data bus and operates only with its internal circuitry, by using the period when the microprocessor MPU directly accesses the memory access control circuit DMA.
C is activated, and the contents of the register group A are saved in the external memory device RAM using address buffer ABZ and data buffer DB2. As a result, when the register group A becomes vacant, a notification to that effect is written to the condition register CR. Thereafter, when a context switch occurs in stages, a program is executed using the empty register group as described above, and the contents of the register group to be made empty are saved to the memory device RAM each time.

Conversely, if you return from a program using register group C to a program using register group B in FIG. 2, there will be two empty register groups, C and A. In this case, the above register group At A, the above-mentioned saved contents are restored by the direct memory access control circuit DM to C using the period when the external bus is open.

Note that if the next context switch occurs before the entire contents of the register group are saved by the direct memory access control circuit DMAC, the data transfer by the direct memory access control circuit DMAC is given top priority. Ru.

In this embodiment, a plurality of register groups are provided as described above, and by saving the contents of previously used register groups to an external memory device using the built-in direct memory access control device DMAC, one free space is always available. This is to ensure that a group of state registers exists. As a result, using the vacant register group, a program can be immediately executed in response to a context switch due to an interrupt, task switching, or the like. Therefore, it is possible to speed up the data processing associated with the above-mentioned context switch.

Furthermore, since the register groups are allocated by dividing the memory area of the built-in RAM, it is possible to arrange a large number of register groups with high density.

The effects obtained from the above examples are as follows. That is, (1) a register group consisting of multiple sets required for instruction execution, and a condition register that holds the usage status of the multiple register groups and specifies one register group used for instruction execution. , has a built-in direct memory access control circuit that saves the information of the above register group to an external storage device, switches the designation of the above register group in response to a context switch or return, and also saves the contents of the previously used register group. is saved in an external storage device by the direct memory access control circuit so that there is always a group of empty registers. As a result, there is always one register group in an empty state, so it is possible to achieve the effect that data processing accompanying a context switch or return can be performed at high speed.

(2) By configuring the above register group using a built-in RAM, it is possible to achieve the effect that a large number of register groups can be mounted on a semiconductor substrate at high density.

(3) The above register group consists of three sets, and they are allocated as follows: the register group used to execute the previous program, the register group used to execute the current program, and the register group that is free. As a result, it is possible to efficiently perform bidirectional data processing of switching and return using a minimum number of register groups.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Also. For example, the number of register groups may be at least two. In this case, when a context switch occurs, data processing is performed immediately using the free register group, and during the data processing period, the contents of the register group used in the previous program by the direct memory access control circuit are saved. That's fine. If the next context switch occurs before the direct memory access control circuit finishes saving the register group, the data should be saved with the highest priority.Furthermore, four or more sets of the above register groups are provided. In this case, 2
It is possible to quickly return to a program from two or more previous programs, and it is possible to provide sufficient time for saving and restoring the contents of the register group that controls direct memory access.

In addition to being configured using the built-in RAM, the register group may be configured by independent circuits. Furthermore, the method for controlling switching of the register group may be performed in various embodiments. can be taken.

Further, the number and arrangement of internal buses that connect the plurality of register groups to the arithmetic and logic operation units, each buffer, etc. can take various embodiments.

The present invention is applicable not only to microprocessors but also to data processing devices.

〔Effect of the invention〕

Is it required for command execution? ,! A condition register that holds the usage status of the plurality of register groups and specifies one register group to be used for executing an instruction, and stores the information of the register group in an external storage device. A direct memory access control circuit for saving is provided, and the designation of the register group is switched in response to a context switch or return, and the contents of the previously used register group are transferred to external storage by the direct memory access control circuit. The registers are saved in the device so that there is always a group of registers in an empty state. As a result, there is always one free register group, so data processing associated with context switches and returns can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining an example of its operation. MPU...Micro processor sensor, A-B...Register group, PCA~PCC...Program counter, 5PA-3
PC: stack pointer, REA-RPC: various registers, ALU: arithmetic logic unit, FF: launch circuit, DBI. DB2...data buffer, ABl, AB2...address buffer, B1-B3...internal bus, DAB...bidirectional data buffer, ADB...address output circuit, IR
・・Instruction register, m ROM・・Micro program ROM, DCR・・Decoder, INT・・Interrupt circuit, CR・・Condition register, DMAC・・Direct memory access control circuit

Claims (1)

[Scope of Claims] 1. Storage means required for instruction execution, a condition register indicating the usage status of the storage means, and a predetermined storage area in the storage means used for the previous instruction execution. What is claimed is: 1. A data processing device comprising means for selectively evacuating data. 2. The data processing device according to claim 1, wherein the storage means is constituted by a plurality of register groups. 3. Three sets of the above register groups are provided, and when a certain program is executed, one register group currently in use,
The direct memory access control circuit controls the connection between the external storage device and the register group so that there is one register group that stores the state of the program immediately before a context switch or return occurred, and one register group that is free. 3. The data processing apparatus according to claim 2, wherein the data processing apparatus performs evacuation and recovery operations between the data processing apparatus and the data processing apparatus.