JPS6352808B2 - - Google Patents

Description

[Detailed description of the invention]

This invention is a DA that converts digital data into an analog signal (DC signal) corresponding to its size.
Regarding converters, especially pulse width modulation type (PWM type)
Regarding DA converters. Generally, a PWM type DA converter compares the input digital data to be converted with a reference digital value that changes within the conversion cycle, and uses the comparison result to generate a pulse signal (PWM wave) with a pulse width corresponding to the size of the input digital data. is generated and smoothed to obtain an output DC signal. This type of DA converter has the advantage that the conversion accuracy can be easily improved by increasing the number of bits of the reference digital value, and is suitable for integrated circuits, so it is often used especially for motor servo control. ing. but
In PWM type DA converters, the output DC signal is determined after one cycle of the reference digital value, and because it passes through a low-pass filter for smoothing, the conversion speed is slower compared to DA converters using other methods. ,
There were drawbacks such as incomplete smoothing and a tendency to generate ripple components. An object of the present invention is to provide a DA conversion circuit that eliminates the above-mentioned drawbacks. According to this invention, a plurality of digital value strings formed corresponding to digital values that change within a conversion period are appropriately distributed and sequentially generated within a conversion period, and this digital value string is compared with input digital data. hand
It is designed to generate PWM waves. This makes it possible to set the cutoff frequency of the low-pass filter for PWM wave smoothing significantly higher than in conventional circuits, improving conversion speed and
It is possible to effectively attenuate the ripple component of the PWM wave and obtain high-quality DC output. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, the conversion principle of this invention will be explained with reference to FIGS. 1 and 2. Figure 1 shows DA using conventional equipment.
This shows the conversion principle, and compares the digital values (indicated by a staircase wave) that are sequentially generated within the conversion period W ₀ with the input digital data (indicated by a straight line). A PWM wave with a pulse width W is generated in the
By smoothing the PWM wave, a DC signal proportional to W/W ₀ is obtained. On the other hand, the principle of DA conversion according to the present invention is shown in FIG. In this invention, as shown in Fig. 2, n rows of digital values (indicated by staircase waves 1, 2...m) are sequentially generated within a conversion period _W0 , and these digital values and input digital data (indicated by a straight line) are Compare staircase wave 1,
2... A pulse signal of a predetermined width is generated in an area where m is smaller or larger than a straight line. Here, the staircase waves 1, 2...m are formed corresponding to the digital values shown by the staircase waves in Fig. 1, each having a different weighting value, and these are appropriately distributed and generated. . In this case, m pulses are generated within the conversion period, and the cutoff frequency of the low-pass filter for smoothing the PWM wave can be increased approximately m times. FIG. 3 shows an embodiment of the DA converter according to the present invention, in which a clock pulse of a predetermined frequency is used.
Up counter type 10 with CK as count input
A bit binary counter 1, a comparator circuit 2 that compares two binary values and generates a large-discrimination output, and 10 that temporarily stores the 10-bit digital data DD to be converted.
It has 3 bit registers. A 10-bit binary counter 1 counts the input clock pulses CK and generates a 10-bit binary number that increases sequentially. Now, if we assume that the contents of each bit of this 10-bit binary number are Q ₀ , Q ₁ ...Q ₉ from the lower bit side, the contents of the lower 6 bits Q ₀ , Q ₁ ...Q ₅ are stored in the upper order of the comparator circuit 2 in this order. The contents of the upper 4 bits are added to the 6 bits.
Q ₆ to _{Q 9} are added to the lower 4 bits of comparator circuit 2 in reverse order. In this way, comparison circuit 2
The binary values to input are Q ₉ ×2 ⁰ +Q ₈ ×2 ¹ +Q ₇ ×2 ² +Q ₆ ×2 ³ +Q ₆ ×2 ⁴ +Q ₁ ×2 ⁵ +
Q ₂ ×2 ⁶ +Q ₃ ×2 ⁷ +Q ₄ ×2 ⁸ +Q ₅ ×2 ⁹ = (Q ₉ ×2 ⁰ +Q ₈ ×2 ¹ +Q ₇ ×2 ² +Q ₆ ×2 ³ ) +2 ⁴ (Q ₀ ×2 ⁰ +Q ₁ ×2 ¹ +Q ₂ ×2 ² +Q ₃ ×2 ³ +Q ₄ ×2 ⁴ +
Q ₅ ×2 ⁵ ). That is, as shown in Figure 4, these binary values form a sequence of ²⁴ binary values (indicated by staircase waves 1 to 16) of ²⁶ steps in units of ²⁴ . Different weighting values (Q ₉ × 2 ⁰ + Q ₃ ×
2 ¹ +Q ₇ ×2 ² +Q ₆ ×2 ³ ), and this weighting value is shown in a table based on the relationship with the contents Q ₆ to ^{Q 9} as follows.

【table】

[Table] In other words, the weighting values of each binary value string are arranged so that their sizes have maximum variance. On the other hand, the digital data DD to be converted is temporarily stored in the register 3 by the load signal LO,
It is added to the comparison circuit 2. The comparison circuit 2 sequentially compares this digital data DD with the binary value string added from the binary counter 1, and generates a magnitude discrimination output. Here, the magnitude discrimination output generated from the comparator circuit 2 differs by one step depending on the weighting value of the binary value strings to be compared. , for example, the digital data DD to be converted is 555 = 2 ⁹ +
Assuming that 2 ⁵ + 2 ³ + ^{2 1} + 2 ⁰ = 11 + 2 ⁴ × 34, the size discrimination output generated from the comparator circuit 2 will be 34 steps with respect to the binary value string with a weight value of 11 or less. This results in 34 steps plus one step (34+1) for the binary value sequence. This is shown in order with reference to the table above: (34+1), (34+1), (34+1), 34, (34+1)
,
(34+1), (34+1), 34, (34+1), (34+1)
,
(34+1), 34, (34+1), 34. In other words, the comparison circuit 2 generates a large/small discrimination output in almost 35 steps, and at the position of the maximum dispersion of the conversion period,
The size discrimination output will be generated in 34 steps. In this case, a pulse with a pulse width having information of 35/2 ⁶ = 0.5469 (100.9%) for the DA conversion true value 255/210 = 0.541992 can be obtained in 1/16 of the conversion period, and -1 /2 ⁶ × 1/4 = -0.00391 (-0.7%) every 1/4 hour of the pulse conversion period of the pulse width that includes correction information of -1/2 ⁶ × 1/4 = -0.00098 (-0.2%) ) are obtained every conversion period. In addition, in the above embodiment, the weighting value of each binary value string is generated within one cycle of each staircase wave.
It is not necessarily limited to this. For example, the same effect can be obtained even if the period is set to span two periods. Another embodiment of the present invention shown in FIG. 5 is constructed in consideration of the above points. In this embodiment, a 6-bit binary counter 11 receives the clock pulse CK as a count input, a 4-bit binary counter 12, a latch circuit 13 that latches the output of the 4-bit binary counter 12, and a 6-bit binary counter 11. The count pulse CP for the 4-bit binary counter 12 and the latch pulse for the latch circuit 13 are monitored.
It includes a gate circuit 14 that generates LP. That is, assuming that the period of each staircase wave is as shown in FIG. 6a, the gate circuit 14 first generates a count pulse CP at the timing shown in FIG. count value 1
The latch pulse continues to advance at the timing shown in Figure 6 c.
LP is generated, and the count value of the 4-bit binary counter 12 is latched into the latch circuit 13 by this latch pulse LP. The output bit contents Q ₆ to _{Q 5} of the 6-bit binary counter 11 are added as they are to the upper 6 bits of the 10-bit comparison circuit 2, and the contents of the latch of the latch circuit 13 are reversed in bit order and added to the 10-bit comparison circuit 2. It is added to the lower 4 bits of 2. The other configurations are the same as in FIG. 3. In FIG. 5, the same reference numerals as in FIG. 3 are used for the parts common to those in FIG. 3 for convenience of explanation. According to such a configuration, the weighting value of each staircase wave is determined by the gate circuit 14.
It will change when a ratte signal is generated from , but all the weighting values will be taken in one cycle of conversion. As can be easily seen, in this embodiment, 4 bits 2 are stored in approximately one period of each staircase wave.
Since it is only necessary to establish the output data of the binary counter 12, the operating speed of the 4-bit binary counter 12 can be changed to 6-bit binary counter 12.
Compared to the decimal counter 11, it can be significantly reduced. Still another embodiment of the invention is shown in FIG.
This embodiment uses the 10-bit comparator circuit 2 shown in FIG.
Instead, a 4-bit comparison circuit 21 compares the contents of the lower 4 bits and 6 compares the contents of the upper 6 bits.
A bit comparison circuit 22 is provided, and a 4-bit comparison circuit 2 is provided.
1, the signal obtained by reversing the order of the output bits of the 4-bit binary counter 12 is compared with the contents of the lower 4 bits of the binary number to be converted, and the magnitude comparison output is sent to the latch output from the gate circuit 14. The signal CP is configured to be latched in a latch circuit 23 and supplied to a 6-bit comparator circuit 22. Here, the comparison circuit 22 outputs its comparison output preferentially, and outputs the comparison output of the comparison circuit 21 only when the comparison contents match. By the way, since the digital data DD to be converted within the conversion period is constant, the weighting of each staircase wave changes when a latch pulse is generated from the gate circuit 14, as in the embodiment shown in FIG. ,output
The PWM wave is the same as the embodiment shown in FIG.
In this embodiment, the 4-bit binary counter 12 is also used for the same reason as described in the embodiment shown in FIG.
Also, the operating speed of the 4-bit comparison circuit 21 can be significantly reduced. In addition, in the above embodiments, the 10-bit
Although the present invention is applied to a PWM type DA converter, it is obvious that it can be applied to any bit PWM type DA converter. Furthermore, although the number of generated bits of each staircase wave and the number of bits of weighted value generation are divided into 6 bits and 4 bits, respectively, the present invention is not limited to this. That is, this division can be arbitrarily selected depending on the purpose. Further, although the construction of the binary counter and comparison circuit is not described in detail, they can be constructed using any known circuit. Furthermore, in the above embodiment, the binary counter is constructed with an up counter, so that the generated staircase wave has a sawtooth waveform, but if this is constructed with an updown counter, a triangular staircase wave can be obtained. In this case as well, DA
It is possible to configure a converter. Furthermore, a down counter or a synchronous counter can also be used as the binary counter.

[Brief explanation of the drawing]

Fig. 1 is a timing chart showing the DA conversion principle of a conventional PWM type DA converter, Fig. 2 is a timing chart showing the DA conversion principle of a DA converter according to the present invention, and Fig. 3 is an embodiment of the present invention. 4 is a timing chart explaining its operation. FIG. 5 is a block diagram showing another embodiment of the present invention. FIG. 6 is a timing chart explaining its operation. FIG. 7 is a timing chart explaining its operation. FIG. 7 is a block diagram showing still another embodiment of the invention. 1, 11, 12... Binary counter, 2... Comparison circuit, 3... Register, 13, 23... Latch circuit, 14... Gate circuit.

Claims (1)

[Claims] 1. An n-bit binary counter that counts pulses of a predetermined frequency; n-1<N) a binary counter, and a first latching value of the N-bit binary counter each time the count value of the N-bit binary counter reaches a second set value. a latch circuit, a first comparator circuit that compares the data obtained by reversing the order of the data of the first latch circuit and data of the lower N-n bits of the N-bit input digital data, and the n-bit binary counter. The count value is compared with the upper n bits of the N-bit input digital data, the comparison result is output with priority over the output of the first comparison circuit, and only when the comparison results match, the first comparison circuit is output. A DA conversion circuit comprising: a second comparison circuit that outputs the output of the comparison circuit; and means for smoothing the output of the second comparison circuit. 2. An n-bit binary counter that counts pulses of a predetermined frequency, and an N-n bit that counts by 1 each time the count value of this n-bit binary counter reaches a first set value (n-1<N). A binary counter, data obtained by reversing the order of the counted values of this N-n bit binary counter, and N
a first comparator circuit that compares the data of lower N-n bits of the bit input digital data; and a first comparator circuit that compares the data of the lower N-n bits of the bit input digital data; The second latches the output.
compares the count value of the n-bit binary counter with the upper n bits of the N-bit input digital data, and outputs the comparison result in priority to the output of the second latch circuit; A DA conversion circuit comprising: a second comparison circuit that outputs the output of the second latch circuit only when the comparison results match; and means for smoothing the output of the second comparison circuit.