JPS6344769A - Field effect transistor and manufacture of the same - Google Patents

Abstract

PURPOSE:To avoid a hot electron effect and gm deterioration and obtain a highly reliable field effect transistor by a method wherein both end parts of a gate insulating film are made thicker than the other parts and source and drain diffused layers composed of double-layer structures are provided so as not to overlap the part of the gate insulating film where the thickness is thin. CONSTITUTION:Low concentration layers 4 are provided closer to a gate electrode 3 than high concentration layers 6 and those two types of layers form double-layer diffused structures. Hot oxidation is applied form the outside of the gate electrode 3 to make the side end parts of a gate insulating film 2 provided between the gate electtrode 3 and a substrate 1 thicker than the other parts. At that time, conditions such as oxidation time and temperature are so selected as to make the oxide film 2 growing thicker gradually from the upper parts of the side ends of the low concentration layers 4 toward the outside parts. With this constitution, as both the end parts of the gate insulating film are made thicker than the other parts and the source and drain diffused layers have double-layer diffused structures, the electric field intensity near the drain is relaxed by the low concentration layer 4 and, moreover, even if created hot electrons are trapped by the gate insulating film 2, the negative potential of the electrons can be neutralized by the positive potential of the gate electrode above the insulating film.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of the gate electrode and source/drain diffusion layer of a field effect transistor (commonly known as MO3Tr) for suppressing the real carrier effect. be.

[Conventional technology]

Figure 2 shows the conventional name LDD: Lightly Doped.
Lightly Doped Drain
) shows the cross-sectional structure of MOSTr in the order of steps. In the figure, 1 is a silicon base film, 2 is a color border film to the gate, 3 is a gate electrode, 4 is a low concentration source/drain diffusion layer, 5 is a side wall, and 6 is a high concentration source/drain layer.
This is a drain diffusion layer.

Next, the manufacturing method will be explained.

After forming a conductive material such as polycrystalline silicon or high melting point metal on the substrate 1 via the gate insulating film 2,
The conductive material is selectively processed by a known method using a plasma reaction to form the gate electrode 3 (FIG. 2 [51])
.

Next, a non-conductor of the opposite conductivity type to the substrate 1 is
Ion implantation is applied to the surface of the substrate 10 at a concentration of about lXIQ''/'cd. At this time, ions, for example of N type Then, an N- diffusion layer 4 is formed.

Next, after forming an insulating film such as a silicon oxide film on the entire surface with a constant thickness, so-called anisotropic etching with directionality such as ion etching is performed on the entire surface to form sidewalls on the vertical side walls of the gate electrode 3. A silicon oxide film called wall 5 is formed.

Thereafter, a high concentration source/drain diffusion layer 6 is formed by ion-implanting impurities of type 4 with conductivity opposite to that of the substrate at a high concentration (I x 10''/ci or more) over the entire surface and by applying high temperature heat treatment. form (Figure 2 (g))).

At this time, the high concentration source/drain diffusion layer 6 is formed in a self-aligned manner using the sidewall 5 as a mask, so that it is formed so as not to protrude from the edge of the low concentration impurity diffusion layer 4, resulting in a double diffusion layer structure. is obtained. MO3T with this structure
With r, the strong electric field near the drain can be weakened and the hot electron effect can be suppressed.

[Problem that the invention seeks to solve]

However, the number of steps required to form the sidewalls increases.

In addition to problems such as difficulty in controlling the sidewall width, the problem of GM deterioration due to this structure has recently become clear. That is, as schematically shown in FIG. 2(C), hot electrons generated by a strong electric field near the drain are trapped in the sidewall 5 on the side wall of the gate 3, and these trapped electrons cause the low-4 degree source/drain layer 4 to be trapped. This is a phenomenon in which the surface of the MOS transistor becomes more likely to be inverted to P type, effectively lowering the N- concentration, increasing the source resistance of the MOS transistor, and deteriorating the gm, etc.

The present invention was made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a field effect transistor with high signal chain properties that can prevent the hot electron effect and GM deterioration, and a method for manufacturing the same.

[Means for solving problems]

The field effect transistor according to the first invention of the present application includes:
Both ends of the gate insulating film are made thicker, and double diffusion source/drain layers are provided in a T-shaped transparent earthen structure that do not overlap with the thinner parts of the gate insulating film.

In the method for manufacturing a field effect transistor according to the second invention of the present application, after forming a gate electrode on a substrate via an insulating film, ions of the same type or different types are implanted to form a double source/drain diffusion layer. Then, the gate electrode is thermally oxidized from the outside to grow thicker both ends of the gate insulating film.

[Effect]

In the first invention of the present application, both end portions of the gate insulating film are thickened22, and the upper double diffusion source/drain layers are provided so as not to overlap with the thin portions of the gate insulating film. There is no additional capacitance between the source and the drain, so the electric field strength near the drain is relaxed, and even if hot electrons are trapped in the gate insulating film, the negative potential of the electrons can be neutralized by the positive potential of the gate electrode.

In the second invention of the present application, since the gate insulating film is oxidized from the outside of the gate electrode, the side portions of the gate insulating film can be easily and reliably thickened.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the cross-sectional structure of an MOS transistor according to an embodiment of the present invention in the order of steps. The gate electrode formed above, 4 is a low 23 degree source/drain diffusion layer, and 6 is a high concentration source/drain diffusion layer formed continuously with the nucleus layer 4 outside the nucleus layer 4 with respect to the gate electrode 3. It is.

Next, the manufacturing method will be explained.

After forming the gate insulating film 2 on the silicon base vi1,
Ge) is used to form paddy for pole 3. This material may be either a single layer film of polycrystalline silicon or a high melting point metal, or a multilayer film of two or more layers containing both.

After forming the gate electrode 3 by processing this electrode material using a known etching method, impurities of the opposite conductivity type to the substrate 1 are ion-implanted at a low concentration (1×10+2/cIa to 1×10'4/-). to form a low concentration diffusion layer 4 (see FIG. 1),
Next, impurities of the same conductivity type as the above impurities were added at a high concentration (5X1
01 to lXl01b/cut) to form a high concentration diffusion layer 6 (FIG. 1(g))). At this time, the low concentration layer 4 and the high concentration layer 6 are continuous with each other, and the low concentration layer 4
Conditions such as impurity elements and heat treatment are set so that N4 is inside the high-4 degree layer 6, that is, a double diffusion structure is formed in which the low concentration N4 is closer to the gate electrode 3 than the high concentration layer.

Next, thermal oxidation is performed from the outside of the gate electrode 3 to thicken the side end portions of the gate insulating film 2 between the gate electrode 3 and the substrate 1 (FIG. 1(C)). Here, the oxidation time, IA degree, etc. are selected so that the oxide film 2 gradually becomes thicker from the upper side end of the low 4 degree diffusion layer 4 toward the outside, that is, toward the high concentration layer 6 side. As a result, the thickness of the gate insulating film 2 corresponding to the effective channel length (Leff), which determines the characteristics of MO3Tr, remains the same as the initially set thickness, and basic characteristics such as gm can be obtained as designed values. Can be done.

In this way, in this embodiment, both ends of the gate insulating film are thickened and the source/drain diffusion layers have a double diffusion structure, so the electric field strength near the drain is relaxed by the low concentration layer 4.
Furthermore, even if the generated hot electrons are trapped in the gate insulating film 2, since the gate electrode 3 is located above it, the negative potential of the electrons can be neutralized by the positive potential of the gate electrode), which has been a problem in the past. It is possible to prevent gm deterioration due to trapped electrons. Furthermore, since the gate insulating film is oxidized from the outside of the gate electrode, the side portions of the gate insulating film can be easily and reliably thickened.

Note that the present invention applies to either N-type or P-type MO3Tr.
Furthermore, it can be applied not only to a single substrate but also to an epitaxial layer or MO3Tr formed on a wafer, and in this case, the same effects as in the above embodiment can be obtained. It goes without saying that the present invention can also be applied to compound semiconductors other than silicon semiconductors.

Furthermore, in the above embodiment, the case where the source/drain layer has a double diffusion structure has been described, but the highly doped source/drain layer is used to lower the source/drain resistance and the contact resistance with the source/drain electrode. It forms
For example, if a low resistance method such as siliciding the surface is used, or if there is no need to reduce the resistance, the high concentration source/drain layer is not necessary.In these cases, the source/drain diffusion layer is A single layer structure of low concentration source/drain diffusion layers may be used.

〔Effect of the invention〕

As described above, according to the first invention of the present application, the side edges of the gate insulating film under the gate electrode are thickened, a low concentration diffusion layer is provided under the thick part of the gate insulating film, and a high concentration diffusion layer is provided outside the thick part of the gate insulating film. Since the layers are formed continuously, it is possible to not only suppress the generation of hot carriers near the drain (but also prevent GM deterioration caused by carriers trapped in the insulating film, making it possible to create a highly reliable field effect transistor. Obtainable.

Further, according to the second invention of the present application, since the gate insulating film is oxidized from the outside of the gate electrode, it is possible to easily and reliably manufacture a MOS transistor with thick side edges of the gate insulating film.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the cross-sectional structure of MO3r according to an embodiment of the present invention in the order of steps, and FIG. 2 is a diagram showing a conventional LDD type MOS.
It is a figure which shows the cross-sectional structure of T r in order of process. In the figure, 1 is a silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a low-1 degree source/drain diffusion layer, and 6 is a high concentration source/drain diffusion layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (6)

[Claims] (1) In a field effect transistor, a gate insulating film is formed in a predetermined region on a substrate, and its side edges are thicker in the center, a gate electrode formed on the gate insulating film, and both sides of the gate electrode. 1. A field effect transistor characterized by comprising a source/drain diffusion layer formed on the surface of a substrate so as not to overlap with a thin portion of a gate insulating film. (2) A patent characterized in that the gate electrode has a single-layer structure made of polycrystalline silicon, a high-melting point metal, or a silicide thereof, or a two-layer structure made of both polycrystalline silicon and a high-melting point metal, or their silicides. A field effect transistor according to claim 1. (3) The source/drain layer includes a low-concentration diffusion layer formed close to the gate electrode and a high-concentration diffusion layer thicker than the low-concentration diffusion layer and continuous with the low-concentration diffusion layer and slightly separated from the gate electrode. 3. The field effect transistor according to claim 1, wherein the field effect transistor has a double diffusion layer structure. (4) The impurity concentration of the above low concentration diffusion layer is 1×10^1^
2/cm^2 to 4 x 10^1^4/cm^2, and the impurity concentration of the high concentration diffusion layer is 5 x 10^1^
4/cm^2 to 1x10^1^6/cm^2. (5) In a method for manufacturing a field effect transistor, a first step of forming a gate insulating film on a semiconductor substrate, forming a gate electrode material thereon, and then selectively etching the gate electrode material. After forming the gate electrode,
The second step is to form source/drain diffusion layers by injecting impurities onto the substrate on both sides of the gate electrode, and then thermal oxidation is performed from the outside of the gate electrode to grow the side edges of the gate insulating film thicker than the center. A method for manufacturing a field effect transistor, comprising a third step of: (6) In the second step, ions of the same or different types are implanted into the substrate on both sides of the gate electrode to form a low concentration diffusion layer close to the gate electrode, and a high concentration diffusion layer slightly away from the gate electrode. 6. The method of manufacturing a field effect transistor according to claim 5, further comprising forming double diffused source/drain layers separately from each other.