JPS63292667A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a steep step in a wiring configuration and to obtain homogeneous characteristics in the entire region of a cell array, by providing an auxiliary conductor material, which is separated from a conductor material at the end part of the cell array by the substantially same interval as the mutual interval between the conductor materials in the cell array region. CONSTITUTION:A dummy or auxiliary electrode material 1 is formed so as to surround a cell array 5. The dummy electrode material 1 has the same width as that of an electrode material 2 of the cell array 5. The electrode material is separated from the end part in the width direction and from the end part in the longitudinal direction of the electrode material 2 by the same interval as the interval between said electrode materials. The pattern of the dummy electrode material 1 is formed at the same time when a mask pattern is formed in order to form the electrode material 2. In this way, the dummy electrode 1 can be formed at the same time as the electrode material 2. Thereafter an insulating film 7 is formed. The sufficiently thick insulating film 7 is formed in a region between the electrode material 2 and the dummy electrode 1 as well as a region between the electrode materials 2 in the cell array 5. An element at the end part of the cell array 5 has the excellent characteristics as an element in the cell array 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS semiconductor device such as an insulated gate field effect transistor in a large-scale integrated circuit device.

[Prior art] In recent years, insulated gate field effect transistors (MISS
FETs) are becoming increasingly finer, and their degree of integration is increasing. In order to achieve high integration of this semiconductor device, in addition to miniaturizing each active element, it is also necessary to miniaturize an inter-element isolation region that separates each element.

For this reason, various element isolation techniques have been developed and proposed.

By the way, as a typical conventional element isolation technology, LOG
There is an element isolation technology using selective oxidation called O8 technology. However, this element isolation technology using LOCO3 has a disadvantage in that the width of the transition region from the active region to the element isolation region, that is, the bird's beak, is large, and this becomes an obstacle to high integration. This impediment to high integration becomes particularly serious in memory cell arrays where large amounts of small active elements must be integrated.

Therefore, as a means to overcome this drawback, a technique has been proposed in which a field insulating film is formed by embedding an insulating film between electrode materials, as shown in FIGS. 4(a) to 4(d). .

A method of forming this field insulating film will be described below with reference to FIGS. 4(a) to 4(d).

First, as shown in FIG. 4(a), a gate insulating film 22 is formed on a semiconductor substrate 21, and then a gate electrode film 23 is formed. Next, as shown in FIG. 4(b), a mask pattern defining an active region is formed using a photoresist technique, and then the gate electrode film 23 is etched to form an electrode pattern 24. After that, this electrode pattern 24
Using as a mask, a channel cut impurity is introduced into the substrate 21 to form a channel cut region 25.

Next, as shown in FIG. 4C, an insulating film 26 is grown by, for example, bias sputter deposition. In this case, the gate electrode pattern 24 is covered with an insulating film 26, but this insulating film 26 is formed thinly on the pattern 24 and thickly between the patterns 24.

Next, as shown in FIG. 4(d), the insulating film 26 is etched so that the surface of the gate electrode pattern 24 is exposed. Thereafter, a wiring material film 27 is formed.

In this way, by embedding an insulator between the patterns formed of the electrode material in the active region and using this as a field insulating film, it is possible to solve the problem of birthbeak associated with the LOCO3 oxidation technology mentioned above, and improve memory cell arrays. High integration becomes possible.

[Problems to be Solved by the Invention] However, in the semiconductor device in which the above-described field insulating film 26 is formed, as shown in FIG. 5(a),
In the memory cell array interior 28 where the electrode patterns 24 are regularly and densely formed, the insulating film 26 is well embedded in the areas between the patterns 24, but in the cell array end 29 where the patterns are sparse, the insulating film 26 is is not formed sufficiently and becomes thin. For this reason, Figure 5 (
As shown in b), when the wiring material film 27 is formed on the insulating film 26 and further elements are formed, the cell array end 2
Since the field insulating film 26 in the device No. 9 is thinner, the subthreshold voltage of the parasitic transistor is lowered. Moreover, since a sharp step occurs in the insulating film 26 and the wiring layer 30 at the cell array end 29, the wiring shape deteriorates. Therefore, there is a drawback that the characteristics of the elements at the end of the cell array are worse than those of the elements inside the cell array.

The present invention has been made in view of the above circumstances, and it prevents the characteristics of the elements from deteriorating even at the ends of the cell array, and prevents sudden steps from forming in the wiring shape.
It is an object of the present invention to provide an MO8 type semiconductor device that can obtain uniform characteristics in the entire region of a cell array.

[Means for Solving the Problems] A MOS semiconductor device according to the present invention includes a semiconductor substrate having:
In a MOS type semiconductor device having a cell array region configured by arranging a plurality of conductive materials at regular intervals through an insulating film and embedding an insulating film between each conductive material to form a field insulating film, placed outside the cell array area,
The present invention is characterized in that it has an auxiliary conductive material spaced apart from the conductive material at the end of the cell array region at substantially the same distance as the mutual distance between the conductive material groups in the cell array region.

[Function] In the present invention, the auxiliary conductive material is spaced apart from the conductive material at the end of the cell array region at substantially the same distance as the mutual spacing between the conductive materials in the cell array region, and is disposed outside the cell array region. has been done. Therefore, when an insulating film is formed on the conductive material and the semiconductor substrate, a sufficiently thick insulating film is formed between the conductive material and the auxiliary conductive material at the end of the cell array, as well as between the conductive materials inside the cell array. be done. This makes it possible to form uniform elements up to the ends of the cell array, and prevent deterioration of the wiring shape.

[Example] Next, a MOS semiconductor device according to an example of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a plan view of the entire cell array, and Fig. 2 (a) is a plan view of the entire cell array.
FIG. 2(b) is a cross-sectional view taken along a line after the insulating film is formed.

=6- Figures 1 and 2 (a) correspond to the manufacturing stage shown in Figure 4 (b) above. That is, after forming the gate insulating film 3 on the semiconductor substrate 4, the gate electrode material is After forming a mask pattern that defines the active region using photoresist technology, the electrode material film is etched to form an electrode pattern in the active region. A cell array 5 is formed in which materials 2 are arranged at regular intervals.This electrode material 2 will later become a part of the device.

In this invention, as shown in FIG. 1, a dummy or auxiliary electrode material 1 is formed around the cell array 5 so as to surround the cell array 5. This dummy electrode material 1 has the same width as the electrode material 2 of the cell array 5,
It is separated from the width direction end portion and the longitudinal direction end portion of the electrode material 2 by the same distance as the distance between the electrode materials 2. This dummy electrode material 1 does not become a part of the element, but merely serves to make the field insulating film uniform in thickness, as will be described later. This tummy electrode material 1 can be formed at the same time as the electrode material 2 by also forming the pattern of the electrode material 1 when forming the aforementioned mask pattern for forming the electrode material 2. After that, an insulating film 7 is formed.

In the semiconductor device configured in this way, the dummy electrode material 1 is present outside the endmost electrode material 2 that forms part of the elements in the cell array 5.
As shown in b), the outer region 6 of the electrode material 2 at the extreme end, that is, the region between this electrode material 2 and the dummy electrode material 1,
A sufficiently thick insulating film 7 is formed similarly to between the electrode materials 2 inside the cell array 5. Therefore, the elements at the ends of the cell array 5 have good characteristics similar to the elements inside the cell array 5.

Note that the field insulating film 7 described above is not limited to bias sputtering, and may be formed by various means, such as vapor phase growth and etchback.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3(a) and 3(b).

As shown in the cross-sectional views of FIGS. 3(a) and 3(b), in this embodiment, the MO8
The present invention is applied to a type semiconductor device.

In this trench isolation technique, as shown in FIG. 3(a), a trench 9 is provided by forming a trench in an inactive region of a semiconductor substrate 8, and an insulating film 14 is embedded in the trench 9. In addition, an active region 1 as a conductive material is provided between the trenches 9.
0 is formed.

In this embodiment, when forming trenches in the semiconductor substrate 8 to provide the trenches 9, a dummy trench 11 having the same width as one of the trenches inside the cell array 12 is placed in the outer region 13 of the trench 9 at the end of the cell array 12. , cell array 12
The trenches 9 are formed with the same spacing as the spacing between the trenches 9 inside.

Therefore, outside the active region 10 at the end of the cell array 12,
A dummy active region 15 is formed.

Thereafter, as shown in FIG. 3(b), the trench 9 and the dummy trench 11 are filled with the insulating film 14 by bias sputtering. In this case, since dummy active regions 15 are formed outside the active region 10 at the end of the cell array 12 at the same spacing as inside, the outside of the end active region 10 is also thick enough. Field insulation film 14
is formed.

[Effects of the Invention] According to the present invention, conductive materials such as electrode materials or active regions are arranged densely and regularly at regular intervals on the outside of the conductive materials at the ends of the cell array, which are the same as the conductive materials inside the cell array. Since the dummy conductive materials are arranged at intervals, the field insulating film is formed to have a sufficient thickness at the end of the cell array as well as inside the cell array. This avoids deterioration of the characteristics of the elements at the ends of the cell array.

[Brief explanation of drawings]

FIG. 1 is a plan view of a MOS type semiconductor device according to an embodiment of the present invention, FIG. 2(a) is a cross-sectional view taken along the line ■-■ in FIG.
FIG. 2(b) is a cross-sectional view after forming the insulating film, and FIG. 3(a)
), (b) are cross-sectional views showing other embodiments of the present invention, FIGS. 4(a) to (d) are cross-sectional views showing the manufacturing process of a conventional MOS type semiconductor device, and FIG. 5(a), (b) is a conventional MOS
FIG. 2 is a cross-sectional view showing an end portion of a cell array of a type semiconductor device. 1; Dummy electrode material, 2, 24. Electrode material, 3, 22; Gate insulating film, 4, 8, 21; Semiconductor substrate, 5.12; Cell array, 6.13; Outer region, 7° 14.26. Insulating film, 9; trench, 10. Active region, 11; dummy trench, 15; dummy active region

Claims (1)

[Claims] A MOS type that has a cell array region formed by arranging a plurality of conductive materials at regular intervals on a semiconductor substrate with an insulating film interposed therebetween, and embedding an insulating film between each conductive material to form a field insulating film. The semiconductor device includes an auxiliary conductive material disposed outside the cell array region and spaced apart from the conductive material at the end of the cell array region at substantially the same distance as the mutual distance between the conductive materials in the cell array region. A MOS type semiconductor device characterized by: