JPS63299574A - Picture signal processor - Google Patents

Abstract

PURPOSE:To realize the joint of picture in a connection state by giving the continuous control to the reading/writing actions of a buffer memory having a double constitution in a start-stop state as well as the control to the picture reading action performed in the subscanning direction. CONSTITUTION:The cycle width of an OFF period of the scan synchronizing signal which controls the changeover of a double buffer memory 7 in response to the stop state of a start-stop signal 13 supplied from an external equipment. Thus the stop of the switching action of the memory 7 is controlled together with the discontinuation of an address counter which writes and reads a picture signal 10. Then the subscanning shift is moved back in the stop state of the signal 13 and then moved forward further after the move-back action. Thus the picture scanning joint is possible between the stop and start states of the signal 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing device such as a facsimile or scanner device.

2. Description of the Related Art In general, in image reading devices such as facsimile machines and scanners, image signals read by a photoelectric conversion element are converted into digital values by an A/D converter, and then various image signal processing is performed. It is. In order to perform this digital image signal processing, faster processing is possible if the image signal processing system is a pipeline processing system using a single clock. Normally, in the case of a scanner device, the synchronization timing of this image signal processing is performed by a scan synchronization signal ζY generated by a main scan rotation motor.

In this case, the image signal for -scanning is temporarily stored in an image signal memory with a high-speed double buffer structure provided immediately after the A/D converter, and is processed by a pipeline structure using a high-speed image signal readout clock. This enables high-speed operation of the system. That is, the high-speed double buffer memory must continuously perform a write operation of the image signal input from the A/D converter and a read operation using the read clock every synchronization signal. However, when outputting high-speed and large-volume image signals to an external computer, etc. through the image signal processing section, it is necessary to temporarily stop the image signal output from the scanner device depending on the processing speed of the external computer, etc. There may be cases where this is not the case. In such a case, a method is known in which the image signal output is temporarily stopped in response to a start/stop signal from the external device.

Hereinafter, a conventional image signal processing device will be explained with reference to FIG.

FIG. 4 shows the overall configuration of the scanner device.
2 is an I10 path connected to the sub-scanning control unit 4, 3 is an I10 path connected to the parameter control unit 5 for passing parameters to the image signal processing unit 8, and 6 is an MPU path that controls the entire system. A mechanism driver that controls mechanical units such as a sub-scanning motor, 7 a double buffer memory used to convert the speed of the input image signal 10, and 9 a timing generator that controls the timing to the double buffer memory 7 and the image signal processing unit 8. 11 is an output image signal output from the image signal processing section 8, 12 is a main scanning synchronization signal, and 13 is a start/stop signal from an external device.

In the above block configuration, a control method for the double buffer memory 7, image signal processing section 8, and timing generation section 9 will be explained. FIG. 5 shows a block diagram of the double buffer memory 7, and FIG. 6 shows its control timing. In FIG. 5, a latch circuit 20 temporarily latches the input image signal 30 after A/D conversion using an input clock 31, and its output data is connected to a buffer 21 and a buffer 23. Address counters 22 and 24 control the image signal write address and read address of the buffers 21 and 23, respectively. 25 and 26 are latch circuits which convert the output image signal data from the buffers 21 and 23 into the buffer read cycle signal 3 output from the buffer switching control section 27.
8.39. Reference numeral 28 denotes a buffer for inputting an image signal to the image signal processing section 8.

Note that the image signal processing section 8 is the same as that shown in FIG.
belongs to. 32 and 33 are a write/read control signal for controlling the buffer 21, a clock for controlling the address counter 22, and a counter clear control signal, which are output from the buffer switching control section 27, respectively. Similarly 34
, 35 are a write/read control signal for controlling the buffer 23 and a clock and counter clear control signal for controlling the address counter 24, which are output from the buffer switching control section 27. Further, 36 is a synchronizing signal for driving the double buffer memory 7 in FIG. 4, and 37 is a scanning synchronizing signal for controlling switching of the buffers 21 and 23, which is output from the timing generator 9 in FIG. is in phase with the drive synchronization signal 36, and both are signals generated by the rotation of the main scanning motor. Reference numeral 40 denotes a readout clock for controlling readout of the double buffer memory 7 and the image signal processing section, and is inputted to the image signal processing section 8 together with the output image signal 29.

Reference numeral 41 indicates a signal for stopping the synchronization signal trains 36 and 37 in response to the start/stop signal 13 inputted from an external device, which is output from the timing generator 9, thereby controlling the buffers 21 and 23 and Controls scanning movement.

The operation of the above configuration will be explained with reference to the timing diagram shown in FIG.

First, the buffer memory driving synchronization signal 36 (FIG. 6(b)) generated by the timing generator 9 based on the main scanning motor synchronization signal 42 (FIG. 6(a)) and the buffer switching synchronization signal 37 (FIG. 6(a)) (C)) is input to the buffer switching control section 27, the buffer 21 and the buffer 23 are switched to the synchronizing signal 3.
7 (FIG. 6(C)), a transition is made to the buffer control state shown in FIG. 6(a). This state control is performed by control signals 32 and 3 output from the buffer switching control section 27.
4, and in FIG.
BUF-WT/RI) is shown.

Now, when the buffer 21 is in the writing state and the buffer 23 is in the reading state, the input image signal 30 (FIG. 6(e))
is input to the buffer 2 along with the input clock 31 (FIG. 6(f)) in response to the main scanning motor synchronization signal 42 (FIG. 6(a)).
1, the input image signal 30 (FIG. 6(e)
)). Furthermore, the synchronization signals 42, 36, 37 from the next scan (Fig. 6(a), (b)
, (C)) together with the input image signal 30 (Fig. 6(e)).
When the buffer 21 is inputted, the buffer 21 becomes a read state and the buffer 23 becomes a write state, and the input image signal 30 (FIG. 6(e)) is written into the buffer 23 by the address counter 24. At this time, buffer 21
is in the read state, and the read clock 40 (Fig. 6 (h)
)) The output image signals 29 (FIG. 6(j)) are sequentially read out from the stored addresses of the address counter 22 counted by the above steps.

These address counters 22 and 24 are connected to synchronization signals 36,
37 (FIGS. 6(b) and 6(C)), the normal method is to clear the count during the OFF period and perform a preparation operation for the next count, and the same operation sequence is continued thereafter. Now, when a trigger signal 41 is input from an external device in response to the start/stop signal 13 as shown in Fig. 6 (in the figure, OFF is shown as a stop and ON is shown as a start), the stop period is The movement of the sub-scanning is stopped, and the synchronization signals 36 and 37 (Fig. 6 (bl,
(C) By increasing the period of time, the buffer switching operation is stopped, and at the same time, the image signal processing section 8 is also stopped. However, during this period as well, the main scanning motor synchronization signal 42 (
Input image signal 30 (FIG. 6(e)) together with FIG. 6(a))
Since the input clock 31 (Fig. 6) is continuously input, the image signals of the same scanning line are sequentially written into the buffer as shown in Fig. 6C2, and the image signals read from the buffer are The same image signal of the previous scanning line will be output. Therefore, the start/stop signal 4
The output image signal 29 (FIG. 6 (j)) at the time of state change at the time of stop of 1 (FIG. 6 (d)) and the restart signal 4
1 (Fig. 6(d)) is input, the synchronizing signal 36, 3
7 (FIG. 6(b), (C)') and the output image signal 29 (FIG. 6(j)) read out are not connected.

Problems to be Solved by the Invention As described above, there is a control configuration that uses a double configuration buffer memory to read one side while writing to the other, and a pipeline that operates in conjunction with this. In the image signal processing section of the structure, in the conventional method, while the start/stop signal from the external device is stopped, the scanning synchronization signal input to the double buffer memory and the image signal processing section is temporarily stopped. According to
Even if the double buffer memory operation was stopped, continuous writing and reading operations could not be performed, so the images could not be connected when restarted.

Furthermore, in image reading devices such as ordinary scanner devices,
In the sub-scanning direction, scanning is performed by mechanical means such as a pulse motor. Therefore, when scanning an image again after a temporary stop of image reading in response to a start/stop signal from an external device, the rise of the pulse motor drive may suddenly occur. Since this cannot be done, the image has the disadvantage of being elongated in the sub-scanning direction during start/stop connections similar to those described above.

In view of the above-mentioned problems (2), the present invention provides continuous control of write and read operations of a double-configured buffer memory at start/stop times and control of image reading operations in the sub-scanning direction, so that images can be connected at the time of connection. The present invention provides an image signal processing device that enables the following.

Means for Solving the Problems The present invention provides a scanning synchronizing signal (2) for controlling switching and writing/reading of the first and second buffer memories. an image signal timing control means for increasing the cycle width of the OFF period; a return counter means for reversing the movement of the sub-scan when the stop signal is input; , a forward counter means for advancing the sub-scanning movement, and a sub-scanning timing control means for controlling the movement timing of the sub-scanning.

Effect of the Invention With the above configuration, the present invention is capable of increasing the cycle width of the OFF period of the scan synchronization signal that controls switching of the double-configured buffer memory in response to the stop of the start/stop signal input from an external device. Therefore, in addition to controlling the stop of the switching operation of the double buffer memory and the stop of the address counter that performs the writing and reading operations of image signals, the sub-scanning movement is also retracted at the time of stop according to the start/stop signal. ,
After the sub-scanning movement is completed, the image scanning at the time of stopping and starting of the start/stop signal is performed by controlling the operation of further advancing the sub-scanning movement. Therefore, the above objective can be achieved with a simple additional device.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an image signal processing device according to an embodiment of the present invention, and FIG. 1 is an overall block diagram of, for example, a scanner device. In FIG. 1, numbers 1 to 13 are the same as the configuration shown in FIG. 4. 14 is the start/
The stop control section is connected to a start signal (13) from an external device, and this signal controls the mechanical section of the sub-scanning movement via both sections 4 on the sub-scanning side, and also controls the timing. The double-configured buffer memory 7 and image signal processing section 8 are controlled via the control section 9 .

The above configuration (2) Start/stop control section 14
The control operations for the double buffer memory 7, image signal control section 8, and sub-scanning control section 4 will be explained.

FIG. 2 shows a block diagram of the start/stop control section 14, and FIG. 3 shows its control timing.

The configuration of the double buffer memory 7 and the connection with the image signal processing section 8 are similar to those shown in FIG.
Portions that are common to conventional techniques will be explained using their numbers.

In FIG. 2, 50 is a buffer for the start/stop signal 13 input from an external device and a sub-scanning synchronization signal 60 input from the timing generator 9, and 51 is a buffer for detecting the input of a stop signal and connecting the signal line 62. Similarly, 61 is a signal line for notifying the MPU of input of a start signal. Reference numeral 52 denotes a sub-scanning timing control unit which outputs a control signal 63 for stopping and starting the sub-scanning movement via the sub-scanning control unit 4 in response to the sub-scanning synchronization signal 60, start/stop signal 13, etc. This includes an image scanning command signal 67 from the MPU and a start/stop signal which instructs forward movement in the sub-scanning from the MPU to the image reading position when a start signal is input again from the stop signal state. A control signal 69 output from a gate circuit 53 with 13 is connected thereto. Reference numeral 54 denotes an image signal timing control section, which receives start/stop signals 13 and 5 and an image scanning command signal 67.
and the end signal of the advance counter 56 are connected to the signals output from the gate circuit 55, and the output signal 66 is used to control the scanning synchronization signals 36 and 37 via the timing generator 9. 56 is a command signal 68 for forward movement at the time of restart and a parameter 70 for the amount of movement by the MPU as described above.
This is a forward counter that counts the number of sub-scanning lines according to the number of sub-scanning lines, and its borrow signal is connected to the gate circuit 55. Similarly, 57 is a return counter that counts the number of return lines in the sub-scanning movement according to the return amount parameter 70 when the stop signal 13 is input, and its output signal 64 is connected to one side of the OR gate 68. The output signal 65 from this performs 0N10FF control of the sub-scanning pulse motor via the sub-scanning control section 4 and mechanism driver 6.

The operation of the above configuration will be explained with reference to the timing diagram shown in FIG.

First, prior to image scanning, the MPU turns on the image scanning command signal 67 (see Figure 3), and along with the sub-scanning movement, the image reading operation is started.

At this time, the main scanning motor synchronization signal 42 (FIG. 6(a)) is used to generate the pan scan memory driving synchronization signal 36 (FIG. 6(d)) generated by the timing generator 9, and the buffer switching synchronization signal 37 (FIG. 6(d)). Figure (e)) shows the buffer switching control section 2.
7, the buffers 21 and 23 transition to the buffer control state shown in FIG. 3(i) in response to the fall of the synchronizing signal 37.

This state and write and read address control are the same as those shown in FIG. 5, and therefore will not be described here. Further, the sub-scanning synchronization signal 60 (FIG. 3(b)) has the same phase as the main-scanning motor synchronization signal 42 (FIG. 3(a)), and is used to control the return and forward movement of the sub-scanning. .

Now, when the stop signal of the start/stop signal 13 (FIG. 3(C)) is input (shown in the OFF state in FIG. 3), it is notified to ■■ via the signal line 62 via the flip-flop circuit 51, and MPU receives image scanning command signal 6
7 (Fig. 3(r)) is turned off.

At this time, the sub-scanning timing control section 52 outputs a control signal 63 so as to stop the sub-scanning movement at the next sub-scanning synchronization signal 60 (FIG. 3(b)). This state is notified by an output signal 65 (FIG. 3(0)) via an OR gate circuit 68.

Similarly, in synchronization with the falling edge of the synchronization signal 42 (FIG. 3(a)) following the input of the stop signal, the image signal timing control section 54 outputs the control signal 66 (FIG. 3(n)) to the timing generating section. 9, and the synchronization signal 36 is output accordingly.
, 37 (Fig. 3(d), (e)) are turned OFF.

Since the sub-scanning movement is stopped at this time, the same image signal is continuously input by reading the same scanning line, but the address counter 22 and address counter 24
remains cleared when the synchronization signals 36 and 37 are in the OFF state, so the counter does not operate and the output image signal 29 (
Figure 3 (1)) does not occur.

At this time, in order to connect the images by the start/stop operation of the sub-scan, the return operation and forward movement of the sub-scan are performed in combination during this stop state. This is because the sub-scanning is controlled by a mechanical means such as a pulse motor, so when the image is scanned again after a temporary stop of image reading, the torque drive of the pulse motor cannot be performed suddenly. This is to prevent the image from being extended in the sub-scanning direction when the /stop is connected.

This operation is performed as follows.

First, after the i'viPU detects that the stop signal 13 (FIG. 3(C)) has been input, the MPU sets the number of return lines of the sub-scanning movement to the return counter 57 via the parameter 70.
Set to . The state is the control signal 57 (Fig. 3 (p))
As shown in FIG. 3(b), the synchronization signal 60 (see FIG.
) is connected via an OR gate 68 to an output signal 65 (FIG. 3(0)) to control sub-scanning movement.

After the sub-scanning return operation is completed in this way, the sub-scanning forward movement is then performed. This is the restart signal 13 (third
After the MPU detects through the signal line 61 that the image scanning command signal 67 (Fig. (f)) is turned on.

The state is as shown in the control signal 56 in FIG. 3(q).
As a result, the movable table moves forward again, and this advance counter 56
The image signal timing control unit 54 is turned on again by the signal output from the gate circuit 55 of the pollo signal and the image scanning command signal 67 that are output when the number of sub-scanning lines has advanced by the set number of sub-scanning lines.

This control output signal is as shown in FIG. 6 (rl), and in synchronization with the rise of this output signal, the synchronizing signals 36 and 37 (FIG. 3 (d) and (e)) are turned ON again and the buffer switching operation described above is performed. The write and read operations continue.

As described above, by controlling from the stop state of the start/stop signal using the synchronization signal with a long cycle width of the OFF period during the restart period, the output image signal 29 is mechanically and A good electrical connection will also be achieved. In addition, the return counter 57
It goes without saying that the number of sub-scan movement lines set in the forward counter and the number of lines to be moved in the sub-scanning must be the same value.

Effects of the Invention As described above, the present invention temporarily stops the operation of the double-configured buffer memory and image signal processing unit in response to a stop signal of a start/stop signal input from an external device, and then restarts the operation of the double-configured buffer memory and image signal processing unit in response to a start/stop signal input from an external device. Even when image signals are read out from the buffer memory, the image signal processing system operates satisfactorily to connect the images. Furthermore, when reading an image, the mechanical movement is corrected by returning the sub-scanning movement and moving it forward again. Further, according to the present invention, it is possible to implement the system with a simple additional device, and in particular, it is possible to perform control according to the processing speed of the partner system.

[Brief explanation of the drawing]

FIG. 1 is a block wiring diagram of an image signal processing device according to an embodiment of the present invention, FIG. 2 is a block wiring diagram of main parts of the same device,
Fig. 3 is a timing waveform diagram of main parts of the same device, Fig. 4 is a block wiring diagram of a conventional image signal processing device, Fig. 5 is a block wiring diagram of main parts of the same device, and Fig. 6 is a main part of the same device. It is a timing waveform diagram. DESCRIPTION OF SYMBOLS 1... Pass, 4... Sub-scanning control section, 5... Parameter control section, 6... Mechanism driver, 7... Double buffer memory, 8... Image signal processing section, 9... - Timing generation section, 14... start/stop control section. Figure 12

Claims (1)

[Claims] Image signal timing control for increasing the cycle width of the OFF period of the scan synchronization signal in synchronization with the stop of the start/stop signal for the scan synchronization signal that controls switching, writing and reading of the first and second buffer memories. means and
a return counter means for reversing the sub-scanning movement when the stop signal is input; a forward counter means for advancing the sub-scanning movement upon completion of counting of the return counter means and input of the start signal; and controlling movement timing of the sub-scanning. and a sub-scanning timing control means to turn on the scanning synchronization signal via the image signal timing control means when the forward counter finishes counting.
An image signal processing device that obtains image signals from first and second buffers.