JPS63268199A - Memory test method - Google Patents

Abstract

PURPOSE:To realize an extremely simple test method by using a bidirectional linear feedback register for the generation of address information and the compression of information through the writing and the reading operation of a memory. CONSTITUTION:As initial value for the information compressor (bidirectional linear feedback register LFSR) 7, for instance, A11'1' is set. Based on the A11'1', an address generator 5 is shifted in the forward direction and an address is generated and written in a memory array 1. At the same time, the address information and data are inputted to the LFSR 7 and are compressed, then the input is made A11'0' and is stepped forward only one time. Thereafter, this value is made an initial value and the LFSR 7 is switched to the reverse direction, as well as the address generator 5 generates an address in the reverse direction to execute a memory reading. Thus the address and the data are inputted to the LFSR 7, and are compressed. If an A11'1' is generated, the memory array 1 is normal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory testing method, and more particularly to a simple, high-speed, and highly accurate memory testing method using a bidirectional linear feedback shift register.

[Conventional technology]

In testing random access memory (RAM), many test buttons are known.

For example, if the memory capacity is N bits, marching and checkerboard tests are known as N-bang tests whose test time is proportional to N, and walking and gear-ropping tests are known as N2-bang tests whose test time is proportional to N2. It is being these are,
They are used depending on the test time and test accuracy.
For example, the N-bang test is used because it is inferior in test accuracy and can be tested at high speed, while the N2-bang test is used when the N-test accuracy is important, although it has a problem in terms of test time. be done. Note that an intermediate M z/z baton has also been proposed.

On the other hand, in recent years, the density of RAM has increased significantly to 1Mbit,
With the advent of 4 Mbit devices, test time has become a major problem. From this point of view, there is active research into test methods that have high test accuracy and can perform high-speed tests.

In addition, a method is being considered in which a test circuit is built into the chip to enable automatic testing.

Traditionally, representative studies from these perspectives include K.
, K 1noshita , K , K , S
“Buiit-In Testing” by oluja
of Memory Using an 0n-Ch
ip Compact Testing Scheme
”, IEEE Transactions
on Computers, Vol. C-35,
Na1. O, pp8 '62-870 (Octobe
r 1986). This method adds a write button that takes into account fixed failures in memory cells, address decoding failures, and failures based on the influence of the contents of neighboring cells, and then firstly specifies addresses sequentially to read the memory contents. This is a simple test method that counts the number of 1'' or <1' based on logic (counting logic) that takes into account data from neighboring cells and compares it with the correct value.

[Problem that the invention seeks to solve]

In the above test method, control is executed using a microprogram built into the chip.

In addition, the correct answer values are also included for comparison testing. Therefore, even though it is a simple test method, it is not necessarily easy to control since it requires the use of a microprogram and the need to prepare correct answer values in advance. In addition, the address is incremented in principle by adding 1, and there is a problem in that it is not sufficient to perform a margin test of the address decoder by changing the address irregularly. Furthermore, addresses are often tested separately, for example by counting the number of 1'' in the read data and comparing it with the correct value, which has the problem that it is not necessarily a highly accurate test method. ing.

An object of the present invention is to provide a simpler, faster, and more accurate memory testing method that does not require determining the correct value in advance.

[Means for solving problems]

Linear feedback shift register (LFSR)
is often used in encoding/decoding circuits for test output compression or error correction, and is usually used as a one-way shift register based on an irreducible polynomial.

The present invention provides for a memory having a 2a word-b bit configuration.
LFSR constructed based on the primitive polynomial g(x) of degree a and LFSR constructed based on the reciprocal polynomial for g(x)
A bidirectional address generation LFSR is provided which can bidirectionally generate an address sequence of a bits, with a structure in which the registers are shared and switched by a switching gate. When a forward address of N is generated, an address sequence in the opposite direction to that during a write operation can be generated during a read operation, and both address information and write or read data are simultaneously compressed (a + b).
) bit length information compression LFSR is similarly configured to be able to operate bidirectionally.

[For production]

First, as an initial value of the information compression LFSR, for example, All
Information of "1" is set, and based on this, the LFSR for bidirectional address generation is shifted in the forward direction to generate an address, and at the same time a write operation to the memory is performed with predetermined write data. , LFS for bidirectional compression of both (a+b) bits of the address information and write data at the same time.
R in parallel and shifted in the forward direction, increments the addresses and compresses them one after another. When 2a addresses have been generated, input the (a+b) bits of the information compression LFSR. Step forward only once as All "O". Next, the LFS for information compression is set using this result as an initial value.
When R is switched to the LFSR for backward information compression, the LFSR for address generation is also switched, generating an address in the opposite direction to that at writing, and at the same time executing the memory read operation at this address, the address information and the read data are is input in parallel to the LFSR for backward information compression and advances one step, and after the final 2a addresses are generated, the (
a+b) Set all bit inputs to “O” and step in the opposite direction once, and as a result, the original initial value All”
1" has been generated in the LFSR. At this time, the information compression LFSR is set to the original initial value Al.
If N is generated, the memory is normal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, in which 1 is a memory cell array and 2 is an address decoder.

3 is a register that stores write data, 4 is a register that stores read data, 5 is an address generator using a bidirectional LFSR, 6 is a two-way manual selection circuit, and 7 is a bidirectional parallel input L.
Information compressor based on FSR.

8 is an AND gate, R/W is a control signal for controlling writing and reading, C is a clock signal, P is a preset terminal of the shift register, and t is a timing signal.

This embodiment differs from the prior art in that a bidirectional LFSR is basically used to generate address information and create compressed values. Therefore, first, the bidirectional LFSR will be explained.

If the forward LFSRti is based on the primitive polynomial g(x), the backward LFSR is based on the reciprocal polynomial g'''(x) of g(x). As a polynomial, g''(x) is defined as follows.

g”(x)=x”g(1/x) Therefore, for example, if g(x)=x''+x+1.

g''(x)=x'+x''+1.

FIG. 2 is a diagram explaining the operation of <LFSR based on the above polynomial, and (a) is based on g(x).

(b) is based on g''(x). In Figure 2, R
0 to R2 are shift registers, 11 is an exclusive OR gate, and C is a clock signal. In addition, the construction method of LFSR is "Code Logic" (Shokodo) 112 ~
It is stated on page 135.

Now, in Fig. 2(a), the initial value of LFSR is (1,
O, O), when clock signal C is stepped sequentially, 1
00→010→001→110→011→111→10
Seven patterns different from one can be generated. In general, based on the ``primitive polynomial of degree a'', <LFSR is different from 2
A pattern of a-1 can be generated.

In FIG. 2(b), the registers R0 to R2 are left as they are, but the direction of shift is reversed, which is equivalent to the LFSR according to the reciprocal polynomial. This is expressed as "LFSR".Now, the final value 10 obtained in Fig. 2 (a)
When the LFSR shown in FIG. 2(b) is operated with 1 as the initial value, it can be seen that as the clock advances, the steps are opposite to those of the LFSR shown in FIG. 2(a). In other words, 101 →111→001→110→001→0
The value changes from 10 to 100, and finally returns to the initial value 100 in FIG. 2(a).

Figure 3 shows the functions of (a) and (b) in Figure 2 by register R.
This shows a bidirectional LFSR with a structure in which 0 to R2 are shared and switched by a switching gate.

9 is a two-man AND gate, 1o is a two-man OR gate,・
11 is an exclusive OR gate. According to this LFSR, when the R/W terminal is set to 1'1'' during writing, it becomes an LFSR that shifts to the right, and when it is set to ``0'' during reading, it becomes equal to an LFSR that shifts to the left. Therefore, the R/W terminal is set to 1", and the three shift registers R0~
By setting the initial value "100" in R2, adding six tarok signals C and shifting to the right, the information sequence shown in FIG. 2(a) can be generated, and finally "101" remains. Next, set the R/W terminal to II OIt and set it to '101'.
If we take the initial value and shift it in the opposite direction, this becomes as shown in Figure 2 (
It should become equal to LFSR'' shown in b), information on the reverse sequence can be obtained, and it should return to the initial value ``100''. Note that the address information A11 "O" can be obtained by setting the LFSR to the reset state, then 2a
All different addresses can be generated.

The address generator 5 in FIG. 1 uses a bidirectional LFSR as shown in FIG. 3, which allows the address sequence to be reversed during writing and reading. That is, when writing, the address generator 5 generates a forward sequence address in synchronization with the clock signal C by setting the R/W terminal to 1'', and when reading,
By setting the R/W terminal to 0'', an address is generated in the reverse sequence to that at the time of writing.The address generated by the address generator 5 is decoded by the address decoder 2, and at the time of writing, the address is set to the write data register. Test button data No. 3 is written in the memory array 1 in a forward address sequence, and when read, it is read out from the memory array 1 in a reverse address sequence and set in the read data register 4.

The selection circuit 6 switches the input to the information compressor 7 using the R/W signal, and selects the output of the write data register 3 during writing (R/W=1), and selects the output of the write data register 3 during reading (R/W=O ) selects the output of the read data register 4. In this way, the write address and write data are input to the information compressor 7 in parallel according to the forward address sequence during writing, and the read address and read data are input in parallel according to the reverse address sequence during read.

Next, the operation of the parallel input LFSR will be explained using a simple example.

FIG. 4 is an example of a parallel input LFSR consisting of four shift registers R0 to R3. The feedback of the output value of this final stage shift register R3 is based on the primitive polynomial g(x
)=x'+x+1.

In this case, exclusive OR gate 11. located at the inputs of Ro and R. and added to 111. The other inputs of each exclusive OR gate are the outputs of the shift registers in the previous stage, and the parallel input terminals 12° to 12. This is data that is added in parallel to . This data of 12 to 123 is
In the case of a 2a word-b bit memory, m containing both a bits of address information and b bits of write or read data.
= data corresponding to a+b bits. C is a clock, and every time information is input to 12° to 12□, a clock is input to shift the contents of shift registers R0 to R1 to the next stage.

Generally, the operation contents of a shift register of a parallel input LFSR can be expressed as the product of a characteristic matrix T determined by an irreducible polynomial g (x) of degree m and an input data vector E of degree m. The irreducible polynomial is expressed as g(x)=Σ
g I X' p go = g m = 1
When i=0, T can be expressed as an m×m square matrix as follows.

In the example shown in Figure 4, the irreducible polynomial g(x)
From '=x'+x+1, it can be expressed as follows.

This LFSR has a width of m bits. ,■,.

...tI n-21I n-1 n pieces of data are input in this order, as a result of the intermediate shift stage, S
i.

i=o, 1. ..., n-1 can generally be represented by the following formula.

S, = I, ■S branch -□ ・T
...
(1) i=o, L −, n-1 (S-4=O) 25,5lyIi is an m-th order row vector, and ■ indicates exclusive OR. In the example shown in FIG. 4, the next n=4 input data is Iw. This is an example of inputting in the order of →work+tt→work, □→work w3.

Address Write data■. . =(00゛11) Iw□=(Ol, 11) Iw□=(11101) Workw□=(10°10) In this example, the address is the first 2 bits, and the write data is the second half 2 bits. In this case the address is x”
It can be generated by a two-stage LFSR created by a primitive polynomial of +x+1. At this time, the results of LFSR at each stage,
5w1 (i=0, 1, 2°3) can be expressed as follows from equation (1).

S1=Iwll=
(0011)Svl”IwzG)So・T=Iw−oI
woT” (1010)S-=IJ
S engineering・T=Iv,■engineering,T■I,,T”=
(1000)Sw)=IJS2-T=Iw,OI,,T
OIw1T"ΦI,,T'=(1110) The information compressor 7 in FIG.
It consists of R, but a parallel input is further added. For the example where m = 4th order, the bidirectional LFSR to which this parallel input is added
FIG. 5 shows the operation sequence of the information compressor 7 consisting of the following.

FIG. 5(a) is a circuit that is exactly the same as the example in FIG. 4, and the parallel input data is also Iw. Enter →IVx→IWz→IV3. Furthermore, the initial values Kw of the LFSRs before these parallel inputs are added are all "1". This can be set in advance using the preset terminal P. Next, Sw is generated by adding the first data IVo and a clock to shift the contents of shift registers R0 to R1. get. Sw.

can be expressed as Swo''Iw.e Kw·T using equation (1). After applying up to II+fs in the same way, the contents of the shift register are 5V3=(1010) tonal.

Next, set the parallel input to All "Ojl" and apply a clock only once to advance the LFSR. This operation is performed by SW3.
・It is displayed as T, and the result is (0101).

Next, consider L F S R'' in which the shift direction is reversed in the second part of the contents of this register. This L F S R'' is composed of a reciprocal polynomial g''(x)=x'+x''+1. This is shown in Figure 5(b). At this time, the initial value is 8w3·T shown earlier, and KR=(0101). As for parallel input, data is now input in the reverse sequence to that input to the previous LFSR. That is, I
V3 (= I R1,) → I wz (= I R
□) → I wx (= I R2) → Eng. (=IR3
). In this way, after the first clock is input and the first shift is executed, SR,=I□. O
+KR-T-1 is obtained. At this time, I RQ = I
W3, and T-1 is the inverse matrix of T. in this way,
Finally, with IRa→IRE→IRI→D applied, SRa = I R3(f) S n□・T-'=
(l O11) is obtained. Next, set the parallel input to All“0”
”, adding the clock only once as L F S R”
advance. This operation can be expressed as SR3·T-1, and as a result, the initial value Kv=
(1111) is equal to the All “1” vector. At this time, it can be proven as follows that SR3·T-1 is equal to Kv.

Sゎ・T−1=(Iゎ■Sゎ・T−1)T−′=IR3
・T-1■Swa・T-2=Koudo T-10 (Kouwa■5RL
T-') T-"=1 Koji T-1eIゎT-"O+SゎT4
=I motion T-0I-T-"■(1,O+SkaT-')T-
"=I R3T-'OI R2T-"oI l12T-
"G) I +hT-" ■S+b T-'= I
-10I R-T-20I yh T-' ■(If
lo eKRT-1) T-'=I,, T-″eI-T-
``ΦIRILT-'eI-'r'OK, T-'Kon
KR=S,・T=(I−■S,・T)T=I,,・TO
5-・T2=IylIT(i)IT"ΦSy,-T
"=5.・T■工、・T" e I +6・T3ΦS1
・T4=1. -T■Ivx "T" OI itx
“T3e Iwe” T’(E)Kw” T’This KR and I RO= IV3y 1R1= IIt!
By substituting +'IR□=Iwzp IR3=IIll, the final result of the above SR,-T-' becomes as follows.

(I vts T-'OI H,T-” ■IRILT4
■IoT-) (1) (KR・T-5)= (IyB
T-ioI In 'r-" e I B T-"
oI @ T-') e(Ius Te I m T”
OI,,T3(i)Ivl,T'eK,-T')T-'
=(IwllT-'eIvlT-"OI,,T-'()
)Iy,T-')■(Iw-T”())Iw!JT-3
eIylT=ΦIyoT−'eKw)=K.

Next, it will be explained that such an operation can generally be realized by the LFSR having the above configuration. The initial value is K, and n crabs are input. , Engineering 1. ..., engineering. If -1 is added, first, the contents Sw of the shift register at that time for a forward shift. ts111? ....

S w-i y S wn is as follows. However, Swn is a 1-clock shift operation with an input of 110''.

SW-, =: Initial value SwI, =I, Φ-T SIh = I ze Swo T = I t O
I a "TeK"T"5un-n=No-x■S
wn-z ” T = I n-10I n-2-T
O・(EI I LTn-"eI.-T"'(E)K-
T' 5wn= Swn-t" T= I n-x "Te
I n-z"T"G)...OItT'-1(i)1
．． TI'0K-Tn" Next, set Swn to the initial value and process □-□tIn-at...
, Engineering 11 Engineering. input in the opposite direction and shift in the opposite direction, resulting in S II-t t S R11g...psR
n is as follows. However, SRI'l inputs "0".
” This is a one-clock shift operation.

5R-t=sVfl S,==In,G)Swn-T-' 5RIL=xr1-ses11. l-'r-”=xn-
t*'r-1esw,-'r-"S n-t =Io
eS, In-t “T-n=No(E) I□”T-
1G) L ” T-” ■・=OI n-1'T-”
-1'oSwn'T-'5nn=S*nt・T-"=
I, T-1e IxT-2e I, T-'■-G)
I rl−□T−n■S,,@T−(n” Substituting the above swn for the last term to 2, Sv
, 6T-””=I n-, @T-noIn-, “T-”
'-"Φ...■I, T-"el, T-OK, 5IIn is as follows.

5un=(IaT-"e IxT-"e IzT-'Φ
...OI n-tr-n)e D n-zT-ne
I n, T-'n-1)ee 1. T=e 1. T1
(2) It can be seen that Sin is generally equal to the initial value K by K)=.

From the above, in the information compressor 7 shown in FIG. 1, when writing, after inputting the write address and write data in the normal sequence to the LFSR whose initial value is "1", the input is set to "110" and one shift is performed. When reading, use this result as the initial value and input the read address and read data in the reverse direction using "LFDR", and finally input the "
By changing the value to "0" and performing a one-time shift operation, it is possible to restore the first initial value All "1". This is a relationship that holds true at least when there is no error in the information input at the time of reading.

Now, suppose that the input to the LFSR at the time of reading in the example of FIG. 5 is as follows.

Address Read data. = (0011) I'□, = (01 [01) IRz = (1101) E'□, = (101■) In other words, the read data of IRl and E R□ each has a one-bit error ( Assume that the above case (indicated by 0) occurs. At this time, the LFSR of Fig. 5(b)
Compression value S□ operated using. sSR□ysR2 etc. are as follows.

KR=(0101): Initial value SRI,=(OOOO):I. . ■KR-T-1S
R1=(0101) :I'ゎ■5RII・T-1S
Yo=(0111) :IBGDSB-・T4Sゎ=(
0101) :I'R3@SR□・T4Syu・T-
'=(1010) 'FKw From now on SRa・T-11
does not become the original initial value Kw of All “1”. From this, it is possible to detect errors in the read data.

FIG. 6 shows a specific configuration of a bidirectional parallel input LFSR that simultaneously realizes the functions of FIG. 5 (a) and (b). In FIG. 6, by setting the R/W signal to "1" or "0", the operation is switched to the operation shown in FIG. 5(a) or (b). Further, using the preset terminal P, initial values All "1" are set in the shift registers R5 to R1. In addition,
C is a clock signal.

The AND gate 13 in FIG. 1 generally takes an AND condition of (a+b) bits, and inputs all the register outputs of the bidirectional LFSR in the information compressor 7 in parallel, and if they are all It 117, then ( If normal), t
Output i1t+. A timing signal t is applied to this AND gate 13, and when the test sequence is completed, the timing signal t is set to "1" to confirm the test result.

In the above description, the length of the LFSR as the information compressor 7 is basically (a + b) bits.

It is clear that in the case of a memory with a large word direction and a large address bit length a, a shorter LFSR structure can be obtained by compressing the space through an exclusive AND gate. In this case, since the object to be inspected is mainly read data,
Compressing b must be avoided.

Further, in the explanation so far, no particular mention was made of the contents of the IF-included data. This write data is "0" to the two-dimensional memory array to test the influence from adjacent memory cells.

A checkerboard pattern in which "1"s are written in a checkered pattern may be adopted, and in this case, the data to be written to the address may be determined in advance and input to the write data register 3.

In addition, the address generator 5 used in the present invention can easily be configured with further control signals and gates so that it can function as a normal address register (1) during normal online operation, and an LFSR (LFSR) during testing. .

As for the bidirectional LFSR used in the present invention, it was previously shown that even if it is started with an arbitrary initial value, it will eventually return to the initial value due to the configuration of the LFSR. Therefore,
In the embodiment, All "1" was used as the initial value, but it does not necessarily have to be this value, and any value can be taken as the initial value, so that the AND gate 8 in FIG. That's fine.

〔Effect of the invention〕

As explained above, the present invention eliminates the need to obtain a signature value in advance, and uses a bidirectional LFSR to generate address information and compress information through memory write and read operations. This method has the advantage of being able to implement a flexible memory testing method. In particular, according to the method of the invention, the final result is that all LFSR values, e.g.
The normality of the memory can be tested by simply checking ll "1", which has the advantage of being a simpler test method.

In addition, L is used to generate address information that changes randomly.
Since FSR is used, it also serves as a marginal test of the address decoder as address information changes. Furthermore, in the method of the present invention, the address that is randomly changed in the case of writing is changed in the direction opposite to that in the case of writing in the case of reading, so there is an advantage that the address decoder can be tested with higher accuracy.

In addition, it is easy to control and the test circuit has a simple configuration, so it is suitable for random access memory, etc.
These circuits can be mounted on a chip, and automatic testing built into the chip can be configured relatively easily.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram explaining the operation sequence of a bidirectional LFSR, FIG. 3 is a diagram showing a specific example of a bidirectional LFSR, and FIG. 4 is a diagram illustrating a specific example of a bidirectional LFSR. FIG. 5 is a diagram illustrating how input information is compressed, FIG. 5 is a diagram illustrating an operation sequence of a bidirectional parallel input LFSR, and FIG. 6 is a diagram illustrating a specific example of a bidirectional parallel input LFSR. 1...Memory array, 2...Address decoder, 3...Write data register. 4...Read data register. 5... Address generator using bidirectional LFSR, 6...
・Input selection circuit, 7... Information compressor using bidirectional parallel input LFSR, 8
...AND gate. Figure 1 Figure 2 (Good) Figure 3 Figure 4 (0011')-5W. (1010')-5w. (+000)-8vJJ () I lo)-
';W. −At°shiλ −−→← Denita →(G) Ll l l
+)-T′ Fig.δ

Claims (1)

[Claims] (1) For a memory with a 2^a word-b bit structure, a
bit-long bidirectional linear feedback shift register (
(hereinafter referred to as bidirectional LFSR); and (a+b) bit length bidirectional parallel input linear feedback shift register (hereinafter referred to as bidirectional parallel input LFSR);
First, an initial value K is set in the bidirectional parallel input LFSR of the information compressor, and then the bidirectional LFSR of the address generator is shifted in the forward direction to generate the forward address sequence. At the same time, the address information and write data are sequentially input in parallel to the bidirectional parallel input LFSR of the information compressor, and the bidirectional parallel input is performed. The input LFSR is shifted in the forward direction and compressed one after another, and when the generation of 2^a addresses is completed, the input of the bidirectional parallel input LFSR is set to all "0" and the input is shifted in the forward direction only once. Next, the bidirectional LFSR of the address generator is shifted in the opposite direction to generate an address sequence in the opposite direction to that for writing, and a read operation to the memory is performed according to the generated address, and at the same time, the address information is and the read data are sequentially input in parallel to the bidirectional parallel input LFSR of the information compressor,
The bidirectional parallel input LFSR is shifted in the opposite direction to the writing time and compressed one after another, and after generating 2^a addresses,
Shifting the inputs of the bidirectional parallel input LFSR to all "0" in the opposite direction only once, and checking whether the original initial value is generated in the bidirectional parallel input LFSR as a result. A memory test method characterized by testing the normality of memory.