JPS63244950A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To facilitate synchronous detection and to decelerate a synchronizing processing, by inserting distributively a frame synchronizing pattern bit by bit into the leading bit of each frame in frame constitution of bit multiplexing system. CONSTITUTION:From high-order group input data 101, for example, seven sub- frames are inputted. To the forefront of each sub-frame, one bit to the frame synchronizing pattern is inserted distributively. The high-order group input data is taken out by every three bits at a serial-parallel conversion circuit 103, and they are developed to three systems of output information, and are inputted to a channel shunt circuit 104. In such a case, since the frame synchro nizing pattern which constitutes a patrol code of seven bits is inserted only to the output data 110 of the circuit 104 at every N/3(N represents a frame length bit), it is fetched in a divider 1061, and is divided by a generating func tion, and synchronization can be confirmed by the result of zero of a remainder.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization system used in digital transmission systems such as backbone transmission systems, public networks, and subscriber systems.

(Conventional technology) There has been remarkable progress in transmission technology using optical fiber as a transmission medium, and the amount of information transmitted is now several hundred Mbps.
Transmission at speeds of up to several Gbps is becoming possible. Time-division multiplexing is a possible method for effectively using large-capacity digital transmission systems, but it requires high-speed processing.
The frame structure is made as simple as possible, and the circuit is made smaller and simpler. One such method is a bit-based time division multiplexing method, and FIG. 4 is a frame configuration diagram of the -a bit multiplexing method. In the figure, one frame is made up of bits, one frame is divided into channels in units of bits, 1,000 channels of which are assigned to frame channels, F is a frame channel, and -1 is assigned to #1 to #. is 11 channels in bits. In this method, when bit multiplexing, a unique frame pattern is inserted one bit at a time into the frame channel (F) in units of several frames, and in synchronization detection, data is separated for each channel and then separated from any channel. The frame channel is detected and synchronization is detected based on whether the inserted signal string matches the inserted unique frame pattern.

Another method is to divide the frame into subframes and distribute the frame pattern to each subframe. FIG. 5 shows a general example of the frame structure. In the figure, one frame is divided into L subframes, and each subframe has a unit of 1 bit, and has a structure of 1 frame (IXL) bits. The pattern is inserted one bit at a time. Fi (i=1.2 . . . le) is a frame bit inserted into the first bit of each subframe,
#1 to #L indicate subframes in units of 1 bit. In this method (P IF2F3...FL-1FL)
is the frame pattern, and in synchronization detection, (PIF2F3...FL-I
Synchronization detection is performed by detecting a frame pattern called FL). It is not necessary to insert the frame pattern into all of the frame hits F1 to FL; for example, if the frame pattern
, . . ., the remaining frame bits F2F4F6 .

(Problems to be Solved by the Invention) In the bit multiplexing system as shown in FIG. 4, one of the bits in one frame is
Bits are used. In order to downsize and simplify the circuit, the length of K constituting one frame cannot be made too large, so the signal amount of the frame pattern is increased to 1/1 of the amount of transmitted data. .

This overhead is expected to increase as the transmission capacity increases and speed increases.Furthermore, when considering system reliability and serviceability, channels to transmit information such as transmission path monitors and service monitors are also required. The trend will increase significantly. Furthermore, in the method shown in Fig. 5, in which the frame is divided into subframes and the frame pattern is distributed to each subframe, there is a unique frame pattern (PIF2F3/
. . . PL-IFL) is detected from the separated signal strings to perform synchronization detection and ensure frame synchronization and subframe synchronization. The complexity of the circuit can be reduced by inserting and transmitting information such as a transmission path monitor or service monitor in the frame bits F1 to FL, and by increasing the number of subframes in one frame and the number of subframe constituent bits I. It becomes possible to transmit information with less overhead relative to the amount of transmitted data without increasing the amount of data transmitted.

However, once the synchronization is lost, the frame pattern (PIF2F3... FL-IFL
) in order to detect a signal string that matches from a separated signal string, hunting for one frame is required in the worst case, so the worst case synchronization time required to recover synchronization is L.
XIXI frame (SEC), and the number of subframes and subframe configuration bits become large.
Once the synchronization is lost, the frame pattern (PIF2F3
. . . FL-IFL).

Furthermore, in the same method, there is a unique frame pattern (
In order to separate the FIF2, . For this reason, once synchronization is lost, it is necessary to detect a frame synchronization pattern for all sequences developed in parallel in the worst case.

The present invention solves these problems, reduces the overhead of the amount of frame pattern signals relative to the amount of transmitted data without increasing the circuit size or complexity, makes it easy to detect frame patterns, and makes it easy to recover synchronization. It is possible to reduce the averaging time, and furthermore, by searching at least one series of the outputs of the serial/parallel converter used to reduce the signal processing speed, it is possible to grasp the state of the entire system. The object of the present invention is to provide a synchronization detection circuit suitable for high-speed, large-capacity transmission systems.

(Means for solving the problem) According to the present invention, the first
a serial-to-parallel converter, a channel switching device to which M outputs of the serial-to-parallel converter are connected and capable of switching the channels of the M input signals and outputting the M signals; M that uses each output signal of the shuffler as an input line and calculates the remainder between a code polynomial whose coefficient is the code length L bits extracted from the input line and a predetermined generator polynomial.
dividers; means for controlling channel swapping of the channel swapping circuit using the code length L bits and the result of the remainder sent from the M dividers; and the channel swapping control means. a second control signal which inputs the control signal of the channel switch and expands the output signal of the channel switch in parallel.
A frame method is obtained which is characterized in that it includes a serial-to-parallel converter.

(Example) Before describing an example of the present invention, a cyclic code will be briefly explained here. Generally code word (A1)
, A1. A2+-An-t), Ao is n-1
Next, by associating A1 with the n-2th order, ..., An-, with the 0th order, the code polynomial F(X) is written as F(X)=^a-1"Ag-,x+^n-3X"”'÷
p, 1Xll-2+AoXll-1 (1). Here, it is assumed that the code length is n, and in terms of time, a higher-order term A appears first, progresses to lower-order terms, and finally A+z-1 appears.

Here, if the code length is 7 and the code word is (C,, C2, C3°..., C7), then the code polynomial F(X)
can be expressed as a 6th degree polynomial, F(X)=C, +C6X+C3X2+C4X'+C3X
It can be expressed as '+C2X'+C,
・ (If 31, F(X)・Q(X)G(X)
...(If there exists a polynomial Qt(X) that satisfies Equation (41), the polynomial in Equation (21) has been generated from the generator polynomial in Equation (3).Here, as the polynomial Qs(X), the input Polynomial 0 whose coefficient is bit string I・<1110)
If we choose the formula %(51) and assume a field modulo 2, we get F(X)=Q(
X) G(X) = (X+X2+X') -(1+X+X3)=X+x5
+) [6-(61), code word wo: (1100 units 10)
. . . is generated from the input bit string I.(1110). In this case, there are 24-1.15 types of input bit strings excluding the (0000) bit string, and a code word corresponding to each input bit string is generated.

Furthermore, as shown in the publication "Coding Theory" (Hiroshi Miyayo, Yoshihiro Iwadare, Hideki Imai, Shokodo, p194-197), in a field modulo 2, generally n is When the code length is taken as the code length, when the generator polynomial Gl(X) divides X''+1, the code word generated from G+(X) forms a cyclic code. Therefore, the generator polynomial in equation (3) is (X' +1)/G(X
)=(X7+1)BaX'+X+1)=X'+X2+X+
1...Divide X7+1 by X'+X2+X+1, so the formula (
3) A code word with a code length of 7 generated from the generator polynomial becomes a cyclic code. That is, in the code word of equation (7), equation (9
) Each row element of the matrix W is a cyclic code with a code length of 7, and W, = (1100010) ・
...(10-1)W2=(10 units 0101)
・(10-2
)w3=(mouth001011)
・(10-3)-4-(0
mouth 10110)
...<10-4)t5=(0101100)
-(10-5)
W6=(101100 units)
...(10-6)w7=(ot
to mouth 01)
...When (10-7), W,, W2,
..., the code polynomial having v7 as a coefficient is divisible by the generator polynomial of equation (3).

FIG. 1 shows a frame synchronization method in an embodiment of the present invention. In the figure, 101 is higher-order group input data Sin
, 102 is a high-order front clock CLKin, 103 is a first serial/parallel conversion circuit, 104 is a channel switching circuit,
105 is a 1/3 frequency dividing circuit, 1061 to l port 6. 107 is a synchronous control circuit, 1081 to 1083 are second serial/parallel conversion circuits, 109□ to 1099 are low-order group output data 5out, and 1101 to 1103 are output data of the channel switching circuit 104.

In the same figure, from the higher order group input data (Sin) 101,
Data in the frame shown in FIG. 2 is input.

The frame in the figure is 3-bit multiplexed, the subframe length is N bits (N is a multiple of 3), and one frame consists of 7 subframes, and the first bit of each subframe has a frame synchronization pattern. Fi(・1.2...,7
) indicates a frame synchronization bit pattern inserted in each subframe. As this frame synchronization pattern, a cyclic code with a code length of 7 generated from the generator polynomial shown in equation (3) is selected. For example, the code Wl shown in formula (10-1): (F tFz-F7)"<1100010)
= Insert (11) as a frame synchronization pattern. In the serial/parallel conversion circuit 103, the high-order group input data 101 consisting of the frame shown in FIG. This channel switching circuit 104 is connected to a synchronous control circuit 107 as described later.
After performing channel switching using the output information from
Outputs three series of information. With this channel switching control, once synchronization is achieved, subsequent channel control only needs to maintain that state, and there is no need to perform high-speed control. In addition, this channel switching circuit 104 does not require a function of connecting each input to an arbitrary output, and the channel switching control here only requires sequential channel switching. For example, the output data 1101 of the channel switching circuit If series A is output to the output data 1102 of the channel switching circuit, series B is output to the output data 1103 of the channel switching circuit, and series C is output to the output data 1103 of the channel switching circuit, the channel switching circuit 104 outputs series B and channel to the output data 1101 of the channel switching circuit. The output data 1102 of the switching circuit is series C, the output data 1103 of the channel switching circuit is series A, or the output data 1101 of the channel switching circuit is series C, the output data 110□ of the channel switching circuit is series A, and the output data 110□ of the channel switching circuit is series A. Sequential channel switching control such as outputting data of series B as output data 1103 can be performed.

Hereinafter, ensuring a synchronous state and hunting control in an asynchronous state will be sequentially explained.

First, in the synchronized state, the channel switching circuit 10
4, a series consisting of frames as shown in FIG. 3 is output. In this figure, the frame of the high-order group input data shown in FIG.
The subframe length is N/3 bits, and one frame consists of seven subframes. The frame synchronization pattern, which is a 7-bit cyclic code inserted into the frame of high-order group input data, is inserted into frame #1 only, distributed every N/3 bits.

In the synchronized state, frame #1 is the output data 1100 of the channel switching circuit 104, frame #2 is the output data 1102 of the channel switching circuit 104,
Frame #3 appears in the output data 1103 of the channel switching circuit 104. Output data 110 of channel switching circuit 104. ~1103 are branched into two, one being the dividers 1061~1063 and the other being the serial/parallel conversion circuit 10.
B, ~1083 input information. Here divider 10
6 to 1063 take in each input information every N/3 bits. Then, the patent polynomial characterized by the sequentially captured 7-bit pattern is divided by the generator polynomial G(X) shown in equation (3). In the synchronized state, only the divider 1061 takes in the frame synchronization pattern shown in equation (11), and the remainder becomes zero. Dividers 1061 to 1063 supply their respective remainder results to synchronization control circuit 107. The synchronization control circuit 107 checks whether the remainder of the divider 1061 is zero and the divider 106! Frame synchronization is confirmed by confirming that the 7-bit pattern captured by the frame matches the pattern shown in equation (11).

On the other hand, the information input to the serial/parallel conversion circuits 10B to 1083 is further expanded into three bits each based on the frame synchronization maintenance information of the synchronization control circuit 107. In other words, in the low-order group output data 1091 to 1099, a signal obtained by expanding the high-order group input data 101 into 9 bits and made further slower appears.

Next, hunting control when an asynchronous state occurs will be explained. In the asynchronous state, first, it is detected to which series of the output data 110° to 1103 of the channel switching circuit 104 the frame #1 shown in FIG. 3 is being transmitted. 106
．． -1063 are output data 1101-110. of the channel switching circuit 104. is captured every N/3 bits, and a code polynomial whose code word is the 7-bit pattern captured sequentially and a generator polynomial 〇(
Perform division with X). In the synchronization control circuit 107, the remainder result is examined. If any remainder is non-zero, the dividers 106 to 1063 divide the output data 11O8 to 1103 of the channel switching circuit 104 into N/3
The phase to be captured is shifted by 1 bit for each bit. This operation is repeated until any of the remainders of the dividers 1061 to 1063 becomes zero.

The fact that the remainders of any of the dividers 1061 to 1063 are non-zero means that the remainders of the dividers 106. This means that the bit string captured in ~1063 is information other than the frame synchronization pattern inserted in the frame of FIG. 2, that is, other than the frame synchronization pattern forming the cyclic code shown in equation (11>). .On the other hand, the dividers 1061 to 1063
The fact that one of the remainders becomes zero means that Equation (11)
This means that a frame synchronization pattern group forming the cyclic code shown in is detected. At this time, the synchronization control circuit 107 determines which divider 1061 to 1063 has a remainder of zero. In other words, divider 1061
When the remainder becomes zero, the channel switching circuit 10
4, output data 110□ of the channel switching circuit 104 when the remainder of the divider 1062 becomes zero, output data 110 of the channel switching circuit 104 when the remainder of the divider 1063 becomes zero.
3, a sequence consisting of frame #1 in FIG. 3 is received. Based on this result, the synchronization control circuit 107 sends control information to the channel switching circuit 104, and outputs data 11 of the channel switching circuit 104.
Sequential channel switching is performed so that frame #1 in FIG. 3 is transmitted on time 01.

However, the 7-bit pattern taken into the divider whose remainder is zero is not necessarily taken in exactly the same order as the code string shown in equation (11).

In other words, subframe synchronization is simply ensured. Therefore, in the synchronization control circuit 107, at the same time as sequential channel switching control, frame synchronization is ensured by detecting the phase difference between the 7-bit pattern taken into the divider with a zero remainder and the code string of equation (11). .

Output data 1101-1 of channel switching circuit 104
Since the number of subframe bits in 103 is N/3 bits, the worst case number of hunting required to perform channel switching control and ensure frame synchronization after once falling out of synchronization is N/3-1, which means that Synchronous processing becomes possible.

So far, the case has been explained using an example in which the number of subframes in one frame is 7, the code length of the cyclic code is 7, and the generator polynomial is X'+X+1. However, the present invention is not limited to these combinations; By increasing the bit multiplicity in input data, it is possible to further reduce the processing speed. Further, the dividers 1061 to 1063 can be easily configured by using a shift register and a mod 2 adder, and the circuit can be simplified and downsized.

(Effects of the Invention) As described above, by using the synchronization method according to the present invention, synchronization detection is easy, the speed of synchronization processing is reduced, and the state of the entire system can be grasped using high-order group data without being particularly conscious of the frame structure. Furthermore, it can be seen that the average asynchronous duration time is significantly improved compared to the synchronous method with the conventional configuration.

The present invention is a synchronization method suitable for such high-speed, large-capacity transmission systems, and is expected to be applied to transmission systems that will become even faster and larger in the future.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG.
Figure 3 is a frame configuration diagram in the present invention, Figures 4 and 5.
The figure is a frame configuration diagram in a conventional example. In the figure, 101 higher-order group input data Sin, 102
High-order group input clock CLKin, 103 first serial/parallel conversion circuit, 104 channel switching circuit, 105 1/3 frequency dividing circuit, 106. ~1063 divider, 107 synchronous control circuit, 108, ~108. Second serial-to-parallel conversion circuit, 1
091-1099 Low-order group output data 5out, 110.
~1103 Output data of channel switching circuit 104.

Claims (1)

[Claims] A first serial-to-parallel converter that extracts the received signal every M bits is connected to M outputs of the serial-to-parallel converter, and outputs M signals by switching channels of the M input signals. A channel swapping device capable of M dividers; means for controlling channel swapping of the channel swapping circuit using the code length L bits and the result of the remainder sent from the M dividers; and the channel swapping control. a second serial-to-parallel converter which receives a control signal of the channel switching device as an input and parallelizes the output signal of the channel switching device.