JPS63182751A - Instruction fetching circuit - Google Patents

Abstract

PURPOSE:To facilitate a program processing in a program debug/practical state by providing a debugging mode bit to an instruction code and discriminating this mode bit in a non-execution mode to skip it. CONSTITUTION:The execution or non-execution mode of a debugging instruction code 54b is set at a mode setting register 3 and a debug mode bit 50 is discriminated when an instruction code 53 read into a buffer 1 is set at an instruction register 2. When a debugging mode is set, the code 53 of the buffer 1 is set as it is at the register 2 with the exclusion of the bit 50. In a non-execution mode, it is inhibited to set the code 54b at the register 2 and at the same time the next code 53 is read into the buffer 1. Since the execution and non-execution modes are controlled by hardware, a program recompiling job is not needed. Furthermore the executing speed is never deteriorated even in a practical application state.

Description

[Detailed Description of the Invention] [Summary] A debug mode bit is provided in the instruction code to identify whether the instruction code is inserted for debug processing, and when non-execution mode information is set in the register, the debug instruction To provide an instruction fetch circuit that reads the next instruction code without executing the instruction code.

[Industrial application field]

The present invention relates to an instruction fetch circuit that controls execution/non-execution of read instruction code.

In computer systems, trace message directives are embedded in programs as a means of checking the program's operation, but when the program is actually used, the trace message directive is removed and the program is retranslated (compiled) or debugged/ A determination flag for actual use is provided to prevent the trace message command from being executed during actual use.

However, if the trace message command is removed, it is difficult to trace a failure when it occurs in actual use, and if the flag is determined by a program, there is a problem that extra program execution time is required.

Therefore, there is a need for an instruction fetch circuit that solves the above problem.

[Conventional technology]

Figure 5 shows an example of embedding a trace message command, and Figure 6 shows execution/execution of a trace message command using flags.
It is a figure showing non-execution control.

FIG. 5 shows the flow of the program, and shows that the program branches in many ways due to conditional branching.

By embedding a trace message command 55 in each part of such a program, for example a series of instruction codes that display the sequence number of executed program steps, the flow of execution can be determined by setting branch conditions and the program can be debugged. can do.

Since a large number of trace message commands 55 are provided for each branch of the program, for example, they are removed during actual use in order to shorten execution time.

The first method is to remove the trace message command 55 and recompile, and the second method, as shown in FIG. 6, is to determine execution/non-execution flags during execution and remove them.

[Problem that the invention seeks to solve]

In the first method described above, it is difficult to trace a failure when it occurs in actual use, and in the second method using determination flags, the program steps and their execution times of flag determination instructions and conditional branch instructions are The problem is that it costs extra.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide an instruction fetch circuit that identifies a debugging instruction code such as a trace message command and controls at high speed whether or not to execute the instruction code. It is.

[Means for solving problems]

For the above purpose, the instruction fetch circuit of the present invention, as shown in FIG. An instruction code (53) with a mode bit (50), a mode setting register (3) for setting execution or non-execution of debug processing, and the corresponding debug mode bit (50) of the read instruction code.
), a detection means (4) for detecting the instruction code (54b) for debugging, and the mode setting register (3).
When the non-execution mode information (51) is set in the instruction register (2) of the instruction code (54b) for debugging,
), and a control means (5) for reading the next instruction code into the buffer (1'').

[Effect]

For example, at the beginning of the instruction code, debug mode focus 50 is set.
is added, and the bit of the instruction code 54b inserted for debugging is set to logic "1", and the other instruction codes are set to logic "0".

The setting of the debug mode bit 50 is performed, for example, at the time of compiling, and the compiler determines the debug instruction code 54b by a specific code representing debug processing, and performs the above setting processing.

Execute the debugging instruction code 54b (execution mode,
Debug mode) or not (non-execution mode) is set in mode setting register 3, and debug mode bit 5
The determination of 0 is based on the instruction code 53 read into buffer 1.
This is done when the command is set in the instruction register 2.

When the debug mode is set, the instruction code 53 of buffer l is set to the instruction register 2 as is except for the debug mode bit 50, and in the non-execution mode, the instruction code 54b for debugging is not set to the instruction register 2. At the same time, the next instruction code 53 is read into the buffer 1.

Since the above is configured by hardware and execution/non-execution is controlled, there is no need to recompile the program, and there is no reduction in execution speed during actual use.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 is a diagram showing an example of the instruction configuration of a 2-byte instruction, FIG. 3 is a block diagram of an instruction fetch circuit of the embodiment, and FIG. 4 is a flowchart explaining the operation.

Note that this embodiment shows a case where the program is loaded into the main memory to which an address is assigned for each byte (in this embodiment, 1 byte consists of 9 bits as described later), and a trace message command 55 is inserted. This will be explained using an example.

The instruction code (the conventional instruction code is designated by the reference numeral 54) is usually composed of multiple bytes (or words) and is stored in the program area of the main memory in units of bytes.

Therefore, 10M bits 50.50B are provided for each byte so that a debug mode (IDM) bit 50 is added to the first byte of the instruction code 54.

FIG. 2 shows 10 at the beginning of the instruction code 54 of a 2-byte instruction.
This shows an instruction code 53 with an M bit 50 added.

When inserting the trace message command 55 into a program, the trace message command 55 composed of a series of instruction codes 54b is constructed as a subprogram, and a specific code is inserted.

The compiler determines this specific code and translates it into a subprogram call instruction, sets "1" to the 10M bit 50 of the first byte of the call instruction, and sets 0 to the IDM bit 50B of the second and subsequent bytes. ”.

A plurality of bits following the IDM bit 50 of the instruction code include byte length data 52, whereby an instruction code of a predetermined byte length is set in the instruction register 2 from the buffer l.

FIG. 3 shows an embodiment of an instruction fetch circuit configured based on the instruction code 53 set as described above.

Note that the instruction code is defined as follows.

° Conventional instruction code...54 Conventional instruction code inserted for debugging...54b Instruction code with IDM bit added...53 In Figure 3, 8 is an instruction buffer register (corresponding to buffer 1) consisting of 4 bytes (9 bits x 4), 9 is an AND gate, and output control signal 56 output from the instruction pointer control unit 14.
10 is an OR circuit, 2 is an instruction register that sets the instruction code 54 of 8-bit configuration excluding 10M bits 50.50B, and 12 is an instruction. 13 is a decoder (corresponding to the detection means 4) that decodes the instruction code 53 output from the OR gate 10 and identifies the data length, 10M bits 50; 14 is an instruction pointer control section (control means 5), which loads the instruction code 53 into the instruction buffer register 8 and controls the transfer to the instruction register 2 based on execution/non-execution mode;
is the mode setting register 0PSR, which can be set from the operation panel (not shown). The operation is shown below.

〔translation〕

A trace message command 55 consisting of a series of instruction codes 54b is made into a subprogram, and a specific code for calling the subprogram is inserted at a predetermined position in the program.

The compiler determines this specific code and translates it into the calling instruction code of the above subprogram, and places "1" in M (10M bits 50) after the first byte of the instruction code.
Add (set) "0" to the beginning of the other bytes (IDM bit 50B).

In addition, the instruction code of the above subprogram and other instruction codes include “
0'' is set.

[Operation] See Figure 4 The translated program above is loaded into the main memory 6,
When in debug mode, mode setting register 0PSR3
Set "1" to "1", and set "0" (non-information mode information 51) for actual use to start the program.

(1) The instruction code 53 indicated by the program counter 7 is read into the instruction buffer register 8 from the program area of the main memory 6.

(2) The instruction pointer control unit 14 opens the AND gate 9 to read the next two bytes of the previously read instruction code 53, and determines the 10M bit 50 and data length.

(3) When mode setting register 0PSR3 instructs execution (1"), the specified data length is read and 10
The instruction code 54 excluding the M bit 50.50B is set in the instruction register 2.

After setting a predetermined byte length, it is decoded and executed.

(4) When mode setting register 0PSR3 is “0”,
The instruction code 53 whose 10M bit 50 is "l" is prohibited from being set to the instruction register 2 and the output of the set signal 57 is prohibited), and the next instruction code 53 specified by the program counter 7 is transferred from the main memory 6 to the instruction buffer register 8. Load into.

As described above, by providing the 10M bit 50 added to the beginning of the conventional instruction code 54 and the mode setting register 0PSR3, the type of instruction code can be quickly identified, and the execution/non-execution by conventional flag judgment is possible. Execution time can be significantly improved compared to when controlling

〔Effect of the invention〕

As explained in detail above, the present invention provides an instruction fetch circuit that provides a debug mode bit in the instruction code and determines and skips the debug mode bit when the instruction code is in non-execution mode. The effect of facilitating program processing in is extremely large.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing an example of the structure of an instruction code in a 2-byte instruction, Fig. 3 is a block diagram of the instruction fetch circuit of the embodiment, and Fig. 4 is a flowchart explaining the operation. Figure 5 shows an example of embedding a trace message command, and Figure 6 shows execution/execution of a trace message command using flags.
This is a diagram representing non-execution control. In the figure, 1 is a buffer, 2 is an instruction register, 3 is a mode setting register, 4 is a detection means, 5 is a control means,
6 is the main memory, 7 is the program counter, 8 is the instruction buffer register, 9 is the AND gate, 10 is the OR gate, 12.
13 is a decoder, 14 is an instruction pointer control unit, and 50.50B is a debug mode bit IDM. 51 is non-execution mode information, 52 is data length information, 53 is an instruction code with an IDM bit, 54 is a conventional instruction code excluding the debug mode bit, 54b is an instruction code inserted for debugging, and 55 is a trace. Message command, 56 is an output control signal, 57 is a set signal, Cabinet debug mode Bift Figure 1 r-1 Nomaito - ■ - - 1 byte -]
・・・・・・－・・・-Block diagram of the instruction fetch circuit of the embodiment of the debug mode bint Fig. 3 A flowchart diagram explaining the operation Fig. 4 A diagram showing an example of embedding a trace message command Fig. 5

Claims (1)

[Scope of Claims] An instruction fetch circuit that sequentially reads instruction codes stored in a memory into a buffer (1), sets the instruction codes in an instruction register (2), and executes the instructions, the circuit comprising: a debug circuit that executes debugging processing; Instruction code for (54
b) an instruction code (53) with a debug mode bit (50) for identifying whether or not the debug mode is selected; a mode setting register (3) for setting execution or non-execution of debug processing; and the debug mode of the read instruction code. Bit (50
), a detecting means (4) detects the instruction code (54b) for debugging, and non-execution mode information (51) is set in the mode setting register (3).
) is set, the instruction code for debugging (54
An instruction fetch circuit comprising control means (5) for prohibiting the setting of the instruction code (b) into the instruction register (2) and for reading the next instruction code into the buffer (1).