JPS63181196A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63181196A JPS63181196A JP62011382A JP1138287A JPS63181196A JP S63181196 A JPS63181196 A JP S63181196A JP 62011382 A JP62011382 A JP 62011382A JP 1138287 A JP1138287 A JP 1138287A JP S63181196 A JPS63181196 A JP S63181196A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- circuit
- supply voltage
- internal circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 26
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 101150114751 SEM1 gene Proteins 0.000 description 1
- 241000277331 Salmonidae Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.
（従来の技術）
半導体集積回路装置例えばＭＯＳ （）ｌｅｔａｌＯｘ
ｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｆｏｒ ）型の集積回路
装置においては、微細化、高密度化が目ざましい。例え
ばダイナミックランダムアクセスメモリにおいては３年
間で１チップ当りのピッ１〜数が４倍になっており近年
では１Ｍビット／チップのものまで商品化されている。(Prior art) Semiconductor integrated circuit device such as MOS ()letalOx
In integrated circuit devices of the ide Sem1 conductor type, miniaturization and high density are remarkable. For example, in dynamic random access memory, the number of bits per chip has quadrupled over the past three years, and in recent years, 1M bits/chip has been commercialized.
一方、電源電圧はシステムインターフェイスやノイズマ
ージンという観点から、従来から用いられてきた電圧を
踏襲している場合が多い。そのため、デバイス内部で電
界が高まり、いわゆるホラ１〜キヤリア注入効果等によ
り信頼性が低下する傾向がある。電源電圧および入出力
レベルを従来と同一にしたままでデバイス内部での電界
を緩和する一つの試みとして、１ｓｓｃｃ ＤｉｇｅＳ
ｔｏｆ Ｔｅｃｈｎｉｃａｌ Ｐａｐｅｒｓ、ｐＤ、２
７２〜２７３．Ｆｅｂ、１９８６にデバイス内部で電源
電圧を低下させる電圧変換回路を内蔵する提案がなされ
ている。このように電圧変換回路を内蔵することにより
、通常よりも高い外部電圧が印加されたとしても、内部
を保護することが、でき、信頼性を向上させることがで
きる。On the other hand, the power supply voltage is often the same as the voltage traditionally used from the viewpoint of system interface and noise margin. Therefore, the electric field increases inside the device, and reliability tends to decrease due to the so-called hollow carrier injection effect. As an attempt to alleviate the electric field inside the device while keeping the power supply voltage and input/output level the same as before, 1sscc DigeS
tof Technical Papers, pD, 2
72-273. On Feb. 1986, a proposal was made to incorporate a voltage conversion circuit to reduce the power supply voltage inside the device. By incorporating the voltage conversion circuit in this way, even if an external voltage higher than normal is applied, the internal parts can be protected and reliability can be improved.
しかし、その反面、内部回路に意図的に通常よりも高い
電圧を与えられないため次のような不都合が生じる。即
ち、半導体デバイスでは、初期不良をスクリーニングし
たり、新しく開発したデバイスの信頼性試験をするため
、通常め規格よりも高い電源電圧を加えて動作させるい
わゆるバーンインを施すことが多い。これは、通常の規
格での使用状態は故障率が小さく、信憑性のめるデータ
を得るには、膨大なサンプル数あるいは試験時間を必要
とするので、電源電圧を高くすることにより、故障発生
を加速し、現実的に対処しているのである。したがって
、内部回路に通常規格よりも高い電圧をかけることがで
きないデバイスではバーンイン番行うことができず、製
品の信頼性評価に支障をきたすことになる。However, on the other hand, the following disadvantages occur because a voltage higher than normal cannot be intentionally applied to the internal circuit. That is, in order to screen for initial failures or to test the reliability of newly developed devices, semiconductor devices are often subjected to so-called burn-in, in which they are operated at a power supply voltage higher than the normal standard. This is because the failure rate is low under normal standard usage conditions, and obtaining reliable data requires a huge number of samples or testing time, so increasing the power supply voltage accelerates the occurrence of failures. And they are dealing with it realistically. Therefore, burn-in cannot be performed on devices in which it is not possible to apply a voltage higher than the normal standard to the internal circuit, which poses a problem in evaluating the reliability of the product.
この発明は、以上述べた内部に電源電圧低減回路をもっ
た半導体集積回路装置における信頼性試験の困難を除去
し、信頼性試験を容易に実施し得る半導体集積回路装置
を提供することを目的とする。An object of the present invention is to eliminate the difficulty in performing reliability tests on semiconductor integrated circuit devices having internal power supply voltage reduction circuits as described above, and to provide a semiconductor integrated circuit device that can easily perform reliability tests. do.
本発明の半導体集積回路装置は、内部回路と、外部から
供給される電源電圧を受け、それよりも低い電圧に変換
して上記内部回路に供給する電圧変換回路とを備え、上
記電圧変換回路は外部から与えられる制御信号により、
上記低い電圧よりも高い電圧を上記内部回路に供給し得
るものである。A semiconductor integrated circuit device of the present invention includes an internal circuit and a voltage conversion circuit that receives a power supply voltage supplied from the outside, converts it to a lower voltage than the power supply voltage, and supplies the converted voltage to the internal circuit. Due to the control signal given from the outside,
A voltage higher than the low voltage can be supplied to the internal circuit.
上記の構成であれば、制御信号により、電圧変換回路の
出力電圧を変えることができる。従って、例えば、内部
回路の通常の動作時には電源電圧よりも低い電圧（通常
の動作電圧）を内部回路に供給する一方、試験時には、
上記低い電圧（通常の動作電圧）よりも高い電圧、例え
ば電源電圧を印加し、バーンイン等を行なうことができ
る。With the above configuration, the output voltage of the voltage conversion circuit can be changed by the control signal. Therefore, for example, while a voltage lower than the power supply voltage (normal operating voltage) is supplied to the internal circuit during normal operation of the internal circuit, during testing,
Burn-in or the like can be performed by applying a voltage higher than the above-mentioned low voltage (normal operating voltage), for example, a power supply voltage.
（実施例〕
第１図は本発明の第１の実施例を示すブロック図である
。信号入力端子１は、例えばデバイスがランダムアクセ
スメモリ（ＲＡＭ）で必ればアドレス入力や読み出し、
書き込みの制御入力のために使用される。入力変換回路
２は信号入力端子１により入力される入力信号の論理振
幅を内部回路の論理振幅に変換する。内部回路３は、デ
バイスがＲＡＭであればアドレスデコーダ、メモリセル
、センスアンプ等で構成される。出力変換回路４は内部
回路部３からの出力を外部の論理振幅に変換する。出力
信＠端子５は出力変換回路４の出力をデバイスの外部に
出力するのに使用される。電源電圧変換回路７は、外部
電源端子６から供給される電源電圧を、これよりも低い
電圧に変換する機能を持つとともに上記低い電圧または
外部電源端子６の高い外部電源電圧のいずれかを選択し
て内部回路３に印加する。上記の選択は制御入力端子９
を介して入力される選択制御入力信号に基いて行なわれ
る。入力および出力変換回路２および９には外部電源端
子６から直接電源電圧が加えられる。より微細な素子で
構成される内部回路３には、通常は、電源電圧変換回路
７によって低減された電源電圧が印加される。一方、通
常の動作条件よりも高い電圧をかけて故障発生を加速す
るようなバーンインを行う場合や信頼性試験を行う場合
には、制御信号により電圧変換回路７を切換え、外部電
源端子６からの電源電圧が内部回路に直接が加わるよう
にする。(Embodiment) Fig. 1 is a block diagram showing a first embodiment of the present invention.For example, if the device is a random access memory (RAM), the signal input terminal 1 is used for address input, readout, etc.
Used for write control input. The input conversion circuit 2 converts the logic amplitude of the input signal inputted through the signal input terminal 1 into the logic amplitude of the internal circuit. If the device is a RAM, the internal circuit 3 is composed of an address decoder, a memory cell, a sense amplifier, etc. The output conversion circuit 4 converts the output from the internal circuit section 3 into an external logic amplitude. The output signal @terminal 5 is used to output the output of the output conversion circuit 4 to the outside of the device. The power supply voltage conversion circuit 7 has a function of converting the power supply voltage supplied from the external power supply terminal 6 to a lower voltage, and also selects either the above-mentioned lower voltage or the higher external power supply voltage of the external power supply terminal 6. is applied to the internal circuit 3. The above selection is the control input terminal 9
This is done based on the selection control input signal inputted via the. A power supply voltage is applied directly to the input and output conversion circuits 2 and 9 from an external power supply terminal 6. A power supply voltage reduced by a power supply voltage conversion circuit 7 is normally applied to the internal circuit 3 made up of smaller elements. On the other hand, when performing burn-in or reliability testing where a voltage higher than normal operating conditions is applied to accelerate the occurrence of failures, the voltage conversion circuit 7 is switched by a control signal, and the voltage from the external power supply terminal 6 is Ensure that the power supply voltage is applied directly to the internal circuits.
第２図は電源電圧変換回路７の一例を示したもので、こ
の回路は、電源電圧をそれよりも低い電圧に変換する変
換部７Ａ、該低い電圧と電源電圧ＶＣＣのいずれかを選
択して出力する切換部７Ｂとから成る。ノード２０１は
基準電圧ノードでおり、電源電圧を■ＣＣ１抵抗器’１
０１．１０２の抵抗値をＲ、Ｒとすれば、この基準電圧
ＶｒｅｆはＲ１０２／ （Ｒ１０１＋Ｒ１０２） ＸＶ
ｃｃとなる。この％ ｉ％電圧ｖｒｅｆはトランジスタ
１０３を通じノード２０２にＶｒｅｆ＋Ｖｔとなって現
われる（Ｖｔはトランジスタ１０３のしきい値電圧であ
る）。トランジスタ１０４は出力トランジスタでおり、
そのディメンジョンは必要な配給能力に応じて決定され
る。出力ノード２０３の電圧はノード２０２よりもトラ
ンジスタ１０４のしきい値電圧だけ低下した値となり、
トランジスタ１０３，１０４のしきい値電圧が等しけれ
ば出力電圧は基準電圧ｙｒｅ’ｔ’にほぼ等しくなる。FIG. 2 shows an example of the power supply voltage conversion circuit 7, which includes a converter 7A that converts the power supply voltage to a lower voltage, and a converter 7A that converts the power supply voltage to a lower voltage, and selects either the lower voltage or the power supply voltage VCC. It consists of a switching section 7B that outputs. Node 201 is a reference voltage node, and the power supply voltage is connected to CC1 resistor '1.
If the resistance values of 01.102 are R and R, this reference voltage Vref is R102/ (R101+R102) XV
cc. This %i% voltage vref appears at node 202 through transistor 103 as Vref+Vt (Vt is the threshold voltage of transistor 103). Transistor 104 is an output transistor,
Its dimensions are determined by the required distribution capacity. The voltage at the output node 203 is lower than that at the node 202 by the threshold voltage of the transistor 104,
If the threshold voltages of the transistors 103 and 104 are equal, the output voltage will be approximately equal to the reference voltage yre't'.
ｉ・ランジスタ１０８．１０９，１１０．１”１１゜１
１２．１１３および１１４はフィードバック回路であり
、出力電圧を安定化している。またトランジスタ１０５
，１０６はノード２０４がハイレベルになると導通し、
電圧変換回路をディスイネーブルする。ノード２０４が
ハイレベルになるとトランジスタ１１５も導通し、電源
電圧ｖＣＣが端子２０３にそのまま伝えられる。したが
って内部回路３に外部電源電圧をそのまま加えたい場合
には、制御入力端子９からの信号によってノード２０４
をハイレベルにし、内部回路３を外部電源電圧に接続す
るようにすればよい。i-ransistor 108.109, 110.1”11°1
12, 113 and 114 are feedback circuits that stabilize the output voltage. Also, the transistor 105
, 106 become conductive when the node 204 becomes high level,
Disable the voltage conversion circuit. When the node 204 becomes high level, the transistor 115 also becomes conductive, and the power supply voltage vCC is directly transmitted to the terminal 203. Therefore, if you want to apply the external power supply voltage to the internal circuit 3 as is, the signal from the control input terminal 9 can be applied to the node 204.
may be set to a high level and the internal circuit 3 may be connected to the external power supply voltage.
次に、第３図を用いて他の実施例について説明する。第
１図と同一の部分については同一符号を付している。こ
の実施例では電源電圧変換回路１７の出力電圧が可変で
、内部回路３へ印加される電源電圧が制御入力端子１９
から入力される制御信号によって連続的に変化させるこ
とができるようになっている。通常の動作では電源電圧
変換回路１７の出力は外部電源電圧よりも低い設定値に
制御されている。試験のため内部回路に設定値よりも高
い電圧をかける場合は制御端子１９により、電源電圧変
換回路１７を制御し、・外部電源電圧の範囲内で電圧を
変化させることができる。Next, another embodiment will be described using FIG. The same parts as in FIG. 1 are given the same reference numerals. In this embodiment, the output voltage of the power supply voltage conversion circuit 17 is variable, and the power supply voltage applied to the internal circuit 3 is controlled by the control input terminal 19.
It can be changed continuously by a control signal input from the controller. In normal operation, the output of the power supply voltage conversion circuit 17 is controlled to a set value lower than the external power supply voltage. When applying a voltage higher than the set value to the internal circuit for testing, the control terminal 19 controls the power supply voltage conversion circuit 17, and the voltage can be changed within the range of the external power supply voltage.
第４図は電源電圧変換回路１７の一例を示したものでお
る。この電源電圧変換回路１７は、制御端子１９からの
制御信号の電圧レベルに応じた基準電圧信号を発生する
基準電圧信号発生部１７Ｃと、電源電圧ＶＣＣを基準電
圧信号に応じた電圧に変換する変換部１７Ａとから成る
。即ち、この回路の基本的な動作は第２図と同一である
がこの例ではノード２０１の基準電圧ｙｒｅ”ｒをノー
ド２０５から制御できるようになっている。簡単のため
、１〜ランジスタ１２１〜１２４のしきい値電圧がすべ
て等しくＶｔとするとノード２０５の電圧がノード２０
１の電圧よりも４ｘｙｔ以上高くなったとぎ、基準電圧
Ｖｒｅｆが上昇し、出力電圧も上昇する。ノード２０５
の電圧がそれ以下では基準電圧Ｖｒｅｆは変化°Ｖず出
力電圧ｙｏｕｔは設定値を保つ。この電源電圧変換回路
１７を第３図の装置に組込むにはノード２０５を制御入
力端子１９に接続し、制御入力端子の信号レベルを、所
望の出力電圧ｖｏｕｔに応じて調整することとすればよ
い。FIG. 4 shows an example of the power supply voltage conversion circuit 17. This power supply voltage conversion circuit 17 includes a reference voltage signal generation section 17C that generates a reference voltage signal according to the voltage level of the control signal from the control terminal 19, and a converter that converts the power supply voltage VCC into a voltage according to the reference voltage signal. It consists of part 17A. That is, the basic operation of this circuit is the same as that in FIG. 2, but in this example, the reference voltage yre''r of the node 201 can be controlled from the node 205. If all threshold voltages of 124 are equal to Vt, the voltage of node 205 is equal to that of node 20.
When the voltage becomes higher than the voltage of 1 by 4xyt or more, the reference voltage Vref rises and the output voltage also rises. node 205
When the voltage is lower than that, the reference voltage Vref does not change by °V and the output voltage yout maintains the set value. To incorporate this power supply voltage conversion circuit 17 into the device shown in FIG. 3, the node 205 may be connected to the control input terminal 19, and the signal level of the control input terminal may be adjusted according to the desired output voltage vout. .
以上のように本発明によれば、電源電圧変換回路の出力
電圧を制御信号により変化できるようにしたので、内部
回路の通常の動作時には低い電圧を供給できる一方、バ
ーンイン鱒のときには、高い電圧を加えることができ、
信頼性試験を容易に実施できるようになる。As described above, according to the present invention, since the output voltage of the power supply voltage conversion circuit can be changed by a control signal, a low voltage can be supplied during normal operation of the internal circuit, but a high voltage can be supplied during burn-in trout. can be added,
Reliability tests can be easily performed.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の電源電圧変換回路の一例を示す回路図、
第３図は本発明の他の実施例を示すブロック図、第４図
は第３図の電源電圧変換回路の一例を示す回路図である
。
３・・・内部回路、６・・・外部電源端子、７，１７・
・・電源電圧変換回路、９，１９・・・制御入力端子。
特許出願人 沖電気工業株式会社
・−１゛＼
代理人弁理士 鈴 木 敏 明 ″７Ａ、−
ｊ−，７Ｂ
電源電り是換回路７の一判
番２巨
１７Ｃ◆ヰゆ／７Ａ
ｔｙｒ、電！ｉｌ［１ＥＩＢ／７のｍ−１発４ 固FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the power supply voltage conversion circuit of FIG. 1, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 4 is a circuit diagram showing an example of the power supply voltage conversion circuit of FIG. 3. 3... Internal circuit, 6... External power supply terminal, 7, 17.
...Power supply voltage conversion circuit, 9, 19...Control input terminal. Patent applicant: Oki Electric Industry Co., Ltd. -1゛＼ Representative patent attorney: Toshiaki Suzuki "7A, -
j-, 7B Power supply exchange circuit 7 no. 2 giant 17C◆Y/7A tyr, electricity! il[1EIB/7 m-1 shot 4 solid
Claims (1)
圧に変換して上記内部回路に供給する電圧変換回路とを
備え、 上記電圧変換回路は外部から与えられる制御信号により
、上記低い電圧よりも高い電圧を上記内部回路に供給し
得るものである ことを特徴とする半導体集積回路装置。 ２、上記電圧変換回路は、上記電源電圧をそれよりも低
い電圧に変換する変換部と、上記変換部の出力と上記電
源電圧とを受け、上記制御信号によりいずれか一方を選
択して出力する切換部とを備えていることを特徴とする
特許請求の範囲第１項記載の装置。 ３、上記電圧変換回路は、上記制御信号の電圧レベルに
応じた基準電圧信号を発生する基準電圧信号発生部と、
上記電源電圧を上記基準電圧信号に応じた電圧に変換す
る変換部とを備えていることを特徴とする特許請求の範
囲第１項記載の装置。[Claims] 1. An internal circuit, and a voltage conversion circuit that receives a power supply voltage supplied from the outside, converts it to a lower voltage, and supplies it to the internal circuit; 1. A semiconductor integrated circuit device, wherein a voltage higher than the lower voltage can be supplied to the internal circuit according to a control signal given from the semiconductor integrated circuit device. 2. The voltage conversion circuit receives a converter that converts the power supply voltage to a lower voltage, an output of the converter, and the power supply voltage, and selects and outputs one of them based on the control signal. 2. The device according to claim 1, further comprising a switching section. 3. The voltage conversion circuit includes a reference voltage signal generation section that generates a reference voltage signal according to the voltage level of the control signal;
2. The apparatus according to claim 1, further comprising a converting section that converts the power supply voltage into a voltage according to the reference voltage signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62011382A JPS63181196A (en) | 1987-01-22 | 1987-01-22 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62011382A JPS63181196A (en) | 1987-01-22 | 1987-01-22 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181196A true JPS63181196A (en) | 1988-07-26 |
Family
ID=11776459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62011382A Pending JPS63181196A (en) | 1987-01-22 | 1987-01-22 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181196A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63207000A (en) * | 1987-02-24 | 1988-08-26 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS6455857A (en) * | 1987-08-26 | 1989-03-02 | Nec Corp | Semiconductor integrated device |
| DE4115082A1 (en) * | 1990-05-09 | 1991-11-14 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE WITH VOLTAGE CONVERTER CIRCUIT AND METHOD FOR OPERATING THE SAME |
| JPH0417191A (en) * | 1990-05-11 | 1992-01-21 | Toshiba Corp | Semiconductor device and its burn-in method |
| JPH06295585A (en) * | 1991-08-19 | 1994-10-21 | Samsung Electron Co Ltd | Inside power supply voltage generating circuit |
| US5363333A (en) * | 1992-09-30 | 1994-11-08 | Nec Corporation | Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process |
| JPH097370A (en) * | 1995-06-12 | 1997-01-10 | Samsung Electron Co Ltd | Generation circuit of internal power-supply voltage for semiconductor memory device |
| US6538931B1 (en) * | 1997-10-15 | 2003-03-25 | Stmicroelectronics S.A. | Methods of operating an integrated circuit with memory having an internal circuit for the generation of a programming high voltage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5870482A (en) * | 1981-10-23 | 1983-04-26 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS60103587A (en) * | 1983-11-09 | 1985-06-07 | Toshiba Corp | Capacitor voltage impressing circuit of memory cell in semiconductor storage device |
-
1987
- 1987-01-22 JP JP62011382A patent/JPS63181196A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5870482A (en) * | 1981-10-23 | 1983-04-26 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS60103587A (en) * | 1983-11-09 | 1985-06-07 | Toshiba Corp | Capacitor voltage impressing circuit of memory cell in semiconductor storage device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63207000A (en) * | 1987-02-24 | 1988-08-26 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS6455857A (en) * | 1987-08-26 | 1989-03-02 | Nec Corp | Semiconductor integrated device |
| DE4115082A1 (en) * | 1990-05-09 | 1991-11-14 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE WITH VOLTAGE CONVERTER CIRCUIT AND METHOD FOR OPERATING THE SAME |
| US5283762A (en) * | 1990-05-09 | 1994-02-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device containing voltage converting circuit and operating method thereof |
| JPH0417191A (en) * | 1990-05-11 | 1992-01-21 | Toshiba Corp | Semiconductor device and its burn-in method |
| US5568436A (en) * | 1990-05-11 | 1996-10-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of screening the same |
| JPH06295585A (en) * | 1991-08-19 | 1994-10-21 | Samsung Electron Co Ltd | Inside power supply voltage generating circuit |
| US5363333A (en) * | 1992-09-30 | 1994-11-08 | Nec Corporation | Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process |
| JPH097370A (en) * | 1995-06-12 | 1997-01-10 | Samsung Electron Co Ltd | Generation circuit of internal power-supply voltage for semiconductor memory device |
| US6538931B1 (en) * | 1997-10-15 | 2003-03-25 | Stmicroelectronics S.A. | Methods of operating an integrated circuit with memory having an internal circuit for the generation of a programming high voltage |
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