JPS63171005A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To connect respective input/output terminals of FFs as prescribed to compare a phase difference by providing four RS FFs having NAND gate constitution and NAND gates which receive their Q outputs and inputting signals to be compared to set terminals of first and second FFs. CONSTITUTION:When a control signal 21 is '1', phases of a reference signal 6 and an input signal 7 are compared with each other as conventional. When it is '0', an FF 8 is reset and the Q output goes to '1', and a Pch FET 16 is turned off. An FF 9 is reset also, and an Nch FET 17 is turned off by inversion 16 of the -Q output. Consequently, the output of a charge pump 2 has a high impedance. Even if the reference signal 6 is disturbed or broken during this time, a pump output 18 is not changed because phase comparison is inhibited. Consequently, if this circuit is used to constitute a PLL circuit, the output of a voltage controlled oscillator VCO 4 is N-number of times as high as the frequency of the reference signal 7 by the conventional phase comparison when the control signal 21 is '1', and the charge pump output goes to the high level when the signal 21 is '0', and the state just before the change to '0' is kept to keep the output of a low-pass filter LPF 3 constant and the output of the VCO 4 is kept at a certain frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparison circuit that compares the phase difference between a reference signal and an input signal.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of a basic PLL circuit. That is, the charge pump 2 is operated according to the output of the phase comparison circuit 1, and the output of the charge pump 2 is converted into a DC voltage by the low-pass filter 3, and the voltage is controlled according to the DC output voltage or the DC output voltage obtained by amplifying this voltage. The excavation circuit 4 is operated, and the oscillation frequency fv obtained from this oscillation circuit 4 is set as the output frequency fO of this system, and it is given as an input signal to the program frequency divider circuit 5 whose division ratio is programmable, and this program frequency division is performed. The phase comparison circuit 1 compares the output of the circuit 5, that is, the signal 7 having the frequency fsig with the reference ef signal 6 having the reference frequency f. If each part in this circuit configuration is appropriately designed, the output frequency fo will be fo = N-f. Here, N is the frequency division ratio of the program frequency divider circuit 5.

FIG. 7 is a circuit diagram showing the conventional phase comparator circuit 1 used in the above PLL circuit together with a charge pump 2, and FIG. 8 is a timing chart for explaining its operation. The phase comparator circuit 1 receives a reference signal 6 and an input signal 7.
are set inputs, and AND gates 13 and 14 are provided at each reset input terminal.
Flip-flop 8, 9, this RS flip-flop 8
It is composed of an RS flip-flop 10.11 which receives each of the Q outputs of 8.9 and 10.11 as set inputs, and a NAND gate 12 which receives Q outputs of each of the RS flip-flops 8.9 and 10.11 as inputs. Further, the Q output of the RS flip-flop 10 and the output of the NAND gate 12 are supplied to the AND gate 13 provided at the reset input terminal of the RS flip-flop 8, and the AND gate 13 provided at the reset input terminal of the RS flip-flop 9 is supplied with the Q output of the RS flip-flop 10 and the output of the NAND gate 12. The Q output of the RS flip-flop 11 and the output of the NAND gate 12 are supplied to the AND gate 14 located therein. Furthermore, the output of the NAND gate 12 is RS
It is supplied to the reset input terminal of each of the flip-flops 10 and 11.

On the other hand, charge pump 2 is powered by ■. P-channel MOS connected in series between 0 and power supply V88 (ground potential)
It is composed of a transistor 16, an N-channel MoS transistor 1f, and an inverter 15 connected to the gate of the N-channel MOS transistor 1f. The Q output of the RS flip-flop 8 is connected to the gate of the P channel MOS transistor 16, and the Q output of the inverter 1 is connected to the gate of the P channel MOS transistor 16.
5 are supplied with the ○ output of the RS flip-flop 9, respectively.

Now, in the above circuit, if the phase of the input signal 7 is ahead of the phase of the reference signal 6 as shown in FIG. Only during the phase advance period of ll O+! level. On the other hand, if the phase of the input signal 7 lags behind the phase of the reference signal 6, the RS flip-flop 8
The ○ output of is at the "0" level only during the phase delay period of the input signal 7 with respect to the phase of the reference signal 6. Therefore, when the phase of the input signal 7 leads the phase of the reference signal 6, the output 18 of the charge pump 2, which receives the 0 output of the RS flip-flop 8 and the ○ output of the RS flip-flop 9, is V88('“O
If there is a delay, the phase advance becomes ■., (“1”) level, and further the reference signal @6
When the input signal 7 and the input signal 7 are in the same phase, a high impedance state occurs.

The output 18 of this charge pump 2 is then supplied to a low pass filter 3 as shown in FIG. 6, where a DC voltage for operating the voltage controlled oscillation circuit 4 is formed.

[Problem that the invention seeks to solve]

When the conventional phase comparator circuit described above is used in a PLL circuit, it continues to compare which phase of the input signal 7 no matter what state the reference signal 6 is in, as shown in FIG. Even if the frequency of the reference signal 6 to be input changes, is disturbed, or is interrupted midway, the voltage control [1 The oscillation frequency fV of the oscillator 4 follows this, so the oscillation is performed according to the change or disturbance of the reference signal 6. The disadvantage is that the frequency fV is disturbed and a constant output cannot be obtained.

(Means for Solving the Problems) The phase comparator circuit of the present invention includes four RS flip-flops, first, second, third, and fourth, each having a NAND or NOR gate configuration, and the Q of each of these RS flip-flops. A NAND gate receiving the output, provided that when the RS flip-flop has a NOR gate configuration, it has a NOR gate, and the first and second input signals to be compared are input to the set terminals of the first and second RS flip-flops. The Q outputs of the third and fourth RS flip-flops are input to the reset terminals, respectively, and the Q outputs of the first and second RS flip-flops are input to the set terminals of the third and fourth RS flip-flops, respectively.
In the phase comparator circuit to which the output is input and the output of the NAND or NOR gate is fed back to the reset terminal of each RS flip-flop, the first. The second RS flip-flop is characterized in that it has a reset terminal to which a control signal is applied.

If the frequency of the reference signal changes, becomes distorted, or is interrupted midway, inputting the 1111 signal will cause the 3rd. All of the fourth RS flip-flops are reset, and the output of the charge pump becomes a high impedance state, maintaining the state immediately before the control signal was input. Therefore, since the output voltage of the low-pass filter also maintains a constant voltage, the output voltage of the voltage controlled oscillator maintains a constant frequency, and phase comparison between the reference signal and the input signal is prohibited.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the phase comparator circuit of the present invention, and FIG. 2 is a timing chart for explaining its operation.

The phase comparator circuit 1A includes RS flip-flops 8, 9, each of which receives a reference signal 6 and an input signal 7 as set inputs, and has an AND gate 19, 20 at each reset input terminal.
It consists of an RS flip-flop 10.11 which receives the Q output of RS flip-flop 8.9 and RS flip-flop 10.11 as set input, and a NAND gate 12 which receives Q output of each of RS flip-flop 8.9 and RS flip-flop 10.11 as input. The Q output of the RS flip-flop 10, the output of the NAND gate 12, and the control signal 21 are supplied to the AND gate 19 provided at the reset input end, and the AND gate 19 provided at the reset input end of the RS flip-flop 70 20 is supplied with the Q output of the RS flip-flop 11, the output of the NAND gate 12, and the control signal 21. In addition, Nand Gate 12
The outputs of are supplied to the reset input terminals of the RS flip-flops 10 and 11, respectively. On the other hand, charge pump 2
is a P-channel MOS transistor 16 and N connected in series between the voltage mv, o and the power supply ■33 (ground potential).
It is composed of a channel MOS transistor 17 and an inverter 15 connected to the gate of the N-channel MOS transistor 17. The gate of the P-channel MOS transistor 16 receives the ◇output of the RS flip-flop 8, and the Φ outputs are respectively supplied.

Next, the operation of this embodiment will be explained using the timing chart of FIG. First, during the period when the control signal 21 is at the "1" level, the operation is the same as that of the conventional phase comparison circuit shown in FIG. 7, and the phase comparison between the reference signal 6 and the input signal 7 is performed. When the control signal 21 is at the "0" level, the RS flip-flop 8 is reset and the Q output becomes "1", so the P-channel MOS transistor 16 is turned off. on the other hand,
Since the RS flip-flop 9 is also reset at the same time as the RS flip-flop 8, the Q output becomes 1", and the output inverted by the inverter 15 becomes "O".
N-channel MOS transistor 17 is also turned off. Therefore, the output 18 of the charge pump 2 becomes a high impedance state and maintains the state immediately before the control signal 21 was turned ON. During this period, even if the frequency of the reference signal 6 changes, is disturbed, or is interrupted, any phase comparison of the input signal 7 is prohibited, so the output 18 of the charge pump 2
does not change.

Therefore, when the 911 circuit shown in FIG. 6 is configured using this phase comparison circuit, when the control signal 21 is at the 1" level, phase comparison is performed as in the conventional case, and the output of the voltage controlled oscillator 4 is set at the frequency of the reference signal 7. The frequency is N times that of υ control signal 2.
When 1 is at the OII level, the output 18 of charge pump 2
becomes a high impedance state and the control signal 21 becomes ``0''.
Since the state immediately before reaching the level is maintained and the output voltage of the low-pass filter 3 is also maintained at a constant voltage, during this time the reference signal 6
Even if the frequency of the voltage-controlled oscillator 4 changes, is disturbed, or interrupted, the output of the voltage-controlled oscillator 4 maintains a constant frequency.

FIG. 6 is a circuit diagram specifically showing the phase comparator circuit of the first embodiment described above, in which the four RS flip-flops are constructed of NAND gates. The configuration of the RS flip-flop in this case is that one input of the first NAND gate is used as the set terminal, this output is used as the Q output, one input of the second NAND gate is used, and the other input is used as the reset terminal, and this output is outputted as 0. This is the other input of the first NAND gate. However, if the RS flip-flop has a NAND gate configuration and a three-man AND gate is connected to the reset terminal, the reset terminal is logically equivalent to three RS flip-flops, so
The reference numerals in the figure refer to the AND gate 19 shown in FIG.
and RS flip-flop8. The AND gate 2o and the RS flip-flop 9 correspond to the RS flip-flops 22 and 23 each having three reset terminals, and the rest is the same as in FIG.

FIG. 4 is a circuit diagram specifically showing a second embodiment of the phase comparison circuit of the present invention, and FIG. 5 is a timing chart for explaining its operation. In this embodiment, the four RS flip-flops are composed of NOR gates, and the NOR gate 24 receives the Q outputs of these four RS flip-flops. The configuration of the RS flip-flop in this case is that one input of the first NOR gate is used as a set terminal, this output is set as Q, one input of the second NOR gate, the other input is set as a reset terminal, and this output is set as the ◇ output. This is the other input of the No. 1 NOR gate.

However, if the RS flip-flop has a NOR gate configuration, the AND gates 19 and 20 in FIG. Since the reset terminals are equivalent to three RS flip-flops, the reference numerals in the figure represent the AND gate 19 shown in FIG. 1 replaced with an OR gate, and the RS flip-flop 8. The AND gate 20 turned into an OR gate and the RS flip-flop 9 correspond to the RS flip-flops 22 and 23, respectively. In this case, the charge pump 2A is powered by ■DD
P channel MO connected in series between and power supply ■88
It is composed of an S transistor 16, an N-channel MOS transistor 17, and an inverter 15 connected to the gate of the P-channel MOS transistor 16. The inverter 15 is supplied with the Φ output of the RS flip-flop 22, and the The ◇ output of the RS flip-flop 23 is supplied to the gate.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

During the period when the control signal 21 is at the “0” level, if the phase of the input signal 7 is ahead of the phase of the reference signal 6, R
The ◇output of the S flip-flop 23 is at 1" level only during the phase lead period of the input signal 7 with respect to the phase of the reference signal 6, and when it is delayed, the ◇output of the RS flip-flop 22 becomes the input signal for the phase of the reference signal 6. It remains at the "1" level for a phase delay period of 7. During the period when the control signal 21 is at the "1" level, the RS flip-flop 23 is reset and the output becomes 0", so the N-channel MOS transistor 17 is turned off. On the other hand, since the RS flip-flop 22 is also reset at the same time as the RS flip-flop 23, the Q output becomes "O" and is inverted by the inverter 15 to become "1", so the P-channel MOS transistor 16 is also turned off.Therefore, the charge pump The 2A output 18 enters a high impedance state and maintains the state immediately before the control signal 21 becomes 1''. During this time, even if the frequency of the reference signal 6 changes, is disturbed, or is interrupted, the output 18 of the charge pump 2 does not change because any phase comparison of the input signal 7 is prohibited.

Therefore, when the PLL circuit shown in FIG. 6 is configured using this phase comparison circuit, when the control signal 21 is at the "O" level, phase comparison is performed as in the conventional case, and the output of the voltage controlled oscillator 4 is at the frequency of the reference signal 7. The frequency is N times that of the control signal 21.
When is at the "1" level, the output 18 of the charge pump 2 becomes a high impedance state, and the control signal 21 maintains the state immediately before reaching the "1" level, and the output voltage of the low-pass filter 3 also maintains a constant voltage. Therefore, even if the frequency of the reference signal 6 changes, is disturbed, or is interrupted during this period, the output of the voltage controlled oscillator 4 maintains a constant frequency. however,
In the first embodiment, the phase comparison was performed at the falling timing of each of the reference signal 6 and input signal 7.
In the second embodiment, phase comparison is performed at the rising timing.

(Effects of the Invention) As explained above, the present invention can prevent the phase of the reference signal from being compared with the input signal by using the control signal whenever the frequency of the reference signal changes or is disturbed. When a PLL circuit is configured, it is possible to always obtain a stable oscillation frequency as the voltage controlled oscillator output without being affected by changes, disturbances, or interruptions in the frequency of the reference signal, and prevents the spread to the outside of the PLL circuit. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the phase comparison circuit of the present invention, FIG. 2 is a timing chart for explaining the operation of the first embodiment, and FIG. 3 is a circuit of the first embodiment. 4 is a block diagram specifically showing the circuit of the second embodiment of the present invention, FIG. 5 is a timing chart showing the operation of the second embodiment, and FIG. 6 is a block diagram specifically showing the circuit of the second embodiment of the present invention. FIG. 7 is a block diagram of a PLL circuit, FIG. 7 is a diagram of a conventional phase comparison circuit, and FIG. 8 is a timing chart for explaining the operation of the conventional circuit of FIG. DESCRIPTION OF SYMBOLS 1... Phase comparison circuit, 2,2A... Charge pump, 3... Low pass filter, 4... Voltage controlled oscillation circuit, 5... Program frequency divider circuit, 6... Reference signal,
7...Input signal, 8-11.22.23...RS flip-flop, 12...NAND gate, 24...
NOR gate, 15...inverter, 21... control signal. Patent Applicant: NEC IG Microcomputer System Co., Ltd. Figure 3 α Fraction

Claims (1)

[Scope of Claims] Four RS flip-flops, first, second, third, and fourth, each having a NAND or NOR gate configuration, and a NAND gate that receives the Q output of each of these RS flip-flops, provided that the RS flip-flop is a NOR gate. In the case of the configuration, the first and second input signals to be compared are input to the set terminals of the first and second RS flip-flops, and the third and fourth input signals are input to the reset terminals, respectively. The Q output of the RS flip-flop is input, and the third and fourth RS
The set terminal of the flip-flop has the first and second terminals, respectively.
In the phase comparator circuit, the Q output of the RS flip-flop is input, and the output of the NAND or NOR gate is fed back to the reset terminal of each RS flip-flop. 1. A phase comparator circuit characterized by having a reset terminal.