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JPS63164335A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS63164335A
JPS63164335A JP31202786A JP31202786A JPS63164335A JP S63164335 A JPS63164335 A JP S63164335A JP 31202786 A JP31202786 A JP 31202786A JP 31202786 A JP31202786 A JP 31202786A JP S63164335 A JPS63164335 A JP S63164335A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor layer
film
grown
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31202786A
Other languages
Japanese (ja)
Inventor
Takeshi Konuma
小沼 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31202786A priority Critical patent/JPS63164335A/en
Publication of JPS63164335A publication Critical patent/JPS63164335A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To relax the warpage due to a difference between the thermal expansion coefficients of an Si substrate and GaAs semiconductor layers by burying recessed parts formed in the substrate with an insulator film consisting of Si. CONSTITUTION:Recessed parts 2 are formed in the desired regions of the main surface of an Si substrate 1. An Si oxide film 3 is deposited and the SiO2 film is remained in the recessed parts only by a normal method. Moreover, if necessary, nitrogen ions (N<+>) are implanted and an Si nitride (Si3N4) film 4 is formed. After that, GaAs semiconductor layers 5A and 5B, for example, are grown. The single crystalline GaAs semiconductor layer 5A is grown on the Si substrate and the polycrystalline GaAs semiconductor layer 5B is grown on the SiO2 films. After a substrate is formed, a device is formed on the semiconductor layer 5A. When the Si nitride film 4 is formed by an ion implantation method, the Si nitride film 4 is formed in contact as close as possible to the surface of the Si substrate 1 and also, holding the Si substrate surface in a single crystal.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体基体に関し、シリコン(Si)基板と
ガリウム・ヒ素(Ga b )系半導体層とを一体化し
た半導体基体に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor substrate, and more particularly, to a semiconductor substrate in which a silicon (Si) substrate and a gallium arsenide (Gab) based semiconductor layer are integrated.

従来の技術 Si半導体とGaAg系の半導体を一体化することU、
GaAs 系半導体が高電子移動度、発光機能を有し、
一方81半導体は大口径高品質結晶が得られ、かつデバ
イス製作技術が確立しているので、Si基板上に高集積
デバイスを、 GaJu  系半導体に高速デバイス、
発光デバイス等を集積する複合デバイスとして有望であ
る。
Conventional technology Integrating Si semiconductor and GaAg semiconductor
GaAs-based semiconductor has high electron mobility and light emitting function,
On the other hand, for 81 semiconductors, large-diameter, high-quality crystals can be obtained, and device manufacturing technology has been established, so it is possible to fabricate highly integrated devices on Si substrates, high-speed devices on GaJu-based semiconductors,
It is promising as a composite device that integrates light-emitting devices and the like.

S1基板上へのcaAsの成長法としては、81基板上
にMBIC法(Mo1ecular Beam ICp
itax3r法)或B M OOV D法(Metal
 Organic Chemical VaporDe
position)を用いてGaAsを堆積し、GaA
gにデバイスを形成している。たとえばp型S1 基板
にMBE法を用い、アンドープGaAa 層、活性層と
なるキャリヤ濃度10cIn 、厚み0.2μmのn型
GtAs 層、オーミック層となるキャリヤ濃度101
8菌、厚み0.4μmのn  GaAs層を順次形成す
る。
As a method for growing caAs on the S1 substrate, the MBIC method (Molecular Beam ICp) is used on the 81 substrate.
itax3r method) or B M OOV D method (Metal
Organic Chemical VaporDe
position) to deposit GaAs.
A device is formed at g. For example, using the MBE method on a p-type S1 substrate, an undoped GaAa layer, a carrier concentration of 10 cIn to form an active layer, an n-type GtAs layer with a thickness of 0.2 μm, and a carrier concentration of 101 to form an ohmic layer.
8 bacteria and a 0.4 μm thick nGaAs layer were sequentially formed.

しかる後通常の写真食刻法、リセス法、真空蒸着法を用
いて、ゲート電極、ソース電極、ドレイン電極を形成し
て、電界効果トランジスタ(FIT)が形成される。こ
の方法に大口径で価格の安い81基板を用い、その基板
上に薄層のGsム3 を堆積し、GaAs 基板の低価
格化を図ったものである。
Thereafter, a gate electrode, a source electrode, and a drain electrode are formed using conventional photolithography, recessing, and vacuum evaporation methods to form a field effect transistor (FIT). In this method, a large-diameter, inexpensive 81 substrate is used, and a thin layer of Gs 3 is deposited on the substrate, thereby reducing the cost of the GaAs substrate.

発明が解決しようとする問題点 この従来例でr4、Si基板上に直接GILA8 半導
体層を形成しているが、81基板の口径が大きくなると
、81基板とGILAS層の熱膨張係数の差のため、そ
シが発生する。例えば2インチの直径を有する81基板
上に2μmのGaAs 層を形成すると約20μmのそ
りが発生し、プロセス上微細加工が出来ない、プロセス
工程で基板が割れる等の問題が生じる。又集積回路等G
aAs 半導体層に形成した場合、シリコン基板を通し
て電流が流れる、いわゆる素子間の分離が不充分である
という問題が生じる。
Problems to be Solved by the Invention In this conventional example, the GILA8 semiconductor layer is formed directly on the r4, Si substrate, but as the diameter of the 81 substrate increases, due to the difference in thermal expansion coefficient between the 81 substrate and the GILAS layer. , soshi occurs. For example, when a 2 μm thick GaAs layer is formed on an 81 substrate having a diameter of 2 inches, a warpage of about 20 μm occurs, causing problems such as the inability to perform fine processing and the substrate breaking during the process. Also, integrated circuits etc.
When formed in an aAs semiconductor layer, a problem arises in that current flows through the silicon substrate, so-called isolation between elements is insufficient.

本発明ニ81基板上にGiLAg系半導体層を形成した
半導体基体に関し、大口径でそシが発生せずかつ素子間
分離のなされた半導体基体を提供するものである。
The present invention relates to a semiconductor substrate in which a GiLAg-based semiconductor layer is formed on a D-81 substrate, and provides a semiconductor substrate with a large diameter, no rips, and isolation between elements.

問題点を解決するための手段 本発明[Si基板の所望の領域に凹部を形成し、前記凹
部をSlからなる絶縁物で埋め、しかる後凹部間にシリ
コンを絶縁物化するイオン注入種をイオン注入して、凹
部間を絶縁物で連結した後、上記81基板上にGILA
jl系半導体層全半導体層なる半導体基体に関するもの
である。
Means for Solving Problems The present invention [forming a recess in a desired region of a Si substrate, filling the recess with an insulator made of Sl, and then implanting an ion implantation species between the recesses to make the silicon an insulator After connecting the recesses with an insulator, GILA is placed on the 81 substrate.
The present invention relates to a semiconductor substrate consisting of all semiconductor layers.

作用 Si基板に形成した凹部を81からなる絶縁物で埋める
ことで、81基板とG&ムS系半導体層の熱膨張係数の
差異によるそシを凹部に埋めた絶縁物で緩和することが
出来、イオン注入法で形成した絶縁物で凹部間を連結す
ることでGILA!! 半導体層に形成した素子を電気
的に分離することが出来る。
By filling the recesses formed in the active Si substrate with an insulator made of 81, the distortion caused by the difference in thermal expansion coefficient between the 81 substrate and the G&M S-based semiconductor layer can be alleviated by the insulator filled in the recesses. By connecting the recesses with an insulator formed by ion implantation, GILA! ! Elements formed in a semiconductor layer can be electrically isolated.

実施例 以下本発明の一実施例を詳細に説明する。Example An embodiment of the present invention will be described in detail below.

第1図〜第4図は本発明の一実施例の半導体基体の製造
工程を示すものである。
1 to 4 show the manufacturing process of a semiconductor substrate according to an embodiment of the present invention.

81基板1の主面の所望領域に腐食法を用いて凹部2を
形成する(第1図) 。OV D (Chemical
Vapor Deposition)法を用いて、シリ
コン酸化膜(Si02)3を堆積し、通常の方法で凹部
のみに5102  を残存せしめる(第2図)。イオン
注入法を用いて、注入種として窒素イオン(N )を2
60KevテロX1d6Ci2イオン注入シ、950’
Cで3時間熱処理し、シリコン窒化物(5i5N4 )
 4を形成する(第3図)。しかる後M B R(Mo
leoularBeam I!pi、taxy)法を用
いて、G&ムS半導体層6ム。
81 A recess 2 is formed in a desired region of the main surface of the substrate 1 using an erosion method (FIG. 1). OV D (Chemical
A silicon oxide film (Si02) 3 is deposited using a vapor deposition method, and 5102 is left only in the recessed portions using a conventional method (FIG. 2). Using the ion implantation method, nitrogen ions (N) are implanted as the implantation species.
60Kev Terror X1d6Ci2 ion implantation, 950'
Heat treated with C for 3 hours to form silicon nitride (5i5N4)
4 (Figure 3). After that, M B R (Mo
leularBeam I! G & M S semiconductor layer 6 M using the pi, taxi) method.

6Bを成長する。81基板上には単結晶のGILA!1
半導体層6ムが成長し、8i02上には多結晶のGIL
A!i半導体層6Bが成長する(第4図)。第4図の基
体を形成した後、単結晶GtAJ 半導体層6ムにデバ
イスを形成する。第3図で肝要なことは、シリコン窒化
物4をイオン注入法で形成する際、シリ ・コン窒化物
4をシリコン基板1の表面に出来るだけ接し、かつシリ
コン基板表面を単結晶に保って形成することである。
Grow 6B. Single crystal GILA is on the 81 substrate! 1
A semiconductor layer of 6 μm is grown, and a polycrystalline GIL is grown on 8i02.
A! An i-semiconductor layer 6B grows (FIG. 4). After forming the substrate shown in FIG. 4, devices are formed on the single crystal GtAJ semiconductor layer 6. What is important in Fig. 3 is that when silicon nitride 4 is formed by ion implantation, the silicon nitride 4 is in contact with the surface of silicon substrate 1 as much as possible, and the silicon substrate surface is kept in a single crystal state. It is to be.

実施例ではGILAS 半導体層6を形成したが、ム1
l−2GazAs、 In1−−ILzAS 等或はこ
れらの多層構造を形成しても良い。GaムS半導体層の
成長法として、MBE法を用いたが、MOCVD法を用
いても良いことば勿論である。
In the example, GILAS semiconductor layer 6 was formed, but M1
1-2GazAs, In1--ILzAS, etc. or a multilayer structure thereof may be formed. Although the MBE method was used as the method for growing the Ga-S semiconductor layer, it goes without saying that the MOCVD method may also be used.

発明の詳細 な説明した様に本発明は、Si基板に凹部を形成し、凹
部をシリコンからなる絶縁物で埋めることで、81基板
上にGaAs系半導体層を形成したとき、凹部に埋め込
まれたシリコンからなる絶縁物によp、Si基板とGI
LAII系半導体層の熱膨張係数の差によるそシが緩和
される。又シリコンからなる絶縁物を埋め込んだ凹部間
のシリコン表面近傍にシリコンの絶縁物を形成している
ので、GaAg系半導体層に形成したデバイスの電気的
な分離を行うことが出来る。
DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention involves forming a recess in a Si substrate and filling the recess with an insulator made of silicon. With an insulator made of silicon, a Si substrate and a GI
The damage caused by the difference in thermal expansion coefficients of the LAII-based semiconductor layers is alleviated. Furthermore, since the silicon insulator is formed near the silicon surface between the recesses in which the silicon insulator is embedded, it is possible to electrically isolate devices formed in the GaAg-based semiconductor layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は本発明の一実施例の半導体基体を説明
するための工程図である。 1・・・・・・81 基板、2・・・・・・凹部、3・
・・・・・シリコン酸化物、4・・・・・・シリコン窒
化物、6ム・・・・・・単結晶GajLi 半導体層、
6B・・・・・・多結晶GaAs 半導体層。
1 to 4 are process diagrams for explaining a semiconductor substrate according to an embodiment of the present invention. 1...81 Substrate, 2... Concavity, 3.
...Silicon oxide, 4...Silicon nitride, 6M...Single crystal GajLi semiconductor layer,
6B...Polycrystalline GaAs semiconductor layer.

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン基体に凹部を設け、上記凹部をシリコン
からなる絶縁物で埋め、上記シリコン基体上にGaAs
系の半導体層を形成してなる半導体基体。
(1) A recess is provided in the silicon substrate, the recess is filled with an insulator made of silicon, and a GaAs layer is placed on the silicon substrate.
A semiconductor substrate formed by forming a semiconductor layer.
(2)シリコンからなる絶縁物で埋められた凹部間にシ
リコン基体を絶縁物化する注入種をイオン注入し、絶縁
物で上記複数の凹部間を絶縁物で連結するようにした特
許請求の範囲第1項記載の半導体基体。
(2) An implantation species that turns the silicon substrate into an insulator is ion-implanted between the recesses filled with an insulator made of silicon, and the plurality of recesses are connected by the insulator. The semiconductor substrate according to item 1.
JP31202786A 1986-12-26 1986-12-26 Semiconductor substrate Pending JPS63164335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31202786A JPS63164335A (en) 1986-12-26 1986-12-26 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31202786A JPS63164335A (en) 1986-12-26 1986-12-26 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS63164335A true JPS63164335A (en) 1988-07-07

Family

ID=18024337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31202786A Pending JPS63164335A (en) 1986-12-26 1986-12-26 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS63164335A (en)

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