JPS63131740A - Serial data transmitter - Google Patents

Abstract

PURPOSE:To correct a transmission error automatically without adding error correcting information by detecting its transmission error at reception side when a transmission error takes place and retransmitting the transmitted data from the transmission side. CONSTITUTION:After a parallel conversion signal 16 is outputted, if a normality reception confirming signal 17 is not returned from a serial input controller 7 in the specific time, a serial output controller 4 discriminates it as the occurrence of a transmission error. Then the serial data shift clock 15 is outputted again and the serial data 14 is sent between the parallel input serial output shift register 3 with a serial input and a serial input/parallel output shift register 5. The serial data 14 in this case is the same data as the preceding data. Thus, the data sent again is received as a received data 18 by a reception side host processor interface 8 only when no transmission error takes place by the parity error signal and the transmission error is corrected automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a serial data transmission device that automatically corrects a data transmission error when it occurs.

(Prior Art) Conventionally, in this type of serial data transmission device, when a transmission error occurs, the receiving side only detects the error, or the transmitting side adds error correction information to the data and transmits it. In some cases, the receiving side corrects the error using the error correction information.

(Problems to be Solved by the Invention) The former method only detects errors and has the disadvantage that they cannot be corrected. In addition, the latter adds error correction information to the data, which not only increases the amount of data to be transmitted, but also requires complex circuits to create error correction information, decode error correction information, and correct errors. The disadvantage is that it requires circuitry.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a serial data transmission device that automatically corrects transmission errors without adding error correction information.

(Means for Solving the Problems) In order to solve the above-mentioned problems and achieve the above objects, the present invention provides a serial data transmission device that transmits parallel data consisting of transmission data and parity bit data for each frame. a first conversion means for converting into serial data and outputting the converted serial data for each frame; a storage means for storing the serial data for each frame; and a second conversion means for receiving the serial data and converting it into parallel data. a parity checker that checks parity bit data included in the parallel data and outputs a check signal, and performs the second conversion only when it is determined that no transmission error has occurred based on the check signal. receiving means for receiving and processing the parallel data of the means as received data, and retransmission command means for instructing retransmission of the transmitted data only when it is determined based on the check signal that a transmission error has occurred, The transmission error is automatically corrected by transmitting the data stored in the storage means again based on a command from a retransmission command means.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The serial data transmission device of the present invention includes a transmitting side host processor interface 1, a parity bit generator 2, a parallel input serial output shift register 3 with serial input, a serial output controller 4, a serial input parallel output shift register 5, It consists of a parity checker 6, a serial input controller 7, and a receiving side host processor interface 8.

Next, the operation will be explained.

The sending side host processor interface 1 sends the sending data 10 to a parity bit generator 82 for each frame.
and output to the parallel manual serial output shift register 3 with serial input. Parity bit generator 2 generates parity bit 11 from transmission data 10 and outputs it to parallel input serial output shift register 3 with serial input.

Next, the sending side host processor interface 1 outputs the sending data output signal 12 to the parallel manual serial output shift register 3 with serial input and the serial output controller 4. The parallel manual serial output shift register 3 with serial input receives transmission data 10 and parity bit data 11 in parallel in synchronization with the transmission data output signal 12. Further, when the serial output controller 4 receives the transmission data output signal 12, it outputs a serial data shift clock 15 to the parallel input serial output shift register 3 with serial input and the serial input parallel output shift register 5. The parallel input serial output shift register 3 with serial input converts parallel data (transmission data 1o+parity bit 11) into serial data in synchronization with the serial data shift clock 15, and outputs this serial data 14. on the other hand,
The serial input parallel output shift register 5 inputs the serial data 14 while shifting it bit by bit in synchronization with the serial data shift clock 15. When the output of one frame of serial data 14 from the parallel input serial output shift register 3 with serial input is completed, the serial output controller 4 transfers the parallel conversion signal 16 to the serial input parallel output shift register 5 and the serial input controller 7. Output to. The serial input parallel output shift register 5 receives the parallel conversion signal 1
6, the serial input data is converted into multi-bit parallel data, and this converted data is converted into received data 1.
8 to the parity checker 6 and the host processor interface 8 on the receiving side. The parity checker 6 performs a parity check on the parity pit data included in the received data 18 and outputs a parity error signal 19 to the serial input controller 7 if a parity error occurs. When the serial input controller 7 receives the parallel conversion signal 16, it checks the parity error signal 19, and if no parity error has occurred, it outputs a normal reception end signal 20 to the host processor interface 8 on the receiving side, and also confirms normal reception. A confirmation signal 17 is output to the serial output controller 4.

Furthermore, the receiving side host processor interface 8
When the normal reception end signal 20 is input, the reception data 18 is input. When the serial output controller 4 receives the normal reception confirmation signal 17, it outputs a normal transmission end signal 13 to the host processor interface 1 on the sending side. When the transmitting side host processor interface 1 receives the normal transmission end signal 13, the transmitting side host processor interface 1 transmits the transmission data 1 of the next frame.
Outputs 0.

Next, the operation when a parity error occurs will be explained.

Serial input controller 7 outputs parity error signal 1
9, if it is determined that a parity error has occurred, the serial input controller 7 does not output the normal reception confirmation signal 17 and the normal reception end signal 20. If the normal reception confirmation signal 17 is not returned from the serial input controller 7 even after a predetermined period of time has elapsed after outputting the parallel conversion signal 16, the serial output controller 4 determines that a transmission error has occurred and outputs the serial data again. A shift clock 15 is output, and serial data 14 is transmitted between the parallel input serial output shift register 3 with serial input and the serial input parallel output shift register 5. The serial data 14 at this time is that the serial data 14 output last time is fed back to the serial input terminal 9 of the parallel input serial output shift register 3 with serial input, and the fed back serial data 14 is fed back to the serial input terminal 9 of the parallel input serial output shift register 3 with serial input. Since it is stored in the storage means built into 3, it is the same data as last time.

Therefore, the data that has been retransmitted is received as received data 18 by the host processor interface 8 on the receiving side only when no transmission error occurs due to the parity error signal, and the transmission error can be automatically corrected.

The above operations are repeated to transmit serial data.

Note that when a transmission error occurs m times in a row during data transmission of the same frame, the serial input controller 7 outputs the error output signal 21 m times to the receiving side host processor interface 8, indicating that the transmission line has failed. Notify the receiving host processor.

(Effects of the Invention) As explained above, according to the present invention, when a transmission error occurs, the receiving side detects the transmission error and the transmitting side allows the transmitting data to be retransmitted, without adding error correction information. Transmission errors can be corrected automatically. Therefore, the amount of data to be transmitted does not become enormous, and a complicated circuit for correcting errors is not required, so that it is possible to transmit highly reliable serial data with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Sending side host processor interface, 2...
...Parity pit generator, 3...Parallel input serial output shift register with serial input, 4...
・Serial output controller, 5... Serial input parallel output shift register, 6... Parity checker, 7... Serial input controller, 8... Receiving side host processor interface, 9... Serial input terminal, 10 ... Transmission data, 11 ... Parity pit, 12 ... Transmission data output signal, 13 ... Normal transmission end signal, 14 ... Serial data, 15 ...
Serial data shift blocker, 16... Parallel conversion No. 3, 17... Normal reception confirmation signal, 18... Received data, 19... Parity error signal, 2o... Normal snow catching end signal, 21 ...m times error signal.

Claims (1)

[Claims] a first conversion means for converting parallel data consisting of transmission data and parity bit data into serial data for each frame and outputting the converted serial data for each frame; a storage means for storing the serial data for each frame; a second conversion means that receives the serial data, converts it into parallel data, and outputs the converted parallel data; a parity checker that checks parity bit data included in the parallel data and outputs a check signal; receiving means for receiving and processing the parallel data of the second converting means as received data only when it is determined that no transmission error has occurred based on the check signal; retransmission commanding means for instructing retransmission of the transmitted data only when the transmission error is determined, and retransmitting the data stored in the storage means based on a command from the retransmission commanding means to automatically correct the transmission error. A serial data transmission device characterized by: