JPS63120528A - Double error correction circuit - Google Patents

Abstract

PURPOSE:To provide error correction capability and error detection capability without increasing a circuit scale by selecting a decoding method based on decoded processing information generated by a 1st decoder and applying decoding correction processing according to a selected decoding method. CONSTITUTION:A decoding correction signal is generated from a coding data according to an optional decoding method in response to the coding data, the 1st decoder 21 outputting decoding processing information representing the error detection state and the correction state and the decoding correction signal, and a 2nd decoder 22 selecting the decoding method based on the decoding processing information fetched by the 1st decoder 21 and applying decoding and correcting the decoding correction signal according to the selected decoding method are provided. The decoding is selected in response to the content of the coding data fetched by the 1st decoder 21, the decoding correction signal is generated by applying decoding and correction to the code data. Simultaneously, the decoding processing information (f) representing the error position and its correcting state is generated. The 1st decoder 21 sends the decoding correction signal and the decoding processing information (f) to the 2nd decoder 22, the 2nd decoder selects the decoding method based on the decoding processing information (f) to decode and correct the decoding correction signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a double error 9 correction circuit used in information storage devices and the like.

Conventional technology Conventionally, coded data is decoded in one or two stages so that data arranged in a matrix is sequentially processed in the vertical and horizontal directions to increase the error correction capability of two pages. Sometimes corrections were made. An example of a circuit that performs such double error correction is a double error correction circuit shown in FIG.

This double error correction circuit includes a first decoder 1 that inputs code data a and performs error correction on the code data a in the vertical direction, and a second decoder 11 that performs error correction on the data a in the horizontal direction.
It has The first decoder 1 includes one decoding circuit 2 and a correction circuit 3 corresponding to the decoding circuit 2.

The second decoder 11 includes a decoding circuit 4, a correction circuit 5, a first decoding and correction means 6 having a predetermined degree of correction processing, a decoding circuit 7, and a correction circuit 8, and is different from the first decoding and correction means 6. The second decoding and correction means 9 having a correction processing level and the decoding property selection information are input, and the first decoding and correction means 6 and the second decoding and correction means 9 are switched and used according to this selection information. It has a selection unit 10 that decodes and corrects data a and outputs it as information data C. Here, the degree of correction processing refers to the degree of re-correction processing in the second decoding 3-Behno device 11, taking into consideration the possibility of erroneous correction in the first decoder 1. For example, the second decoder 11 determines that the error correction processing performed by the first decoder 1 is correct, and processes the error correction processing to increase the probability of correcting the erroneously corrected data to the original data. In the following, this will be tentatively referred to as ``processing with increased detection capability''.

In the opposite case, even if there is a possibility that the first decoder 1 has made an erroneous correction, if the second decoder 1 takes action that emphasizes the correction operation of the first decoder 10, then the following , this is tentatively called ``processing with improved correction ability''.

In this double error correction circuit, the degree to which code data should be corrected is specified by decoding selection information.
By inputting this decoding property selection information to the selection section 10, it is set in advance so that either the first decoding correction means 6 or the second decoding correction means 9 is used. When code data a is input to the first decoder 1 in this state, decoding and correction are performed in the vertical direction, and decoding processing information d indicating the decoding processing status here is sent from the decoding circuit 2 to the decoding circuit 4.
and is output to the decoding circuit 7. Either of the decoding and correction means 6 or 7 selected by the decoding property selection information S performs decoding and correction processing on the encoded data a in the horizontal direction while referring to the decoding processing information d, and the processing result is used as the information data C.
Output as .

Problems to be Solved by the Invention By the way, by applying the double error correction circuit as described above to a storage medium such as a CD in which a data area and a management information area for that data are recorded separately, can be effectively decoded using a decoding method with high correction ability, and management information can be effectively decoded using a decoding method with high detection ability.

However, in performing decoding processing by switching the degree of correction processing according to the information content, in the conventional double error correction circuit as described above, the first decoding processing means 6 and the second decoding processing means 6
There is a problem in that at least two circuits each having a different degree of correction processing, such as the decoding processing means 9, must be provided, resulting in an increase in circuit scale. on the other hand,
The dual encoding system has a characteristic that the error correction ability and error detection ability change by passing decoding information between the first stage processing and the second stage processing 5 pages at the time of decoding.

The present invention has been made in view of the above-mentioned circumstances, and utilizes the above-mentioned characteristics of the double-encoding method to realize double error correction and error detection capabilities without increasing the circuit scale. The purpose is to provide circuits.

Means for solving the problem Generate a decoded correction signal from coded data according to an arbitrary decoding method according to this coded data, and output decoding processing information and a decoded correction signal indicating the error detection status and its correction status. It is characterized by comprising a first decoder and a second decoder that selects a decoding method based on the decoding processing information taken in from the first decoder and decodes and corrects the decoded correction signal according to the selected decoding method. shall be.

The decoding is selected according to the contents of the coded data taken into the first decoder, and the coded 6 page data is decoded and corrected according to the decoding method of , and a decoded correction signal is generated.

At the same time, decoding processing information indicating the error position of coded data and its correction status is generated. The first decoder sends a decoded correction signal and decoded processing information to the second decoder. The second decoder selects a decoding method based on the decoding processing information, and decodes and corrects the decoded correction signal according to the decoding method.

Embodiment FIG. 1 is a schematic block diagram showing a double error correction circuit according to an embodiment of the present invention.

This double error correction circuit inputs code data a and performs error correction on it in the vertical direction, and a first decoder 21 that inputs the processing result of the first decoder 21 and performs error correction on it in the horizontal direction. It has a second decoder 22.

The first decoder 21 includes one decoding circuit 23 and a correction circuit 24 corresponding to this decoding circuit.

The second decoder 22 includes one decoding circuit 5 and this decoding circuit 5
It is composed of a correction circuit 26 corresponding to.

Decoding method selection information e indicating decoding methods AXB and C that perform the processing shown in Table 1 is input to the decoding circuit n and the decoding circuit 5, and the first decoder According to the processing content of 21, decoding process information f indicating the content is outputted from the decoding circuit 23 to the decoding circuit section. Note that regardless of the designation of the decoding method A or BX'C by the decoding processing information f, the first decoder 21 and the second decoder 22 are set in advance to perform the processing of the decoding method as described later. has been done.

Note that in this embodiment, the code characteristic is set to a minimum distance of 5. Further, the first decoder 21 and the second decoder 22 can perform up to two correct error corrections.

The operation of the double error correction circuit configured as described above will be explained below.

First, when code data a is input to the first decoder, decoding method A is selected from decoding process information e according to the content of code data a.
The encoded data a is decoded and corrected according to the selected decoding method, which is either B or C, which is preset, to generate a decoded correction signal. Also, at this time, code data a
Decoding processing information f is generated by determining the error portions, their number, and their correction status. In this case, if the minimum distance is 5 and there are two or more errors, correction processing is performed by the correction circuit 24 as shown in Table 2.

If there are three or more errors in the second table size on page 10, no corrections will be made (see Table 2). Then, two errors are corrected, and decoding method A
, B is selected, the flag of the decoding processing information f is set to 1, and when decoding method C is selected, the flag of the decoding processing information f is set to O. Note that when there is one or less errors, the flag of the decoding processing information f is set to 0, and when there are three or more errors, the flag of the decoding processing information f is set to 1 (processed according to the decoding method).

After the encoded data a is processed by the first decoder 21, it is inputted to the second 11-heno decoder 22. In parallel with this, the decoding processing information f and the decoding property selection information e with the flags set as described above are input to the second decoder 22, respectively. and,
The second decoder 22 uses the decoding processing information f to determine the decoding method AXB of the decoding property selection information e.

Select either C or a pre-prepared decoding method and perform the processing shown in Table 3 according to the selected decoding method. If it is determined that this is the case, the decoding process is performed. In this case, it is impossible to correct three or more errors, and when it is determined that there are three or more errors, no correction is performed, and when one error is detected, correction is performed on this one error. Further, when it is determined that there are one or less errors or three or more errors, the number of matching positions (described later) is not calculated.

When the second decoder 22 determines that there are two errors, the processing corresponding to the decoding methods AXB and C as well as the decoding methods applied in relation to the decoding methods AXB and C are performed as shown in Table 3. Processing is performed. If it is determined that there are two errors, regardless of the decoding method, the decoding circuit 5 first detects the error part, and this part matches the error part detected by the first decoder 21. The number of matches (the number of matching positions) is calculated. A comparison is made to see if both parts match. If the second decoder 22 detects an error overlapping the part in which the first decoder 21 detected an error, the first decoder 21 detects an error. 21 is not an error but a result of correct processing." On the other hand, if they do not match, "the correction made in the first decoder 21 was incorrectly corrected (
It may be determined that the information was incorrectly corrected. in this case,
If decoding method A is set and the number of position matches is "0", no correction processing is performed, and the number of position matches is "1".
In this case, two corrections are made. Also, decryption method B''!
or C is set, the number of position matches is "0"
, "1" are treated as unprocessed. Note that when the number of matching positions is calculated as 12 by this comparison, the decoding method is applied and two corrections are performed.

As described above, the decoding process information is passed from the first decoder to the second decoder and the decoding methods AXB and C are used separately to create ``processing with increased detection ability'' or ``processing with increased correction ability''.
By doing this, we aim to simplify the equipment and
In this case, in decoding method C, if the first decoder 21 performs the correction operation, the flag will not be turned on, so the second decoder 22 will not turn on the flag. , the correction operation is limited, and as a result, processing with improved detection ability is achieved.
In decoding method A, if the first decoder 2 performs a correction operation, the flag is turned on, so the second decoder 22 is less likely to perform a correction operation, and as a result, processing with improved correction ability is achieved. be done. Furthermore, decoding method B is decodability selection information e
If processing for two errors is performed by the first decoder 21 and the second decoder 22 based on the decoding method B selected by and , as is clear from the above explanation, the degree of decoding correction is This is approximately intermediate between decoding method A and decoding method C.

In this embodiment, the shortest distance is 5, and therefore the case where decoding methods A-, B, and C based on two error corrections are set has been described, but the present invention is not necessarily limited to this. It is also possible to set other shortest distances such as 3.7, . Further, the decoding method based on two-error correction is not limited to the decoding methods AXB and C shown in this embodiment, and a decoding method with different conditions may be set.

Furthermore, in this embodiment, a matrix-like table is assumed, and the first decoder 21 performs decoding correction in the vertical direction, and the second decoder 22 performs decoding correction in the horizontal direction, but the present invention is not necessarily limited to this. Alternatively, the decoding and correction processing may be performed with the vertical and horizontal directions reversed.

Effects of the Invention As explained in Section 2, the present invention selects a decoding method based on the decoding processing information generated by the first decoder, and performs decoding correction processing according to the selected decoding method, so that the circuit size can be reduced. If it is made larger, appropriate error correction ability and appropriate error detection ability are simultaneously provided, and decoding and correction processing can be performed appropriately depending on the coded data content.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a double error correction circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional double error correction circuit. 21...first decoder, 22...second decoder, 23.
5...Decoding circuit, 24.26...Correction circuit, a...
Encoded data, e: decoding processing information, f: decoding processing information.

Claims (1)

[Claims] a first decoder that decodes and corrects encoded data according to an arbitrary decoding method to generate a decoded correction signal, and outputs decoding processing information indicating an error detection status and its correction status and the decoded correction signal; and the decoding process. A double error correction circuit comprising: a second decoder that selects a decoding method based on the information and decodes and corrects the decoded correction signal according to the selected decoding method.