JPS63128648A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63128648A JPS63128648A JP61274763A JP27476386A JPS63128648A JP S63128648 A JPS63128648 A JP S63128648A JP 61274763 A JP61274763 A JP 61274763A JP 27476386 A JP27476386 A JP 27476386A JP S63128648 A JPS63128648 A JP S63128648A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- electrode
- film
- plating
- bonding property
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000007747 plating Methods 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract 2
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000002918 Fraxinus excelsior Nutrition 0.000 description 1
- 239000002956 ash Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バンプ電極を有しｔ半導体装置に関する。さ
らに言えば、バンプ電極形成用の下地膜として、メタル
ナイトライド膜、あるいはメタルシリサイド膜を、含ん
だ多層膜を用い、バンプメッキ電極と、ＡＬ配線との密
着性、耐熱性を大幅に改良し、且つ、従来より、合理化
し九プロセスでバンプ電極を形成した半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having bump electrodes. Furthermore, by using a multilayer film containing a metal nitride film or a metal silicide film as the base film for forming the bump electrode, the adhesion and heat resistance between the bump plating electrode and the AL wiring can be greatly improved. The present invention also relates to a semiconductor device in which bump electrodes are conventionally formed using nine streamlined processes.
従来のバンプ電極形成方法を第３〜５図に示した。バッ
トフォトエッチＭ、ｃｒｔｔと、Ａｕ１２′ｔ−スパッ
タで形成する１次に、１３のレジストでバンプ電極部を
保護し、その他の部分のＯｒとＡｕｔ−除去する。続い
て、０ｕ１４１スパツタで形成する。この時下地との密
着性金高める為同一チャンバーでスパッタエッチする。A conventional method for forming bump electrodes is shown in FIGS. 3 to 5. First, the bump electrode portion is protected by resist No. 13 formed by butt photoetch M, crtt and Au12't-sputtering, and Or and Out- from other parts are removed. Subsequently, it is formed using 0u141 sputtering. At this time, sputter etching is performed in the same chamber to increase the adhesion of the gold to the base.
次に、電極部のみメッキを形成する為、レジストマスク
１５でおおい、ｏｕ電極１６を形成する。Next, in order to plate only the electrode portion, it is covered with a resist mask 15 and an ou electrode 16 is formed.
さらに、Ｏｕ電極と同様に、Ｃａスパッタ膜１４をメッ
キ用電極としてハンダ電極１７を形成する。Furthermore, similarly to the Ou electrode, a solder electrode 17 is formed using the Ca sputtered film 14 as a plating electrode.
第５図は、レジスト１５を除去後、１６．１７のメッキ
電極なマスクとして、スパッタａｕｇ！ｔエツチングす
る。FIG. 5 shows that after removing the resist 15, the plating electrodes 16 and 17 are used as a mask for sputtering. T-etch.
この構造では、Ｏｒ、Ａｕ等のエツチング液では、Ｏｕ
やハンダ電極が、非常に早くエツチングされてしまう為
、前述の如く、電極部のみ先ずＯｒ、Ａｕを残すフォト
工程が必要になってしまう。さらに、１回目のＯｒ、Ａ
ｕのスパッタと、２回目のＯｕスパッタの間にｌノジス
ト処理の工程がある為、密着性が悪く、不安定であつ九
、又Ｃｒは、膜ストレスが大きい為、１５００Ａ以上つ
けれない為、ＡＬ配線と、Ａｕ 、Ｏｕとのパリマ性が
十分でなく、４００℃以上では、拡散灰石が進み、バン
プ強度が劣化するという欠点があつ九・
本発明は、従来のバンプ電極半導体装置にみられ几この
ような欠点を一掃し、シンプルで且つ、信頓性の高い半
導体装置ケ提供するｔのである。In this structure, in etching solutions such as Or and Au, Ou
Since the electrodes and solder electrodes are etched very quickly, a photo process is required to leave Or and Au only on the electrode portions, as described above. Furthermore, the first Or, A
Because there is a nozzle treatment process between the U sputtering and the second O sputtering, the adhesion is poor and unstable. There is a drawback that the polarity between the wiring and Au and O is not sufficient, and at temperatures above 400°C, diffusion of ashes progresses and the bump strength deteriorates. The aim is to eliminate these drawbacks and provide a simple and highly reliable semiconductor device.
パッシベーション膜のフォトエッチ後のバンプメッキ形
成用の電極膜として、少なくとも１層は、メタルナイト
ライド°膜、あるいはメタルシリサイド膜を有すること
ｔ−特徴とする・
〔実施例〕
本発明を実施例をもって説明していく、第１図。As an electrode film for forming bump plating after photo-etching the passivation film, at least one layer has a metal nitride film or a metal silicide film. Figure 1 explains this.
２図は本発明の一実施例の略図を示したものである０図
中１は８１基板、２は絶縁膜、３はＡＬ合金配線で入出
力バット部を示し比。Figure 2 shows a schematic diagram of an embodiment of the present invention. In Figure 1, 1 is an 81 substrate, 2 is an insulating film, and 3 is an AL alloy wiring, indicating the input/output butt part.
４のパッシベーション膜を、電極部のみ、エツチングし
た後、Ｔｉ５を５００Ａ％ ＴｉＮ６を０ 、 ′
１０００Ａスハツタで堆積する。次にメッキ用レジスト
７を用いて、８のＣｕｔ極を２０μ形成する。さらにハ
ンダ９全４０μメツキ形成シ、レジストアを除去後、８
．９の電極をマスクとして、下地５．６膜ｔエツチング
する。ＴｉＮ ／Ｔｉは、硫酸と過酸化水累の水浴液で
エツチング出来る為、ハンダメッキ電極をそこなわずに
、第２因の如く完成出来る。After etching only the electrode portion of the passivation film of No. 4, Ti5 is deposited at 500% and TiN6 is deposited at 0.5% and 1000% in a 1000A succession. Next, using the plating resist 7, cut electrodes 8 of 20 μm are formed. Furthermore, after forming a 40μ plating on all solder parts 9 and removing resistor,
．． Using the electrode No. 9 as a mask, the underlying film 5.6 is etched. Since TiN/Ti can be etched with a water bath containing sulfuric acid and peroxide, it can be completed without damaging the solder plating electrode as in the second case.
このようにＴ１は下地膜との密着性にすぐれ、ＴｉＮは
、非常に安定なバリアメタルであシ、導体である上、Ｔ
ｉＮ／Ｔｉは、応力も少ない。In this way, T1 has excellent adhesion with the underlying film, and TiN is a very stable barrier metal and conductor, and T1
iN/Ti also has less stress.
さらに、ＡＬ−Ｔｉ−ＴｉＮと殆ど、表面汚しのない状
態で形成出来るので各ノー藺の密着性が安定している。Furthermore, since it can be formed with AL-Ti-TiN with almost no surface stains, the adhesion of each layer is stable.
又上述の如く工程も約半分に省略出来、合理化と、高信
頼性が、同時に確立出来るものである。Furthermore, as mentioned above, the process can be cut in half, and rationalization and high reliability can be established at the same time.
さらに本発明では、ＴｉＮ／Ｔｉの例をとったが、Ｔｉ
５ｉｘ／Ｔｉ、Ｍｏ５ｉｘ／Ｍｏ、あるいは、ＴｉＨの
み、Ｍｏｅｉｚのみでも、同様の効果が得られるもので
ある。要は、従来のメタルのみの場合から、少なくとも
１層は、メタルナイトライド、又は、メタルシリサイド
°を用い几構造のバンプ電極半導体装［ｔｋ提出するも
のである。Further, in the present invention, an example of TiN/Ti is taken, but TiN/Ti is used as an example.
Similar effects can be obtained using 5ix/Ti, Mo5ix/Mo, TiH alone, or Moeiz alone. In short, from the conventional case of only metal, at least one layer is made of metal nitride or metal silicide, and a bump electrode semiconductor device with a solid structure is proposed.
又バンプｉｌＩ造としてこの他に金、銅のバンプ゛１極
にも適用出来るものである。In addition to the bump structure, it can also be applied to one pole of gold or copper bumps.
第１図、第２（８）は、本発明の実施例による半導体装
置の断面図。
第３図、第４１及び第５図は、従来技術の半導体装置の
断面図である。
１・・・８１基板
２・・・絶縁膜
３・・・ＡＬ合金配線
４・・・パッシベーション膜
５・・・Ｔ１膜
６・・・ＴｉＮ膜
７・・・レジスト（１）
８・・・Ｏｕメッキ電極
？・・・ハンダメッキ電極
１０・・・Ｔｉ１ｌＴｉ除去後
１１・・・Ｏｒ膜
１２・・・Ａｕ膜
１５・・・レジスト（１）
１４・・・Ｏｒ膜
１５・・・レジスト（２）
１６・・・Ｏｕメッキ電極
１７・・・ハンダメッキ電極
１８・・・Ｏｕエッチ後 以 出出願人
セイコーエプソン株式会社
代理人 弁理士 最上 務 他１名
＝７〕
（。1 and 2(8) are cross-sectional views of a semiconductor device according to an embodiment of the present invention. 3, 41, and 5 are cross-sectional views of conventional semiconductor devices. 1...81 Substrate 2...Insulating film 3...AL alloy wiring 4...Passivation film 5...T1 film 6...TiN film 7...Resist (1) 8...Ou Plated electrode? ...Solder plating electrode 10...After Ti1lTi removal 11...Or film 12...Au film 15...Resist (1) 14...Or film 15...Resist (2) 16...・Ou plating electrode 17...Solder plating electrode 18...After Ou etching Applicant: Seiko Epson Co., Ltd. Agent, Patent attorney Tsutomu Mogami and 1 other person = 7] (.
Claims (1)
おいて、パッシベーション膜のフォトエッチ後の、バン
プメッキ形成用の電極膜として、少なくとも１層は、メ
タルナイトライド膜、あるいは、メタルミクサイド膜を
有することを特徴とした半導体装置。In a semiconductor device equipped with a bump electrode of a semiconductor integrated circuit, at least one layer has a metal nitride film or a metal mixed film as an electrode film for forming bump plating after photo-etching a passivation film. Featured semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61274763A JPS63128648A (en) | 1986-11-18 | 1986-11-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61274763A JPS63128648A (en) | 1986-11-18 | 1986-11-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63128648A true JPS63128648A (en) | 1988-06-01 |
Family
ID=17546236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61274763A Pending JPS63128648A (en) | 1986-11-18 | 1986-11-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63128648A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238044A (en) * | 1988-03-17 | 1989-09-22 | Nec Corp | Semiconductor device |
| JPH0290622A (en) * | 1988-09-28 | 1990-03-30 | Seiko Instr Inc | Gold bump forming method |
| JPH02271635A (en) * | 1989-04-13 | 1990-11-06 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH07283225A (en) * | 1994-04-07 | 1995-10-27 | Nippondenso Co Ltd | Circuit board with bump electrode |
| EP1039530A2 (en) * | 1999-03-05 | 2000-09-27 | Nec Corporation | Method for manufacturing semiconductor device capable of avoiding flaws and erosion caused by metal chemical-mechanical polishing process |
| US6909191B2 (en) * | 2000-03-27 | 2005-06-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
1986
- 1986-11-18 JP JP61274763A patent/JPS63128648A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238044A (en) * | 1988-03-17 | 1989-09-22 | Nec Corp | Semiconductor device |
| JPH0290622A (en) * | 1988-09-28 | 1990-03-30 | Seiko Instr Inc | Gold bump forming method |
| JPH02271635A (en) * | 1989-04-13 | 1990-11-06 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH07283225A (en) * | 1994-04-07 | 1995-10-27 | Nippondenso Co Ltd | Circuit board with bump electrode |
| EP1039530A2 (en) * | 1999-03-05 | 2000-09-27 | Nec Corporation | Method for manufacturing semiconductor device capable of avoiding flaws and erosion caused by metal chemical-mechanical polishing process |
| EP1039530A3 (en) * | 1999-03-05 | 2000-10-25 | Nec Corporation | Method for manufacturing semiconductor device capable of avoiding flaws and erosion caused by metal chemical-mechanical polishing process |
| US6909191B2 (en) * | 2000-03-27 | 2005-06-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
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