JPS6310396A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the influence due to an inter-line capacity from a pair of adjacent bit lines and to attain a balanced state by alternately providing a pair of crossing bit lines and a pair of non-crossing bit line in case of a loop back bit line system. CONSTITUTION:The bit line B2 is adjacent to bit lines B1 and the inverse of B1 with half width, and the bit line, the inverse of B2 is also adjacent to the bit lines B3 and the inverse of B3 with half width. Consequently the force that the bit line, the inverse of B1 tries to maintain the bit line B2 at 'H' is halved than before. Force that the bit line B3 tries to drop the bit lines; the inverse of B2 to 'L' is also halved. Besides, the influence of the capacity between the bit lines B1 and the inverse of B1 on the bit line B2 and the influence of the capacity between the bit lines B3 and the inverse of B3 on the bit line; the inverse of B2 become completely the same. A pair of bit lines B2 and the inverse of B2 is completely balanced with respect to adjacent bit lines, and the margin of a sense action is improved.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a folded bit line type semiconductor memory device, and in particular, the present invention relates to a semiconductor memory device using a folded bit line method, and in particular, the invention relates to a semiconductor memory device using a folded bit line method. The present invention relates to a semiconductor memory device that prevents the operational margin of a circuit from decreasing due to generation of different noises.

<Prior Art> In a semiconductor memory device, a large number of memory cells are arranged in a matrix on the same semiconductor chip, and when a desired memory cell is selected by applying an address signal, information is written to that memory cell. or the stored information is read.

Figure 2 shows that in a folded bit line type DRAM,
This is the configuration of a bit line that is generally used such as the conventional bit line. A large number of bit line pairs CB +', B I'), CB
2', B2')-- are arranged parallel to each other.

ti, a large number of word lines Wl', W2', .
CII', MCI2', . . . are connected. Note that WS' is a word line selection circuit, SAI'.

SA2', . . . are sense amplifiers, BS' is a bit line selection circuit, and D' is data.

<Problems to be Solved by the Invention> A desired memory cell is selected from the above memory cell group and information is read or written therein. Consider the case of reading.First, word line W2'i is selected by word line selection circuit WS' and memory cells MC21', MC
22', MC2B'.

... information on bit lines Bl' and B2', respectively.

After reading to B3',..., the bit line selection circuit BS
Therefore, the bit lines B 2 and B 2 are selected to take out the information of the MC 22 to the outside. At this time, the information read out from the memory cell to the bit line is a very small signal, so before the bit line selection circuit BS' operates, one sensor is attached to each bit line pair.・Bit line B forming a bit line pair by an amplifier
It is necessary to amplify the minute voltages generated at i', Bi' (i=1.2...). However, during this sensing operation, a force acts to prevent a normal sensing operation due to stray capacitance between adjacent bit lines.

This principle will be explained in detail.

When reading the contents of the memory cell MC22' mentioned above, the initial state of the bit line is °l HH level, and the information of the memory cell is MC21' = "L", MC22' =
"L", MC28' - "L", the word line W2' is selected, and the information of the memory cell is transferred to the bit and node lines B1' and B2'.

B3', ... transmitted through Yuko, bit line Bl', B2〆.

BB' is the other bit line B l' forming the bit line pair.
, B2', and B3' are slightly lower in level.

In this state, the sense amplifier operates and amplifies the level difference that occurs between the bit lines forming the bit line pair, so that the bit lines B 1', B2', and B3' become IIL.
'' level, and the bit lines Bl', B2'.

B8' remains at the "t Hw level. However, at this time, the bit line i2' and the adjacent bit line Bl' remain at the "Hw level.
``level t'' is lowered to the tll-'' level due to the line capacitance, and the bit line B2' is pulled down to the tIL'' level by the bit line B8', so the bit line B2'.

A force that prevents normal sensing operation will act on B2', and even if it does not cause a direct malfunction to the sensing operation, it will reduce the sensing operation margin. In turn, this causes a reduction in the operating margin of the entire device.

In recent years, these have become a major problem in semiconductor integrated circuits, which are becoming increasingly finer.

The invention was devised to solve the above problems, and its purpose is to reduce and balance the influence of line capacitance from adjacent bit line pairs.

Means to solve problems〉 In order to achieve the above object, one aspect of the present invention is as follows.

A configuration is adopted in which intersecting bit line pairs and non-intersecting bit line pairs are provided alternately.

<Embodiment> FIG. 1 shows the configuration of a folded bit line type DRAM, which is a yet-to-be-invented embodiment. The features are the bit line pairs (Bl, Bl), [B3°B8), which intersect in the center, and the non-intersecting bit line pairs (B2, B21,...), which have the same configuration as the conventional one.
・The key point lies in the fact that they are all alternated. Note that %Wl, W2.
... is a word line, MCII.

MCI2, . . . are memory cells, and WS is a word line selection circuit-8A1. SA2. ...is a sense amplifier, B
S is a bit line selection circuit, and D is data.

Now, as in the prior art, memory cell MC21==
Considering the case of "L", MC22-"L", MC23-IIL", the bit lines Bl, B2, B4C3 change to "L" level.

B2. BB remains at I'H''H'. However, in the 73-1 degree uninvention, bit line B2 is adjacent to bit lines Bl and Bl by half the length of each, and bit line B2 is also bit line B1. This was a problem in the prior art because the lines B8 and B3 are adjacent to each other by half their respective lengths.The force with which the bit line B2 is held back by the bit line Bl from H' is half that of the prior art. , and the force of the bit line τ lower being pulled to L' by the bit line B3 is also halved.

Moreover, the bit line Bl for the bit line B2.

The influence of the line capacitance of positive 1 and the influence of the line capacitance of the bit lines B8 and B8 on the bit line W1 are completely equal, and the influence of the line capacitance of the bit line pair B2 . B2 has a completely balanced configuration with respect to the adjacent bit line numbers, and the margin for sensing operation is wide.

The above was about reading from non-crossing bit line pairs, but also when reading from crossing bit line pairs,
Structure: The influence of line tolerance on each bit line from the adjacent bit line [c1] is completely equal, resulting in a well-balanced structure.

In the above embodiment, bit line pairs crossed once in the center and non-crossing bit line pairs are provided alternately. As described above in detail, according to the present invention, the influence from adjacent bit line pairs can be reduced and balanced, and the operating margin of the circuit can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention, and FIG. 2 is a block diagram of a conventional semiconductor memory device. Explanation of symbols Bl, Bl,...: Bit line, Wl, W2,
... word line, MCII, MCI2. ...: Memory cell. WS: word line selection circuit, SAI, SA2. ...：
Sense amplifier, BS: Bit line selection circuit, D: Data.

Claims (1)

[Claims] 1. A semiconductor memory device of a folded bit line type, characterized in that crossed bit line pairs and non-crossed bit line pairs are provided alternately.