JPS63106898A

JPS63106898A - Receiver

Info

Publication number: JPS63106898A
Application number: JP24776287A
Authority: JP
Inventors: デビッド・ディラタッシュ; スティーブン・エム・オクセルバーグ
Original assignee: Honeywell Inc
Current assignee: Honeywell Inc
Priority date: 1986-10-01
Filing date: 1987-09-30
Publication date: 1988-05-11
Also published as: EP0262659A3; EP0262659A2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】［産業上の利用分野］本発明は、工業計測等において、２線式伝送路を介して
各種計測値の受信を行なう場合に適用される受信器に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiver that is applied to receive various measured values via a two-wire transmission line in industrial measurement and the like.

［従来の技術１従来、工業計測においては、差圧発信器、電磁流量計等
の計測出力を遠隔地点へ伝送する場合、−最に４〜２０
ｍ八等の統一信号が用いられており、このアナログ信号
の電流値により計測値を示すものとなっている。[Conventional technology 1] Conventionally, in industrial measurement, when transmitting the measurement output of a differential pressure transmitter, electromagnetic flow meter, etc. to a remote point,
A unified signal such as m8 is used, and the measured value is indicated by the current value of this analog signal.

また、アナログ信号を用いずディジタル信号により計測
値の伝送を行なうものもあり、米国特許第４，５２０，
４８８号により開示されており、近来の傾向としては、
ディジタル信号を用いれば伝送情報量および内容の信頬
性等が向上するため、ディジタル信号を用いる場合が増
大している。There are also devices that transmit measured values using digital signals without using analog signals, such as U.S. Patent No. 4,520,
No. 488, and recent trends include:
The use of digital signals improves the amount of information transmitted and the credibility of the content, so the use of digital signals is increasing.

［発明が解決しようとする問題点］し２かし、伝送路の直流的な電位は、伝送路へ電流を通
じ、あるいは、信号を送信する条（ｌ目こ応して異なり
、伝送路吉受信器吉を接続する際、両者間の電位関係を
その都度適合させねばならず１、ごれにしたがって受信
器を製造するご、とを要すると共に、アナログ信−号用
とディジタル信Σ用とを各個Ｇこ用意し、信号の形態に
応じて用いねばならず、受信器の共用化が不可能であり
、これの共用化および量産化による低価格化が阻害され
る問題を生じている。[Problems to be Solved by the Invention] However, the direct current potential of a transmission line is a condition that allows current to pass through the transmission line or transmits a signal. When connecting the receivers, it is necessary to adapt the potential relationship between the two each time1, and it is necessary to manufacture the receiver according to the requirements. G receivers must be prepared for each type and used according to the signal format, making it impossible to share the receiver, which poses a problem that prevents sharing and lowering costs through mass production.

したがって、本発明は、伝送路側の直流電位と受信器側
の直流電位との関係が不特定であっても使用できる受信
器の提供を第１の目的とするものである。Therefore, a first object of the present invention is to provide a receiver that can be used even if the relationship between the DC potential on the transmission line side and the DC potential on the receiver side is unspecified.

また、ディジタル信号を用いる場合、これの波高値と無
関係に受信を行なえる受信器の提供を第２の目的とする
ものである。A second object of the present invention is to provide a receiver that can receive digital signals regardless of their peak values.

更に、信号形態がアナログ信号、ディジタル信号のいず
れであっても適用できる受信器の提供を第３の目的とす
るものである。Furthermore, a third object of the present invention is to provide a receiver that can be applied regardless of whether the signal format is an analog signal or a digital signal.

［問題点を解決するだめの手段］前述の問題を解決するため、本発明（７才つぎの手段に
より構成するものとなっている。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention (7 years old) is constructed by the following means.

すなわち、第１発明は、２線式伝送路により伝送される
計測値を示す信号の受信を行なう２１ｉ１式受信器にお
いて、基準電圧と受信々号吉を比較し基準電圧以上の成
分を抽出してパルス信号とする比較器と、この比較器の
入力出伝送路きの間へ直列に挿入され受信々号の交流成
分のめを通過させるコンデンサさを設８）だものである
。That is, the first invention is a 21i1 type receiver that receives a signal indicating a measured value transmitted through a two-wire transmission line, which compares a reference voltage with a received signal and extracts components that are higher than the reference voltage. A comparator for generating pulse signals and a capacitor inserted in series between the input and output transmission lines of this comparator to pass the alternating current components of the received signals are provided (8).

また、第２発明は、第１発明に加え、受信々号をディジ
タル信号へ変換するアナ１′□ｊグ・ディジタル変換器
を設し」たものである。In addition to the first invention, the second invention further includes an analog-to-digital converter for converting the received signal into a digital signal.

〔作　用１したがって、比ＩＨの入力と伝送路との間へ挿入された
コンデンサにより、直流分が阻止され、両者間の直流電
位関係が無関係になると共に、受信々号の交流分抽出に
より受信々号の波高値にか＼わらず受信が可能となり、
更に、第２発明によれば、アナログ信号はアナログ・デ
ィジタル変換器によりディジタル信号となり、ディジタ
ル信号は比較器により抽出され、いずれも受信できるも
のとなり、受信器の共用化による形式統一が可能となる
。[Effect 1 Therefore, the DC component is blocked by the capacitor inserted between the input of the ratio IH and the transmission line, and the DC potential relationship between the two becomes irrelevant, and the AC component of each received signal is extracted. Reception is possible regardless of the wave height of the wave,
Furthermore, according to the second invention, an analog signal is converted into a digital signal by an analog-to-digital converter, and the digital signal is extracted by a comparator, and both can be received, making it possible to unify the format by sharing receivers. .

［実施例］以下、実施例を示す図によって本発明の詳細な説明する
。[Example] Hereinafter, the present invention will be described in detail with reference to figures showing examples.

第１図は、全構成のブロック図であり、線路１、．１２
からなる２線式伝送路（以下、伝送路）ムこ対し電流を
供給する電源部（以下、ＰＳ）２が設けられていると共
に、伝送路の他端には、差圧発信器、電磁流量計等の発
信器Ｃ以下、ＴＸ）、３が接続されており、ＴＸ３が電
流値Ｉを制御し、アナログ信号またはパルス状のディジ
タル信号古して伝送路へ通じ、これによって計測値を示
すものとなっている。FIG. 1 is a block diagram of the entire configuration, showing lines 1, . 12
A power supply section (hereinafter referred to as PS) 2 that supplies current to a two-wire transmission line (hereinafter referred to as transmission line) is provided at the other end of the transmission line, and a differential pressure transmitter, an electromagnetic flow rate A transmitter (C below, TX), 3 such as a meter is connected, and TX3 controls the current value I, and transmits an analog signal or pulsed digital signal to the transmission path, thereby indicating the measured value. It becomes.

また、伝送路中には、電圧腎下素子として抵抗器ＲＬが
直列に挿入されており、抵抗器Ｒｔの端子電圧を受信々
号として受信器（以下、ＲＸ）４へ与え、ＲＸ４におい
て受信を行なうものとし、受信出力を母線５を介してホ
ストコンビエータ等の主制御部（以下、ＭＣ）６へ更に
与えており、こ（において、ＲＸ４から与えられた工４
測値に基づく制御演算を行ない、母線５を介し図上省略
した制御対象機器へ制御データを送出し、これの制御を
行なうものとなっている。In addition, a resistor RL is inserted in series in the transmission path as a voltage infrared element, and the terminal voltage of the resistor Rt is applied as a reception signal to the receiver (hereinafter referred to as RX) 4, and the reception is performed at RX4. The reception output is further given to a main control unit (hereinafter referred to as MC) 6 such as a host combinator via a bus 5, and in this (here, the work 4 given from RX4 is
Control calculations are performed based on the measured values, and control data is sent to the controlled equipment (not shown in the figure) via the bus 5 to control the equipment.

なお、母線６には、ブラウン管表示器およびキーボード
等を備えた操作部（以下、０Ｐ）７が接続されており、
これによって制御状況の表示を行なうと共に、ＭＣ６お
よびＲＸ４に対する指令を与えることが自在となってい
る。Note that an operation unit (hereinafter referred to as 0P) 7 equipped with a cathode ray tube display, a keyboard, etc. is connected to the bus bar 6.
This allows the control status to be displayed and commands to be given to the MC6 and RX4.

一方、抵抗器ＲＬよりもＴＸ３例の伝送路には、通信器
（以下、ＣＥ）８が橋絡接続されており、これがＴＸ３
において受信され、受信に応じてＴＸ３が電流値■を同
様に変化させ、ディジタル信号の応答信号としてＣＥ８
へ送信するため、これがＣＥ８において受信されるもの
となっている。On the other hand, a communication device (hereinafter referred to as CE) 8 is bridge-connected to the transmission line of the TX3 example from the resistor RL, and this is connected to the transmission path of the TX3 example.
, TX3 similarly changes the current value ■ in response to the reception, and CE8 as a response signal of the digital signal.
This is to be received at CE8.

したがって、ＣＥ８からの送信により、ＴＸ３の計測状
況変更等が行なえると共に、ＣＩ”、　８とＴＸ３との
間の信号送受信により、ＴＸ３の動作状況ヂエソク等が
なされ、これらの状況がＣＥ８において表示されるもの
となる。Therefore, the measurement status of TX3 can be changed by transmission from CE8, and the operating status of TX3 can be checked by transmitting and receiving signals between CI'', 8 and TX3, and these statuses are displayed on CE8. become something that

第２図は、ＲＸ４のブロック図であり、マイクロプロセ
ッサ等のプロセッサ（以下、ＣＰＵ）７１、固定メモリ
　（以下、ＲＯＭ）７２、可変メモリ　（以下、ＲＡＭ
）７３およびインターフェイス（以下、Ｉ／Ｆ）７４．
７５を母線７６により接続し、ＣＰＵ７１がＲＯＭ７２
中の命令を実行すると共に、必要とするデータをＲＡＭ
７３ヘアクセスしながら受信との制御を行なうものとな
っており、Ｉ／Ｆ７４には、複数の伝送路からの入力Ｉ
Ｎ、〜■Ｎｎが与えられ、これらからの電流値変化に基
づく受信々号を順次にかつ反復して受入れ、これを一旦
ＲＡＭ７３へ格納し、ＣＰＵ７１が計測値への変換を行
なってからＴ／Ｆ７５を介してＭＣ６およびＯＦ２へ送
出すると共に、１／Ｆ７５を介するＭＣ６またはＯＦ２
からの指令に応じてＣＰＵ７１が指令内容および変換演
算上の各種データをＲＡＭ７３へ格納し、これらにした
がって受信々号の変換を行なうものとなっている。FIG. 2 is a block diagram of the RX4, which includes a processor such as a microprocessor (hereinafter referred to as CPU) 71, a fixed memory (hereinafter referred to as ROM) 72, and a variable memory (hereinafter referred to as RAM).
) 73 and interface (hereinafter referred to as I/F) 74.
75 is connected to the bus bar 76, and the CPU 71 connects to the ROM 72.
In addition to executing the instructions inside, the necessary data is stored in RAM.
The I/F 74 receives input I/F from multiple transmission lines.
N, ~■Nn are given, and received signals based on current value changes are sequentially and repeatedly accepted, temporarily stored in the RAM 73, and after the CPU 71 converts them into measured values, the T/ Send to MC6 and OF2 via F75, and send to MC6 or OF2 via 1/F75
In response to a command from the CPU 71, the contents of the command and various data for conversion calculations are stored in the RAM 73, and the received signals are converted in accordance with these.

第３図は、Ｔ／Ｆ７４の回路図であり、各々が線路１＋
＋、１□１．〜１１．ｌ＋１２１１からなる複数の伝送
路へ各個に挿入された抵抗器ＲＬ１〜ＲＬｎの端子電圧
が入力端子Ｉ　Ｎ−＋　、Ｉ　Ｎｂ＋〜Ｔ　Ｎ、ｌｌ、
　Ｉ　ＮｂＩ。Figure 3 is a circuit diagram of T/F74, each line 1+
+, 1□1. ~11. The terminal voltages of the resistors RL1 to RLn each inserted into a plurality of transmission lines consisting of 1211 are input terminals I N-+, I Nb+ to T N, ll,
I NbI.

へ与えられており、入力端子Ｉ　Ｎ、Ｉ〜ＴＮ□は、直
列に挿入された抵抗器Ｒ０〜Ｒ１ｎおよびコンデンサＣ
１１〜ＣＩ、、を介し、比較器（以下、ｃｐ）８１、〜
８１．．の反転入力へ接続され、これらの各入力と共通
回路との間には、コンデンサＣＺＩ〜Ｃ２１，および抵
抗器ＲＺＩ−Ｒ２ｎが接続されていると共に、各反転入
力と電源■、との間には、入力端子が過大となったとき
、この点の電位を電源■。The input terminals IN, I~TN□ are connected to resistors R0~R1n and capacitor C inserted in series.
Comparators (hereinafter referred to as cp) 81, through CI, 11 to
81. ．． Capacitors CZI-C21 and resistors RZI-R2n are connected between each of these inputs and the common circuit, and between each inverting input and the power supply , when the input terminal becomes excessively high, the potential at this point becomes the power supply ■.

の電圧ヘクランプするダイオードＤ、〜Ｄ３．．が接続
されている。diodes D, ~D3. ．． is connected.

したがって、抵抗器Ｒ１１〜Ｒ１ｎ、コンデンサＣＨＩ
〜Ｃ２□および抵抗器Ｒｔ　Ｉ　””　Ｒ２ｎにより雑
音除去用の低域濾波器を構成していると共に、コンデン
サＣ１ｌ〜ｃａｆｉは受信々号の交流成分のみを通過さ
せ、直流分を阻止しており、ＰＳ２＋〜ＰＳ２．。Therefore, resistors R11 to R1n, capacitor CHI
~C2□ and resistor Rt I ``'' R2n constitute a low-pass filter for noise removal, and capacitors C1l~cafi allow only the AC component of the received signal to pass through and block the DC component. , PS2+ to PS2. .

により伝送路へ通ずる電流値の変化に基づく抵抗器ＲＬ
Ｉ〜Ｒｔ□の端子電圧変化は、雑音成分が除去されたう
え、交流分のみがＣＰ８１＋　〜ＣＰ８１．。Resistor RL based on the change in the current value flowing to the transmission line due to
As for the terminal voltage changes of I to Rt□, the noise component is removed and only the alternating current component is changed from CP81+ to CP81. .

の反転入力へ与えられる。is applied to the inverting input of

また、ＣＰ８１＋　〜８１゜の非反転入力には、抵抗器
Ｒ３１〜Ｒ３ゎを介し基準電圧ＥＳが印加されていると
共に、出力との間に正帰還用の抵抗器Ｒ４１〜Ｒ４，、
が接続されており、これによって比較動作にヒステリシ
ス特性を与えるものとなっている。In addition, a reference voltage ES is applied to the non-inverting input of CP81+~81° via resistors R31~R3ゎ, and positive feedback resistors R41~R4,...
are connected, thereby giving a hysteresis characteristic to the comparison operation.

したがって、各伝送路へ通ずる電流がパルスコードによ
るディジタル信号であれば、これの交流分のみがＣＰ８
１＋〜ＣＰ８１１１において基準電圧Ｅｓと比較され、
同電圧Ｅｓ以上の成分がパルス信号として抽出され、シ
フトレジスタ等の直並列変換器（以下、５ＰＣ）８２＋
〜８２、へ順次に蓄積された後、並列ビットのディジタ
ル信号として母線７６を介しＣＰＵ７１へ送出される。Therefore, if the current flowing to each transmission path is a digital signal based on a pulse code, only the alternating current component of this is CP8.
1+~CP8111 is compared with the reference voltage Es,
Components higher than the same voltage Es are extracted as pulse signals, and a serial-to-parallel converter (hereinafter referred to as 5PC) 82+ such as a shift register
.about.82, and then sent to the CPU 71 via the bus 76 as a parallel bit digital signal.

なお、ＰＳ２＋　〜ＰＳ２１１の電圧に応じて入力端子
ＩＮ、Ｉ−ＩＮ□の電位が異なり、あるいは、各伝送路
へ通ずる電流値のパルス状変化が例えば４〜２０−１ま
たは、これ以外であれば、これらの波高値も異なるもの
となり、伝送路の条件および受信々号の状況に応じて基
１“電圧Ｅ　ｓを最適に設定しなければ、パルス信すの
抽出状況が不正確となり、受信−［に誤りを生ずるもの
となるが、コンデンサＣ＋　＋　−Ｃ＋　ｎによる交流
骨のみの通過許容により１．基準電圧Ｅｓを一定として
も支障なくパルス信号の抽出を行な・うことができる。In addition, if the potential of the input terminals IN and I-IN□ differs depending on the voltage of PS2+ to PS211, or if the pulse-like change in the current value flowing to each transmission path is, for example, 4 to 20-1 or other than this, , these peak values will also be different, and unless the basic voltage E s is set optimally according to the conditions of the transmission path and the status of the received signal, the extraction status of the pulse signal will be inaccurate, and the reception signal will be incorrect. [Although an error will occur, the capacitor C+ + -C+ n allows only the AC bone to pass through. 1. Even if the reference voltage Es is kept constant, the pulse signal can be extracted without any problem.

−・方、入力端子Ｉ　Ｎ、、　、　Ｉ　Ｎ、、〜ｒ　Ｎ
、、１．　Ｉ　Ｎｂ、。-・Input terminal I N, , I N,, ~r N
,,1. I Nb,.

には、抵抗器Ｒ５１〜Ｒｓｎ　＋Ｒｈ、〜Ｒｂｎおよび
コンデンサＣ３ｌ−Ｃ３１１，Ｃａｌ−Ｃａ、ｌによる
微少変化および雑音除去用の低域濾波器を介し、マルチ
プレクサ（以下、ＭＰＸ）８３の各入力が接続されてお
り、ＣＰＵ７１の制御に応じてＭＰＸ８３が各入力を順
次にかつ反復して選択し、これの出力をアナログ・ディ
ジタル変換器（以下、Ａ　Ｉ）　Ｃ）８４へ与え、受信
々号がアナログ信号であれば、これをＡＤＣ８４ｂこお
いてディジタル信号−・変換の後、母線７６を介しＣＰ
Ｕ７１へ送出するものとなっている。The inputs of the multiplexer (hereinafter referred to as MPX) 83 are connected to the resistors R51 to Rsn +Rh, ~Rbn and the capacitors C3l-C311, Cal-Ca, and a low-pass filter for removing noise and minute changes. Under the control of the CPU 71, the MPX 83 sequentially and repeatedly selects each input and supplies the output to an analog-to-digital converter (hereinafter referred to as AI) 84, so that the received signals are analog If it is a signal, it is converted into a digital signal by the ADC 84b, and then sent to the CP via the bus 76.
It is to be sent to U71.

したがって、ＣＰＵ７１は、例えば最初に５ＰＣ８２，
〜５ＰＣ８２ｎの出力を取込の、これの解読を行ない、
これによって計測値が得られ−ば、以降５ＰＣＢ２１〜
５ＰＣ８２ｎの出力を用いて受信処理を行なうものとし
、計測値が得られなければ、ＭＰＸ８３の制御およびＡ
ＤＣ８４の出力取込みを行ない、これにより計測値が得
られることを確認のうえ、以降はＡＤＣ８４の出力を用
いて受信処理を行な・うことにより、相手側のＴＸ３が
アナログ信号、ディジタル信号のいずれを送信するもの
であっても、正常に受信を行なうことができる。Therefore, for example, the CPU 71 first uses the 5PC82,
~ 5PC82n output is taken in and decoded,
If the measured value is obtained by this, then 5PCB21~
Reception processing shall be performed using the output of 5PC82n, and if no measured value is obtained, control of MPX83 and A
After capturing the output of the DC84 and confirming that a measured value can be obtained, from then on, the output of the ADC84 is used for reception processing to determine whether the TX3 on the other side is receiving an analog signal or a digital signal. Even if a message is sent, it can be received normally.

なお、相手側の１゛Ｘ３がアナログ信号の送信を行なう
ものと、ディジタル信号の送信を行なうものとの混在す
る場合には、これに応じて５ＰＣ８２１−３ＰＣＢ２、
中の対応する出力、および、対応する入力をＭＰＸ８３
が選択したときのＡＩ）（１４の出力を交互に用いるも
のとすればよい。In addition, if there is a mixture of 1゛X3 on the other side that transmits analog signals and those that transmit digital signals, 5PC821-3PCB2,
The corresponding output and the corresponding input in MPX83
AI when selected) (14 outputs may be used alternately.

たりし、接続する伝送路数は１回路でもよく、この場合
にはＭＰＸ８３を省略することができると共に、５ＰＣ
８２１−３ＰＣＢ２、およびＡＤＣ８４の出力側へ母線
７６との入出力回路等を挿入してもよく、基準電圧Ｅｓ
としては、電圧安定化回路の出力等を用い、または、定
電圧ダイオード等の定電圧素子により安定した電圧を用
いても同様である等、様々の変形が自在である。However, the number of transmission lines to be connected may be one circuit. In this case, MPX83 can be omitted and 5 PCs can be connected.
An input/output circuit with the bus 76 may be inserted into the output side of the 821-3 PCB2 and ADC84, and the reference voltage Es
Various modifications are possible, such as using the output of a voltage stabilizing circuit or using a voltage stabilized by a constant voltage element such as a constant voltage diode.

［発明の効果］以−にの説明により明らかなとおり本発明によれば、接
続される伝送路の直流電位、および、受信々号の波高値
にか−わらずディジクル信号の受信を正常に行なえると
共に、アナログ信号、ディジタル信号のいずれにも適合
できるものとなり、各種条件に対する共用化が実現し、
各種計測信号の受信において顕著な効果が得られる。[Effects of the Invention] As is clear from the above description, according to the present invention, digital signals can be normally received regardless of the DC potential of the connected transmission line and the peak value of the received signals. At the same time, it is compatible with both analog and digital signals, realizing common use for various conditions.
Remarkable effects can be obtained in receiving various measurement signals.

[Brief explanation of the drawing]

図は本発明の実施例を示し、第１図はインターフェイス
の回路図、第２図は全構成を示すブロック図、第３図は
受信器のブロック図である。１□１□＋１１１＋　　１ｚ＋＋〜１１ｎ＋　　１　ｔ
ｎ・・・線路２．２Ｉ〜２７・・・ＰＳ（電源部）３・・・ＴＸ（発信器）４・・・ＲＸ（受信器）７１・・・ＣＰＵ　（プロセッサ）７２・・・ＲＯＭ　（固定メモリ）７３・・・ＲＡＭ（可変メモリ）７４．７５・・弓／Ｆ（インターフェイス）８１、〜８
１．ｌ・・・ＣＰ（比較器）８４・・・ＡＤＣ（アナロ
グ・ディジタル変換器）ＣＩｌ〜Ｃ１・・・コンデンサＲｔ　、　Ｒｔ＋−Ｒｔｎ・・・抵抗器。The figures show an embodiment of the present invention; FIG. 1 is a circuit diagram of an interface, FIG. 2 is a block diagram showing the entire configuration, and FIG. 3 is a block diagram of a receiver. 1□1□+111+ 1z++~11n+ 1 t
n...Line 2.2I~27...PS (power supply part) 3...TX (transmitter) 4...RX (receiver) 71...CPU (processor) 72...ROM ( Fixed memory) 73...RAM (variable memory) 74.75...Bow/F (interface) 81,~8
1. l...CP (comparator) 84...ADC (analog/digital converter) CIl-C1...capacitor Rt, Rt+-Rtn...resistor.

Claims

[Claims]

(1) In a receiver that receives a signal indicating a measured value transmitted through a two-wire transmission line, a reference voltage is compared with a received signal, and a component higher than the reference voltage is extracted and made into a pulse signal. and a capacitor inserted in series between the input of the comparator and the transmission line to pass only the alternating current component of the received signals.

(2) The receiver according to claim 1, characterized in that a digital signal based on a change in current value passing through a two-wire transmission line is used as a reception signal.

(3) The receiver according to claim 1, characterized in that the terminal voltage change of a voltage drop element inserted in series in the two-wire transmission line is used as the reception signal.

(4) In a receiver that receives a signal indicating a measured value transmitted through a two-wire transmission line, a comparison is made in which a reference voltage and a received signal are compared, and components higher than the reference voltage are extracted and made into a pulse signal. a capacitor inserted in series between the input of the comparator and the transmission line and passing only the alternating current component of the received signal; and an analog-to-digital converter that converts the received signal into a digital signal. A receiver characterized by being provided with.

(5) The receiver according to claim 4, wherein a digital signal based on a change in the value of current flowing through the two-wire transmission line is used as the received signal.

(6) The receiver according to claim 4, characterized in that an analog signal based on a change in current value passing through a two-wire transmission line is used as a reception signal.

(7) The receiver according to claim 4, characterized in that the terminal voltage change of a voltage drop element inserted in series in the two-wire transmission line is used as the reception signal.