JPS6264176A - Fade circuit for video signal - Google Patents

Abstract

PURPOSE:To provide the white fade function to the titled circuit consisting of an IC having the black fade function by adding a simple circuitry. CONSTITUTION:A voltage of a setup level Ls1 approximately equal to the white level Lw of a video level is maintained for a duration from time T1 to time T2. During the said time duration, the gain of a level control circuit 20 is controlled to the minimum. The setup level being to be lowered at the time T2. At the time when the said level goes to 2/3 of the voltage of the setup level Ls1 approximately equal to the white level Lw of the video level i.e. T3, a level controlling signal S1 begins to be lowered. And, the gain of the circuit 20 is controlled to increase. Consequently, the white-fade operation is executed to obtain a normal video output signal V.OUT at time T4.

Description

[Detailed Description of the Invention] C. Industrial Application Field] The present invention relates to a video signal fade circuit, and more particularly, to a video signal fade circuit that has both a black fader function and a white fader function. be.

C. Conventional technology] TV left cameras with a fade function are commonly used, and these fade functions include a black fade function and a white fade function, each of which has a series of fade-in and fade-out functions. .

First, details of the black fade function will be explained using FIG. 10. In other words, black fade-in means that the image is brought to a set-up level Ls that is 0.07 V (P - P) higher than the bedscale level Lp of the video signal having the horizontal synchronizing signal H, as shown in FIG. 10(A). The so-called black screen where the component is located is gradually transferred to a regular screen having regular video components as shown in FIG. 10(B). Further, black fade-out is the opposite of the above-mentioned black fade-in, and is a gradual transition from the regular screen in the state shown in FIG. 10(B) to the black screen in the state shown in FIG. 10(A). .

Next, the white fade function will be explained using FIG. 11. In other words, white fade-in means that the video component is located at a white level Lw that is 0.7 V (P-P) higher than the pedestal level Lp of the video signal having the horizontal synchronizing signal H, as shown in FIG. 11(A). , the so-called white screen gradually,
The screen is moved to a regular screen having regular video components as shown in FIG. 11(B). Also, the white fade-out is the opposite of the white fade-in described above.
) The normal screen in the state shown in FIG. 11(A) is gradually transitioned to the white screen in the state shown in FIG. 11(A).

To perform the black fade function, the image component of the video signal may be gradually increased during black fade-in, and the image component of the video signal may be gradually attenuated during black fade-out.

In order to achieve the - black fade function, the video component signal of the video signal is gain controlled using a gain control type amplifier circuit such as a voltage control amplifier to correspond to the fade operation. .

On the other hand, in order to achieve the white fade function, it is not sufficient to perform gain control on the image component signal of the video signal in response to the fade operation, as in the case of the black fade function. This is because when the signal level of the video component of a video signal is increased, the entire image becomes whitish, but the component in the direction of the white peak of the normal video component is superimposed, causing a white fade-in or white fade-out. The image when completed becomes unsightly.

For this reason, at the time of white fade-out, the setup level of the video signal is gradually increased, and the signal of the image component of the video signal is gradually attenuated. Furthermore, at the time of white fade-in, the setup level of the video signal is gradually lowered, and the signal of the video component of the video signal is gradually increased to become a regular video component.

Increasingly, TV left cameras are equipped with such a fade function. In addition, in order to make the TV right camera body smaller and lighter, video signal processing circuits having these fade functions are now integrated into ICs and mounted on the TV right camera body.

[Problems to be Solved by the Invention] However, when implementing a video signal processing circuit into an IC, only one of an IC having a black fade function and an IC having a white fade function exists. Although it is possible to manufacture an IC having both fade functions, the circuit scale becomes larger, which requires larger manufacturing equipment, lowers the yield, and increases costs. Additionally, the current trend is to provide either a white fade or a black fade for the fade function in the TV left camera, so it is not recommended to increase the number of units manufactured, which significantly affects the cost of the IC. This is not practical as it would lead to an increase in costs.

The present invention was made in view of these circumstances, and its purpose is to make it possible to have a white fade function by simply adding a simple circuit configuration when configured using an IC having a black fade function. The object of the present invention is to provide a video signal fade circuit.

Means and operation for solving problem E] The present invention includes:
In order to achieve the above object, as shown in FIG. 1, a level control circuit 20 is provided to control the amplitude of the output signal of the imaging means 10, and the output of this level control circuit 20 is separated into a color signal and a luminance signal. a video signal processing circuit 30 that performs predetermined signal processing;
A set-up control circuit 40 controls the set-up level given to the video signal processed by the set-up control circuit 40. The mixer circuit 50 which adds the above-mentioned level control circuit 20 and the setup control circuit 40 respectively have both circuits 20. The device is characterized in that it includes a control signal generation circuit 60 that provides a control signal for controlling the operation of the '40.

[Example] Examples of the present invention will be described below with reference to FIGS. 2 to 9. In FIG. 2, the imaging means 10 is a well-known circuit that produces a desired output signal from an image of a subject. A subject image obtained by a photographing lens 11 forming this imaging means 10 is photoelectrically converted by an image sensor 12 such as a CCD or an image pickup tube, and then preamplified by a preamplifier 13, and a clamp circuit 14 adjusts the optical black level. Fixed. The output of the clamp circuit 14 is corrected for dark shading caused by the state of the light source in a dark shading correction circuit 15. The output of the dark shading correction circuit 15 is subjected to γ correction by a γ correction circuit 16 in order to make the gradation of the image appropriate.

The output signal S of this γ correction circuit 16 becomes the output of the imaging means 10.

The output signal S of the imaging means 10 obtained in this way is
The signal is supplied to the video signal processing circuit 30 via the level control circuit 20. This level control circuit 20
The gain of the amplifier circuit is variably controlled in accordance with the fade operation, and in this embodiment, the voltage control amplifier (hereinafter abbreviated as rVCAJ) 2
1 and a control circuit 22 that supplies a control signal Sl- to this VCA 21. The output signal S of the level control circuit 20 is transmitted to the video signal processing circuit 3.
0, and this output signal S'' is supplied to a De/γ correction signal generation circuit 31 forming the same circuit 30, an HPF (bypass filter) 32 for extracting the color signal component, and an LPF (bypass filter) for extracting the luminance signal component. low pass filter) 39.

Then, the video signal component of the output signal S' is extracted by the LPF 39, and the luminance signal Y is sent to the mixer circuit 50 at the next stage of the video signal processing circuit 30.

On the other hand, the output signal S' of the level control circuit 20 is
Color signal components are extracted by HPF32, and R/B components! De/
In the γ correction circuit 33, the above-mentioned De/γ correction signal generation circuit 3
De/γ correction is performed based on various correction control signals generated in step 1, and R and B signals of color signal components are separated and extracted.

The R signal generated in this way is transmitted to the matrix circuit 3.
4 into a (RY) signal, and this (RY)
The signal is converted by modulator 35 to (R-Y)SC: (R
-Y) Quadrature modulated based on the subcarrier signal. Further, the B signal generated as described above is converted into a (B-Y) signal by the matrix circuit 36, and this (B-Y) signal is converted into a (B-Y) signal by the matrix circuit 36.
-Y) signal is transmitted (B-Y)sc by modulator 37;
(B-Y) Quadrature modulated based on the subcarrier signal.

The outputs of the modulators 35 and 37 are combined by a mixer 38 and supplied as a color signal C to a mixer circuit 50 at the next stage. The mixer circuit 50 is also supplied with various horizontal and vertical synchronization signals 5YNC and color burst signals CB.

Further, the mixer circuit 50 is supplied with a set-up control signal S2- for controlling the set-up level of the luminance signal Y described above in accordance with the fade operation. The setup control signal S2- is generated by the setup control circuit 40 based on the setup command signal S2 generated by the control signal generation circuit 60.

Further, the level control signal Sl- supplied to the VCA 21 described above is also generated by the control circuit z2 based on the level control command signal S1 generated by the control signal generation circuit 60.

Next, details of the above-mentioned control circuit 22 will be explained using FIG. 3. That is, the control circuit 22 receives the control signals Fl, F3 . F
The level control signal SL- is generated based on the level control command signal S1 consisting of 4. Grounded. Further, the input terminal of the control signal F3 is connected to the base of the transristor Q1 via a resistor R2. Furthermore, the input terminal of the control signal F4 is connected via the inverter G1 and the diode 1 to the connection point of the resistors R2 and R3.

Further, the input terminal of the operating voltage Vcc is grounded via a variable resistor R7 and a resistor R6. The connection point between the variable resistor R7 and the resistor R6 is connected to the input terminal of the control signal F3 via the resistor R4, and is also connected to the above-mentioned resistor R via the resistor R5.
2, connected to the connection point of R3. Moreover, the connection point of the above-mentioned resistors R2 and R3 is grounded via a capacitor C1 that determines the charging/discharging time constant. The resistance values of the resistor R3 are the resistors R1, R2, R4, R5, R6°R7,
The resistance value is set to be sufficiently larger than the resistance value of . This is because the time constant of charging and discharging is determined by the capacitance of the capacitor C1 and the resistance value of the resistor R3.

Then, the voltage VIO generated at the connection point between the variable resistor R7 and the resistor R6 (referred to as "point A" for convenience of explanation) is
It is made into a level control signal SL- through a well-known inversion circuit composed of a resistor R9 and an operational amplifier OPI. Note that the symbol Vr is a reference voltage supplied to the non-inverting input terminal of the operational amplifier oP1.

Further, as shown in FIG. 4, the details of the setup control circuit 40 are configured in the same manner as the above-mentioned control circuit 22, so the numbers are given by adding 10 to the number of subscripts of each of the above-mentioned symbols. The difference from the above is that the setup command signal S2 is the control signal F2. F3. The voltage V20 generated at the connection point between the variable resistor R17 and the resistor R16 (referred to as 18 points for convenience of explanation) is converted to the setup control signal S2- through a well-known inverting circuit. That's true.

The fade operation in this embodiment configured as described above will be explained below with reference to FIGS. 5 to 9.

When the white fade operation is not performed, the video level can change between the white level Lw and the pedestal level Lp in accordance with the video signal, and the set-up level Ls at that time is 0.07 V. low level L
It has sO.

In order to perform the white fade-in operation, each of the control signals Fl, F3°F4 forming the level control command signal S1 from the control signal generation circuit 60 is set at the time T.
1, all are set to L level. Then, the input terminals of control signals Fl and F3 become approximately ground level, and at the same time, transistor Q1 is turned off, and inverter G1
The output terminal of becomes H level. Therefore, the equivalent circuit is
As shown in FIG. 6, the voltage at point A, vlo, becomes 1. This voltage v1 is inverted to a voltage v2 by an inverting circuit formed by an operational amplifier OPI, etc., and a level control signal Sl- is obtained. The voltage v2 of the level control signal S1= at this time is VC shown in FIG.
The gain at A21 is set to be the minimum. Therefore, the output signal S of the imaging means 10 is significantly attenuated by the level control circuit 20, so that the video level becomes the pedestal level Lp. Therefore, the video component of the output of the imaging means 10 is not supplied to the video signal processing circuit 30.

At the same time, the control signal F2. which forms the setup control command signal S2 from the control signal generation circuit 60.
F3. F4 are all brought to L level at time T1. Then, the control signal F2. F3. All input terminals of F4 become approximately ground level, and at the same time, transistor Qll is turned off and the output terminal of inverter Gll becomes H level. Therefore, the equivalent circuit is the 8th
As shown in the figure, the voltage V20 at point B becomes v3. This voltage v3 is inverted to a voltage v4 by an inverting circuit formed by an operational amplifier 0PII, etc., and a setup control signal 82'' is obtained.

Then, at time T2 after a predetermined time has elapsed from time T1, control signal F2 is inverted to H level. Then,
The capacitor C1l, which has been charged to a balanced state in the equivalent circuit shown in FIG. 8, is gradually charged up by the voltage applied to the H level signal via the resistor R12, as shown in the equivalent circuit shown in FIG.

The voltage V20 at point B at this time is inverted by an inverting circuit formed by an operational amplifier 0P11, etc., and a setup control signal S2'' that gradually decreases is obtained. V2
is maintained.

Then, at time T3 after a predetermined time has elapsed from time T2, control signal F1 is inverted to H level. Then,
The capacitor C1, which has been charged to a balanced state in the equivalent circuit shown in FIG. 6, is gradually charged up by the voltage applied to the H level signal via the resistor R2, as shown in the equivalent circuit shown in FIG. The voltage v10 at point A at this time is inverted by an inverting circuit formed by an operational amplifier OPI or the like, and a level control signal SL- which gradually decreases is obtained.

As a result, the set-up level L s 1 (0
, 7V) is maintained between time T1 and time T2, and during this period, the gain of the level control circuit 20 is controlled to the minimum.

Then, the set-up level is gradually lowered from time T2, and the set-up level is approximately equal to the white level Lw of the video level.
/3 (time T3), the level control signal Sl
- is gradually decreased and the gain of the level control circuit 20 is gradually increased. Therefore, a white fade-in operation is performed, and a normal video output signal V.OUT can be obtained at time T4.

On the other hand, when performing a white fade-out operation, the level control command signal S from the control signal generation circuit 60 is
1 and the set-up control command signal S2, at the start time T5 of white fade-out, the control signals Fl, F2
．． All of F3 are set to L level, and control signal F4 is set to H level. Then, the output terminals of the inverters Gl and Gll of the control circuit 22 and the setup control circuit 40 become L level, and at the same time, the control signals Pi, F2 . The input terminals of F3 are both at approximately ground level.

Therefore, at time T4 when the white fade-in operation is completed, or in a normal state where no fade operation is performed, the charges in the capacitors C1 and 11, which are in the fully charged state, are gradually discharged, and as a result, the level Both the control signal Sl- and the setup control signal S2- rise gradually. Then, at time T6 when the discharge of the capacitor C1 is completed, the gain of <VCA21 becomes minimum based on the level control signal Sl-. Further, the set-up level is gradually increased from time T5 based on the discharge of the capacitor C11, and at the time T7 when the discharge is completed, the set-up level based on the set-up control signal S2- reaches the maximum, and that level is equal to the video level. It becomes approximately equal to the white level Lw, the white fade operation ends at time T8, and the video output signal V-OUT
The image based on the image becomes completely white.

Note that the symbol REC shown in FIG. 5 is a recording control signal for actually recording in an interval excluding the transient time τ at each of the self-fade-in start point and the white fade-out start point.

On the other hand, when performing a black fade operation, the aforementioned setup control circuit 40 is made inactive and the setup control signal S2- is made to set the setup level of the video signal to a normal level. In this state, the level control signal Sl'' sent from the control circuit 22 is set to V
The gain of the CA 21 may be appropriately set to gradually increase during black fade-in, and may be appropriately set to gradually decrease during black fade-out.

[Effects of the Invention] As described above, according to the present invention, a circuit configured using an IC having a black fade function can be made to have a self-fade function by simply adding a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a
FIG. 4 is a detailed circuit diagram of the control circuit shown in FIG. 2, FIG. 4 is a detailed circuit diagram of the setup control circuit, and FIG. 5 is the control circuit and setup control circuit shown in FIGS. 3 and 4. Figures 6 and 7 are equivalent circuit diagrams of the control circuit shown in Figure 3. Figures 8 and 9 are equivalent circuit diagrams of the setup control circuit shown in Figure 4. 10 is a diagram for explaining the black fade operation, and FIG. 11 is a diagram for explaining the white fade operation. 10...71 (1 hand L20...level control circuit, 30...video signal processing circuit, 40...setup control circuit, 5
0...Mixer circuit, 60...Control signal generation circuit. Horse 3 map A 4 outside wards 5 outside 6 wards outside 7 wards 10 outside wards 11 outside wards

Claims (1)

[Scope of Claims] A level control circuit that controls the amplitude of an output signal of an imaging means; A video signal processing circuit that separates the output of the level control circuit into a color signal and a luminance signal and performs predetermined signal processing; A setup control circuit that controls the setup level given to the video signal processed by this video signal processing circuit, and a synchronization signal and a color burst signal are added to the video signal whose setup level is controlled by the output signal of this setup control circuit. A video signal fade circuit comprising: a mixer circuit; and a control signal generation circuit that provides control signals to the level control circuit and setup control circuit to respectively control the operations of both circuits. .