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JPS6263470A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6263470A
JPS6263470A JP20179585A JP20179585A JPS6263470A JP S6263470 A JPS6263470 A JP S6263470A JP 20179585 A JP20179585 A JP 20179585A JP 20179585 A JP20179585 A JP 20179585A JP S6263470 A JPS6263470 A JP S6263470A
Authority
JP
Japan
Prior art keywords
region
emitter
base
electrode
emitter region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20179585A
Other languages
Japanese (ja)
Inventor
Hideo Kawasaki
川崎 英夫
Akira Yamazaki
晃 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20179585A priority Critical patent/JPS6263470A/en
Publication of JPS6263470A publication Critical patent/JPS6263470A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make it possible to perform high speed switching operation, by isolating an inner emitter region other than an active region in the emitter region, and reducing charge accumulated in a base region. CONSTITUTION:A base region 2 is formed on a collector substrate 1. An emitter region 3 is formed in the base region. At this time, an isolating region 4, which has the same conductivity type as the emitter region, is isolated from the emitter region 3 and formed at a part separated inward from the emitter region on the opposite side of a base electrode 5. An emitter electrode 6 is connected to the emitter region 3. The base electrode 5 is connected to the base region so that the electrode 5 is insulated from the emitter electrode 6 by an insulating film 7. At this time, the isolating region 4 is not connected to the electrode but is floated. At the time of switch OFF3 charge 8 is accumulated in the base region 2 beneath the emitter region 3 on the opposite side from the base electrode 5. The expansion of the accumulated charge 8 is suppressed by the effect of the isolating region 4. Thus high speed switching can be performed because of the fact that the expansion of the charge is proportional to the switching time.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、高速スイッチングトランジスタに関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to high-speed switching transistors.

(従来の技術) 従来トランジスタのスイッチング特性を向上させる方法
を第2図および第3図に基づいて説明する。第2図(a
)および第3図(a)はともに、従来のトランジスタの
断面図であり、第2図(b)および第3図(b)は同電
荷蓄積分布図である。同図において、11は半導体基板
、12はベース領域、13はエミッタ領域、14はエミ
ッタ電極、15はベース電極、16は絶縁膜であり、1
7はスイッチング・オフ時のベース領域中の蓄積電荷で
ある。
(Prior Art) A method for improving the switching characteristics of a conventional transistor will be described with reference to FIGS. 2 and 3. Figure 2 (a
) and FIG. 3(a) are both cross-sectional views of a conventional transistor, and FIG. 2(b) and FIG. 3(b) are charge accumulation distribution diagrams of the same. In the figure, 11 is a semiconductor substrate, 12 is a base region, 13 is an emitter region, 14 is an emitter electrode, 15 is a base electrode, 16 is an insulating film, and 1
7 is the accumulated charge in the base region during switching off.

第2図で示すように、エミッタ領域13を細いストライ
プ状にし、エミッタ領域13の活性領域以外はベース領
域12のままにして、エミッタ領域13を電極で配線す
る方法であった。このようなトランジスタ構造において
は、スイッチング・オフ時にベース領域中に蓄積された
蓄積電荷17は、第2図(b)に示すようにエミッタ領
域下のベース電極15の反対側のベース領域12中に分
布し、この電荷はエミッタ領域13に入って徐々に減少
する。この減少時間がスイッチングのオフ時間になるた
め、電荷の蓄積量が少ない程、高速スイッチング特性が
得られることになる。
As shown in FIG. 2, the emitter region 13 is formed into a thin stripe shape, the base region 12 is left as it is except for the active region of the emitter region 13, and the emitter region 13 is wired with electrodes. In such a transistor structure, the accumulated charge 17 accumulated in the base region at the time of switching off is transferred to the base region 12 on the opposite side of the base electrode 15 under the emitter region, as shown in FIG. 2(b). This charge enters the emitter region 13 and gradually decreases. Since this decreasing time becomes the switching off time, the smaller the amount of charge accumulated, the faster the switching characteristics can be obtained.

また第3図に示すトランジスタ構造においては、エミッ
タ領域の幅を微細化することにより、第2図(b)に示
すように蓄積電荷17を少なくすることができる。
Furthermore, in the transistor structure shown in FIG. 3, by reducing the width of the emitter region, the accumulated charge 17 can be reduced as shown in FIG. 2(b).

(発明が解決しようとする問題点) 上記構成において、第2図(b)においてはストライブ
状のエミッタ領域の中間のベース領域に電荷が蓄積され
るため、高速スイッチング特性としては不充分であった
(Problems to be Solved by the Invention) In the above configuration, in FIG. 2(b), charges are accumulated in the base region in the middle of the striped emitter region, resulting in insufficient high-speed switching characteristics. Ta.

また、第3図(a)に示す構成においては、微細化によ
り、エミッタ領域の内部抵抗および電極の抵抗が大きく
なり、大電流では、エミッタ領域が均一に動作しにくい
ことになり、また微細化のため歩留りの低下が欠点であ
った。
Furthermore, in the configuration shown in FIG. 3(a), the internal resistance of the emitter region and the resistance of the electrodes increase due to miniaturization, making it difficult for the emitter region to operate uniformly under large currents. Therefore, the drawback was a decrease in yield.

本発明の目的は、従来の欠点を解消し、高速スイッチン
グ特性を有し、かつ歩留りのよい半導体装置を提供する
ことである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates the conventional drawbacks, has high-speed switching characteristics, and has a high yield.

(問題点を解決するための手段) 本発明の半導体装置は、半導体基板上に形成された一導
電型のコレクタ領域と、このコレクタ領域内に形成され
た反対導電型のベース領域と、このベース領域に接続さ
れたベー・スミ極と、前記ベース領域内に形成された一
導電型のエミッタ領域とよりなり、このエミッタ領域が
活性領域と、この活性領域に対して、前記ベース電極と
反対側に分離して形成さ九た内部エミッタ領域とより形
成されているものである。
(Means for Solving the Problems) A semiconductor device of the present invention includes a collector region of one conductivity type formed on a semiconductor substrate, a base region of an opposite conductivity type formed within the collector region, and a base region of the opposite conductivity type formed in the collector region. an emitter region of one conductivity type formed in the base region, and this emitter region is connected to an active region and a side opposite to the base electrode from the active region It is formed by nine internal emitter regions formed separately from each other.

(作 用) 上記構成により、スイッチング・オフ時にエミッタ領域
下のベース領域に蓄積される電荷は大幅に減少するため
、高速スイッチング特性を有することになる。
(Function) With the above configuration, the charge accumulated in the base region under the emitter region during switching off is significantly reduced, resulting in high-speed switching characteristics.

(実施例) 本発明の一実施例を第1図に基づいて説明する。(Example) An embodiment of the present invention will be described based on FIG.

第1図(a)は本発明の半導体装置の断面図である。FIG. 1(a) is a sectional view of the semiconductor device of the present invention.

同図において、コレクタ基板1の上にベース領域2を形
成し、ベース領域2にエミッタ領域3を形成する。この
際、エミッタ領域3と同一導電型の分離領域4をエミッ
タ領域3と分離して、ベース電極5と反対側のエミッタ
領域の内部へ形成する。
In the figure, a base region 2 is formed on a collector substrate 1, and an emitter region 3 is formed in the base region 2. At this time, an isolation region 4 having the same conductivity type as the emitter region 3 is separated from the emitter region 3 and formed inside the emitter region on the opposite side from the base electrode 5 .

さらに、エミッタ電極6をエミッタ領域3に接続し、ベ
ース電極5はベース領域に絶縁膜7によりエミッタ電極
6と絶縁して接続する。この際分離領域4は、電極と接
続させず、フロートしたままにする。
Furthermore, the emitter electrode 6 is connected to the emitter region 3, and the base electrode 5 is connected to the base region insulated from the emitter electrode 6 by an insulating film 7. At this time, the separation region 4 is left floating without being connected to the electrode.

このようにして、形成されたトランジスタは、スイッチ
ング・オフ時に、第1図(b)に示すように、ベース電
極5と反対側のエミッタ領域3下のベース領域2に蓄積
電荷8が蓄積することになる。
When the transistor thus formed is switched off, the accumulated charge 8 is accumulated in the base region 2 under the emitter region 3 on the opposite side to the base electrode 5, as shown in FIG. 1(b). become.

しかし、この場合、蓄積電荷8の拡がりは、分離領域4
の効果により押えられる。したがって、電荷の拡がりが
スイッチング時間と比例することにより、高速スイッチ
ングが可能となる。またこの場合、分離領域4とエミッ
タ領域3の間隔は狭い方がよい。
However, in this case, the spread of the accumulated charge 8 is
It is suppressed by the effect of Therefore, the spread of charges is proportional to the switching time, thereby enabling high-speed switching. Further, in this case, it is better that the distance between the isolation region 4 and the emitter region 3 be narrower.

以」二述べたように、本実施例によれば、エミッタ領域
3の微細化は必要であるが、分離領域4は任意の大きさ
が可能のため、全体的な微細化は不必要であり、このた
め微細化にともなう歩留りの低下、および電極の抵抗増
加がなくなり、エミッタ領域で均一に動作することにな
る。
As described above, according to this embodiment, although it is necessary to miniaturize the emitter region 3, since the isolation region 4 can have any size, overall miniaturization is unnecessary. Therefore, there is no decrease in yield due to miniaturization and no increase in resistance of the electrode, and uniform operation is achieved in the emitter region.

さらに、高速スイッチングをはかるには、分離領域4を
、エミッタ領域3より深い拡散を行なうことにより、蓄
積電荷8を少なくすることも可能である。
Furthermore, in order to achieve high-speed switching, the accumulated charge 8 can be reduced by diffusing the isolation region 4 deeper than the emitter region 3.

(発明の効果) 本発明によれば、エミッタ領域の活性領域以外の内部エ
ミッタ領域を分離して形成し、ベース領域中の蓄積電荷
を減少させることにより、高速スイッチング動作が可能
なトランジスタが実現できその実用的効果は大である。
(Effects of the Invention) According to the present invention, a transistor capable of high-speed switching operation can be realized by separately forming an internal emitter region other than the active region of the emitter region and reducing accumulated charges in the base region. Its practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の一実施例による半導体装置の断
面図、第1図(b)は同電荷蓄積分布図、第2図(a)
は従来の半導体装置の断面図、第2図(b)は同電荷蓄
積分布図、第3図(a)は他の従来の半導体装置の断面
図、第3図(b)は同電荷蓄積分布図である。 1.11・・・半導体基板、 2,12・・・ベース領
域、 3,13・・・エミッタ領域、 4 ・・・同一
導電型の分離領域、 5,15・・・ベース電極、6.
14・・・エミッタ電極、 7 ・・・絶縁膜、8 ・
・・蓄積電荷。 特許出願人 松下電子工業株式会社 第1図 (a) 1 ゛平〜i4イ、+しI 縁 2 べ一人@域 3  エミッ7肩1人 8・°署y4芝荷 第2図
FIG. 1(a) is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a charge accumulation distribution diagram of the same, and FIG. 2(a)
is a sectional view of a conventional semiconductor device, FIG. 2(b) is a diagram of the same charge accumulation distribution, FIG. 3(a) is a sectional view of another conventional semiconductor device, and FIG. 3(b) is a diagram of the same charge accumulation distribution. It is a diagram. 1.11... Semiconductor substrate, 2, 12... Base region, 3, 13... Emitter region, 4... Isolation region of the same conductivity type, 5, 15... Base electrode, 6.
14...Emitter electrode, 7...Insulating film, 8.
...Accumulated charge. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 (a) 1 ゛ flat ~ i4 A, +shi I Edge 2 One person @ Area 3 Emi 7 Shoulder 1 person 8 ° Sign y4 Shiba load Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された一導電型のコレクタ領域と、
該コレクタ領域内に形成された反対導電型のベース領域
と、該ベース領域に接続されたベース電極と、前記ベー
ス領域内に形成された一導電型のエミッタ領域とよりな
り、該エミッタ領域が活性領域と、該活性領域に対して
、前記ベース電極と反対側に分離して形成された内部エ
ミッタ領域とより形成されていることを特徴とする半導
体装置。
a collector region of one conductivity type formed on a semiconductor substrate;
It consists of a base region of opposite conductivity type formed in the collector region, a base electrode connected to the base region, and an emitter region of one conductivity type formed in the base region, and the emitter region is activated. What is claimed is: 1. A semiconductor device comprising an internal emitter region and an internal emitter region formed separately on a side opposite to the base electrode with respect to the active region.
JP20179585A 1985-09-13 1985-09-13 Semiconductor device Pending JPS6263470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20179585A JPS6263470A (en) 1985-09-13 1985-09-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20179585A JPS6263470A (en) 1985-09-13 1985-09-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6263470A true JPS6263470A (en) 1987-03-20

Family

ID=16447058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20179585A Pending JPS6263470A (en) 1985-09-13 1985-09-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6263470A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008518A (en) * 1996-09-06 1999-12-28 Mitsubishi Denki Kabushiki Kaisha Transistor and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008518A (en) * 1996-09-06 1999-12-28 Mitsubishi Denki Kabushiki Kaisha Transistor and method of manufacturing the same

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