JPS6257930B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention enables a detector such as a position encoder, a laser interferometer, etc. to change the phase according to a change in position.
The present invention relates to a device that is used in a device that outputs two sine signals that differ by 90 degrees, and that further divides and reads the sine signal.

Conventionally used position encoder signal division reading devices apply two sine signals obtained from a detector with a phase difference of 90 degrees to a resistor array to form sine signals of various phases. A method is known that counts all zero-crossing points of the signal.

However, such conventional divisional reading devices have the disadvantage that a large number of zero detection circuits are required to increase the number of divisions, resulting in a complicated circuit configuration.

An object of the present invention is to provide a divisional reading device with a simple circuit configuration.

The present invention will be described below based on embodiments shown in the drawings.

In the following embodiments, in order to proceed with the discussion concretely, an example in which the divisional reading device of the present invention is applied to a linear encoder will be explained. In a linear encoder, two sine voltages with a phase difference of 90 degrees can be obtained as the output of the detector due to the directional valve.

FIG. 1 is a circuit diagram showing the principle of split reading according to the present invention, in which the zero detection circuits 2 and 4 detect two sinusoidal voltages e ₀ and e ₉₀ obtained from the above-mentioned detector (e ₉₀ is equal to e ₀₎ . (which is a sine voltage with a phase lead of 90 degrees)
This is for shaping the waveform into a rectangular voltage with 0V as the reference. The gate circuit 6 forms pulses at the rise and fall of a rectangular voltage corresponding to the voltage e ₀ , and determines the moving direction of the main scale of the encoder from the relationship between the two rectangular voltages corresponding to the voltages e ₀ and e ₉₀ , respectively. When the movement is in the forward direction, a pulse is output to the terminal connected to the up input a of the up-down counter 8, and when the movement is in the reverse direction, the pulse is output to the terminal connected to the up input a of the up-down counter 8.
A pulse is output to the terminal connected to the down input b of the Therefore, the number of counting pulses of the counter 8 is:
Corresponds to the displacement of the main scale from its initial position. Further, if the configuration is such that a half period of the voltage e ₀ corresponds to 1 μ on the main scale, it can be seen that the displacement of the main scale is n μ based on the count n of the counter 8. Such a configuration is well known as a counting circuit of a conventional linear encoder.

On the other hand, the sine voltages e ₀ and e ₉₀ are converted into digital signals e _D0 and e _D90 by the AD converters 10 and 12, respectively, and then e _D0 /e _D90 is calculated by the dividing circuit 14 and output. The calculation circuit 16 calculates tan ⁻¹ e _D0 /e _D90 .

The conversion circuit 18 converts tan ^-1 , which is the output of the arithmetic circuit 16, according to the rounding width set in advance depending on how many parts the half cycle (180 degrees) of the sine voltage is divided into.
A signal converted from e _D0 /e _D90 is output (that is, a half cycle of the sine voltage is interpolated). For example, when dividing a half period into 10 as shown in FIG. 2, the rounding width is 18 degrees, so the conversion circuit 18
tan ^-1 e _D0 /e 0 when _D90 is 0 degrees to 18 degrees, 18 degrees to 3
A digital signal corresponding to 0 to 9 is output every 18 degrees, such as 1 for 6 degrees, 2 for 36 degrees to 54 degrees, and so on.
If a half period (180 degrees) corresponds to 1μ, then the order of these signals corresponds to 0.1μ. Addition circuit 2
0 is a drive signal for the display 22 by adding the output of the conversion circuit 18 to the count content of the counter 8. Therefore, if the output of the conversion circuit 18 is m (0≦m≦9), the display circuit 22 displays (n+0.1m) μ. Therefore, the reading accuracy has been improved by one order of magnitude. Note that the arithmetic circuit 16 and conversion circuit 18 used in the above explanation store the ratio e _D0 /e _D90 and the values from 0 to 9 corresponding to the ratio in the ROM, and use the division circuit It is also possible to use the value from 14 as ROM address designation data. Furthermore, after calculating the ratio between the voltages e ₀ and e ₉₀ in an analog manner, it is also possible to perform analog-to-digital conversion and processing.

However, in the circuit configuration used in the above explanation, the circuit for detecting the zero-crossing point of the sine voltage e ₀ and the circuit used for divided reading are independent, so for example, the amount of drift may differ depending on each circuit. As shown in FIG. 3, reading problems occur at carry positions. The following is a description of an embodiment of the present invention that overcomes the drawbacks. Figure 3a
is the sinusoidal voltage e ₉₀ and FIG. 3b is the sinusoidal voltage e ₀ . Figure 3c shows a rectangular voltage shaped into a waveform at the zero crossing point of the sine voltage e ₉₀ , and Figure 3d shows the sine voltage e _0.
These are the outputs of circuits 2 and 4 in FIG. 1, respectively. Figures 3e and 3f are pulses generated at the rising and falling edges of Figures 3c and d. FIG. 3g shows the count value of the counter 8 in FIG. Fig. 3 h and i are the values obtained by dividing the half period of Fig. 3 b, respectively.
Figure i is an example where the reference position is shifted to the right with respect to Figure 3g. In other words, when the divided minimum digit is read as shown in Figure 3h, the overall reading is as follows:
At position A it is 9999, at position B it is 9990,
The reading value of 0000 at position C and 9990 at position B becomes a meaningless value. In addition, if the reading of the divided minimum digit is as shown in Figure 3 i, at position A it is 9998, at position B it is 9999, at position C it is 0009, and the reading value 0009 at position C is meaningless. It becomes a value. Therefore, the display should be either Fig. 3 g or Fig. 3 h (or i).
If one of the two values is not used as a reference and the value of the other is not corrected, the digital display will lose its meaning. FIGS. 4 and 5 are examples of correcting the reading of FIG. 3 g based on FIG. 3 h, that is, the value of the minimum digit. The difference between the circuit in Figure 4 and that in Figure 1 is that the function of the counter has been changed as described later, and a gate circuit 30 has been added. Explanation will be omitted. Blocks 30 and 80 of FIG. 4 will be explained in detail with reference to FIG. In FIG. 5, the gate 50 outputs an H signal to the upper output terminal when the output of the conversion circuit 18 is 0 to 4, and outputs an H signal to the lower output terminal when the output is 5 to 9. Gate 51 is an exclusive OR gate and outputs an H signal only when the signal levels from zero detection circuits 2 and 4 are different. The gate 52 connects the upper output terminal of the gate 50 and the gate 5
The signal generated at the first output terminal is input, and when the two input signals are H, an H signal is output. When the output of the gate 52 becomes H, the one shot circuit 54 outputs one pulse and increases the count of the preset counter 82 by one. On the other hand, the gate 53 is
A signal generated at the lower output terminal of the gate 50 and the two output terminals of the gate 51 is input, and the signal generated at the lower output terminal of the gate 50 is inputted.
An H signal is sent to the lower output terminal of the gate 51.
The one-shot circuit 55 outputs an H signal when an L signal is generated at the output terminal of the gate 53.
When the output becomes H, one pulse is output and the count content of the preset counter 82 is decremented by one. The counter 80 has counters 81a and 81 corresponding to each digit.
b, 81c, and the pulses from the gate circuit 6 in FIG. 1 are sequentially counted. It should be noted that the counters 81a to 81c are the counters 8 in FIG.
corresponds to The preset counter 82 receives the contents of these counters 81a, 81b, and 81c in parallel. Because of this configuration,
For example, assume that at the position shown in FIG. 3B, the output of the converting circuit 18 is 0 as shown in FIG. 3h. At this time, the counter 81a is 9, the counter 81b is 9,
The counter 81c counts 9. Since the outputs of the zero detection circuits 2 and 4 are L and H, respectively, the gate 51 outputs an H signal. On the other hand, conversion circuit 1
Since the output of 8 is 0, the output to the upper terminal of gate 50 is H, and the output of gate 52 is H. Therefore, preset counter 82 counts one pulse, and the count becomes 000. Therefore, in this case, 9999 is at position A in Figure 3, and 9999 is at position B.
0000, the count value becomes 0000 even at position C, and the count value continues.
For example, assume that the output of the conversion circuit 18 at the position shown in FIG. 3C is 9 as shown in FIG. 3I. At this time, the counter 81a is 0, the counter 81b is 0,
The counter 81c counts 0. Since the outputs of the zero detection circuits 2 and 4 are H and H, respectively, the gate 51 outputs an L signal. On the other hand, conversion circuit 1
Since the output of 8 is 9, the output to the lower terminal of gate 50 is H, and the output of gate 53 is H. Therefore, preset counter 82 subtracts one pulse, and the count becomes 999. Therefore, in this case, 9998 is at position A in Figure 3, and 9998 is at position B.
9999, the count value becomes 9999 at position C as well, and the count value continues.

In this way, discontinuous values that may occur at carry positions due to inherent errors in each circuit can be corrected at the reading stage.

As described above, the split reading device of the present invention takes the ratio of the magnitudes of two sine signals whose phases differ by 90 degrees, and makes this ratio correspond to, for example, the displacement of the main scale of a linear encoder, so the circuit configuration is Not only is it simple, but it also has the advantage of being able to freely adjust the number of divisions by just slightly changing the configuration of the conversion circuit, ROM, etc., and furthermore, reading values can be obtained continuously.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the principle of the device of the present invention, Fig. 2 is a waveform diagram to explain the state of division,
FIG. 3 is a waveform diagram explaining reading errors that may occur in the circuit of FIG. 1, FIG. 4 is a block diagram of an embodiment in which a reading error correction circuit is added to the circuit of FIG. 1, and FIG. 5 is a block diagram showing details of blocks 30 and 80 of FIG. 4. FIG. [Explanation of symbols of main parts] Division circuit...1
4. Conversion circuit...18.

Claims (1)

[Claims] 1. The phase obtained by the detector according to the position change.
pulsing means for pulsing two sine signals that differ by 90 degrees at predetermined levels, and counting pulses corresponding to one sine signal in the positive direction among the pulses produced by the pulsing means, and adding the pulses to the other sine signal. A sine signal division reading device for use in a reading device comprising: counting means for counting corresponding pulses in the negative direction; converting means for converting the output of the dividing means into an interpolated value corresponding to the position between the pulses, and outputting the first signal; a first gate means for outputting a second signal in other cases; and a third signal for outputting a third signal when one of the sine signals is higher than the predetermined level and the other is lower than the predetermined level; a second gate means for outputting a fourth signal; when the first signal and the third signal occur together, 1 is added to the count value of the counting means; when the second signal and the fourth signal occur together; a correction means for subtracting 1 from the count value of the counting means; a synthesis means for synthesizing the count value of the counting means corrected by the correction means and the interpolated value of the conversion means and outputting a composite value; A split reading device characterized by having: