JPS6236797A - Semiconductor device - Google Patents

Abstract

PURPOSE:To solve effectively such problems as an excessive transient power supply current or malfunction, etc. by using an external power supply voltage generating circuit provided in a chip to actuate a circuit part which causes a transient power supply current when a power supply is applied and prescribing the characteristics of the internal power supply voltage generating circuit. CONSTITUTION:A semiconductor substrate or a chip incorporates a main body circuit part 200 of a semiconductor device, a substrate voltage generating circuit 300 which produces the substrate voltage VBB and supplies it to a substrate 1 and an internal power supply voltage generating circuit 400 which produces the internal power supply voltage VINT and supplies it to the part 200. The part 20 is equal to a memory circuit or other various circuits of microcomputers in accordance with the types of semiconductor devices. Then the part 200 works mainly on an external power supply VCC. While the circuit part which causes a transient power supply current when a power supply is applied is actuated by the voltage VINT. Thus the transient current is suppressed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is applicable to a semiconductor device suitable for solving problems such as excessive transient power supply current or malfunction caused by voltage fluctuations in a semiconductor device when power is turned on or during operation. Involved.

[Background of the invention]

In a semiconductor device, it is known that various problems occur because the internal state of the semiconductor device differs from the normal operating state during a certain period of time when the semiconductor device stabilizes to a normal operating state immediately after power is turned on. Among the problems that occur when turning on the power,
One of the most important problems is the generation of excessive transient power supply current, which in some cases may lead to destruction of the power supply device for driving the semiconductor device or the semiconductor device itself. The approximate value of the occurrence of this transient power supply current is
Let's explain using a diagram.

FIG. 1 schematically shows the cross-sectional structure of the main components of a MOS dynamic type memory (abbreviated as DRAM). Here, it has become mainstream in recent DRAMs. An example in which a substrate voltage generation circuit is built into a chip is shown. A memory cell for storing 1 bit of information is composed of one MOS transistor as a switching buffer and one capacitor for information charge 1M. An example using a so-called transistor type cell is shown. In the figure, 300 is the above-mentioned chip-embedded substrate voltage generation circuit. Here, for convenience, 300 is shown as a separate circuit from the silicon substrate 1 of the chip, but it goes without saying that it is actually provided mainly on the surface of the substrate 1 or in the vicinity thereof. The circuit configuration shown in 300 is an example of generating the saw plate voltage V- by the well-known charge pump method, and O20 is a circuit that generates a periodic signal for the charge pump, and is usually an automatic circuit. It consists of an excited oscillation type ring oscillator circuit.

C2 is a charge pump capacitor, which is often formed by taking advantage of the anti-layer structure. D is a rectifying diode, which is the drain of the MOS transistor.

For details on the configuration and operation of these circuits, which are often used as diodes by connecting the in and gate.

Jitsusho 54-82150, or 1976 ISC Digest of Technical Papers (T
SSCC Digest of Technical P
apsrs) pp, 138-139, etc.

1 is a silicon substrate; if the main component of the circuit is an N-channel MOS transistor, a P-type silicon substrate;
If the main component is a P-channel MOS transistor, an N-type silicon substrate is used, but the former case will be described below as an example. 2 is an insulating film for isolation between elements. 38 to 3e are relatively high concentration N (hereinafter referred to as N') type impurity diffusion layers, 48 to 4c are gate electrodes,
It is formed of polysilicon, AΩ, a high melting point metal such as W or Mo, or a silicide material such as WSi, MOSi, or the like. 4a to 4c may be formed using different processes or different materials depending on the case. 4
Although there is a gate insulating film between a to 4c and the substrate 1, it is omitted here for simplicity.

Here, 4a, 3a, 3b are memory cell switches MO8
, and 4b is an information charge? jj product capacitor electrode (hereinafter referred to as plate electrode), and the capacitor is connected to this electrode and 11! Inversion layer 5 formed directly below
formed between. Note that the insulating film that exists between 4b and 5 and acts as a dielectric is omitted in the figure, as described above.

4c, 3d, and 3e also constitute MOS transistors, and are shown as representative MOS transistors constituting circuits other than memory cells.

In the figure, numerals 7 and 8 schematically indicate the division of regions within the memory chip, with numeral 7 indicating a portion of the memory cell array, and numeral 8 indicating a peripheral circuit section for controlling the operation of the memory cell array. 7,8
It goes without saying that each of them is composed of a plurality of circuits each including a plurality of memory cells and a plurality of MOS transistors.

Now, in one or more memory chips, an excessive transient current at the time of power-on is mainly generated by the following two mechanisms.

First, during the period when the substrate voltage generation circuit does not operate sufficiently immediately after the power is turned on, the substrate voltage ■8. is lower than the normal value (
3d because the absolute value is small).

This is because the threshold voltage of the MOS transistors 3e, 4c, etc. becomes negative, and therefore a transient current flows from the power supply voltage v0° toward ground.

That is, as shown in the same figure (B), the substrate voltage generation circuit has a power supply voltage ■. . is a certain voltage V, 1. Therefore, V m m becomes almost Ov, and since the threshold voltage of the MOS transistor becomes negative in some cases, a transient current flows. Regarding the above phenomenon, the 1980 ISSC Digest of Technical Papers (ISSCCDiges)
Another mechanism for generating transient power supply currents is caused by capacitive coupling between the power supply voltage and the substrate. This phenomenon is
This has become a particular problem in recent years because the parasitic capacitance between the power supply voltage and the substrate increases as the degree of integration of memories increases.

The biggest influence is the transient power supply current generated by the parasitic capacitance C□ between the plate electrode 4b and the substrate. At this time, the power supply current I. . The peak value I, is expressed as. Therefore, when the value of C2, becomes extremely large due to the increase in memory density, C,.

The displacement current flowing between V Ce and the substrate becomes extremely large. Also, the steeper the rise of the power supply voltage, the more
becomes larger. At the same time that the above current is observed as a transient power supply current when the power is turned on, the following phenomenon occurs, further increasing the transient current. That is, in the type with a built-in substrate voltage generation circuit, the driving ability of the substrate voltage generation circuit is originally low, and the substrate voltage generation circuit does not operate normally immediately after power is turned on, so that the substrate 1 is almost in a floating state. Therefore, when current flows through C□, as shown by the broken line in the same figure (B), ■1. rises in the positive direction. As a result, the threshold voltage of the MOS transistor mentioned above changes further in the negative direction, and at the same time, the following phenomenon, which becomes a more important problem, occurs. That is, 3
A forward bias is applied between the N'''' type diffused layer type substrates 1 such as c and 3e, and a parasitic bipolar transistor as shown by Q□+Qz acts as an active element.
■. A current such as 1000 m flows, which further increases the transient current in addition to the above-mentioned displacement current.

In other words, the current generated by the capacitance @C0 becomes the base current. Therefore, the current flowing between the collector and emitter is 1. (current amplification factor) times,
Q,,Q, etc. 1. depends heavily on This value is Q
,,Q, are lateral type transistors, so
Although it is smaller than normal ones, as the integration becomes higher and the distance between the diffusion layers that act as emitters and collectors becomes narrower, 2. is growing and becoming an important issue.

The generation mechanism of transient power supply current at power-on has been explained above using a DRAM using an N-channel MOS transistor as an example.
Technical Papers)pp, 56-5
7°285-286. P channel M, as seen in
In the case of a so-called OMOS type DRAM that uses both an OS transistor and an N-channel MOS transistor as main ellipsoidal elements, the above problem of transient current becomes even more important.

Note that when the power is turned off, the first
As shown in figure (B), the substrate voltage fluctuates in a more negative direction, but
This does not significantly affect the transient current that is the issue here. Therefore, in each of the drawings below, waveforms at the time of cutting will be omitted, and explanations will also be omitted.

FIG. 2 shows a cross section of the main part of the CMO8 type LSI. 1 is a P-type silicon substrate, and 9 is an N-type impurity diffusion layer, usually called a well, in which a P-channel MOS transistor is formed. On the other hand, an N-channel MOS transistor is formed directly on P-type silicon substrate 1. Note that the silicon substrate is N-type, the well is P-type, and an N-channel MOS transistor is placed in the well.
Of course, it is also possible to form the channel MOS transistor on the substrate. 3f and 3g are representative diffusion layers that become the source, drain, etc. of a MOS transistor.
The former is an N-type diffusion layer, and the latter is a P3-type diffusion layer. In such lateral movement, NPN types such as Q, P,
NP-type parasitic bipolar transistors, and R, , R
2, a parasitic resistance occurs. These are connected in a manner equivalent to a so-called thyristor element as shown in FIG. 3(B).

Therefore, every time the thyristor turns on (ignition state), V. . An excessive current may flow between the device and the ground, eventually leading to the destruction of the device. This is the so-called CM
This is a latch-up phenomenon in O5 semiconductor devices, and 19
82 IEDM, Technical Digest (I
EDM, Technical Digest) PP,
454-477 and others. In order to turn on such a thyristor element, it is sufficient to flow an ignition current of a certain value or more to the base of Q3 or Q4, but if the transient current that occurs when the power is turned on as mentioned earlier is This acts as an ignition current and becomes a serious problem.

Among the transient power supply currents mentioned above, those caused by the threshold voltage of the MOS transistor becoming negative can be reduced to some extent by setting the element constants. (ISSCCDigest of Te
Chnical Papers) pp, 228-22
9. This is stated in the following. However, the transient current caused by capacitive coupling will increase with increasing integration, and will become an important problem in the future. To solve this problem,
There is a method of changing the potential of the plate electrode 4b in FIG.
It is necessary to provide a low concentration N-type impurity layer directly under b. As a result, a new manufacturing process is required, and additional mask alignment margins are required in the photolithography process, resulting in a reduction in the effective memory cell area and a need to increase the chip area. This causes essential problems such as a decrease in manufacturing yield and an increase in price.

I have explained the transient current that occurs when the power is turned on, but
Even during normal operation, transient currents may similarly occur due to fluctuations in the power supply voltage, or may occur due to changes in the power supply voltage, or may occur due to changes in the power supply voltage, such as plate '1 in FIG. Voltage fluctuations are transmitted to channel 5 via L pole 4b.

It causes bad luck such as malfunction.

[Purpose of the invention]

Therefore, an object of the present invention is to effectively solve the above-mentioned problems such as transient power supply current or malfunction caused by voltage fluctuations during power-on or operation without adding a new manufacturing process, and to provide a high-performance, highly stable product. The object of the present invention is to provide a means for realizing a semiconductor device.

[Summary of the invention]

In the present invention, the circuit section that causes a transient power supply constant current when the power is turned on is operated by an internal power supply voltage generation circuit provided within the chip. As a result, the circuit section is operated almost at the same time as or after the substrate voltage generation circuit starts operating, and the generation of transient power supply current is effectively suppressed. Furthermore, by defining the characteristics of the internal power supply voltage generation circuit, problems such as malfunctions caused by voltage fluctuations can be solved.

[Embodiments of the invention]

FIG. 3 is an embodiment for explaining the basic concept of the present invention.

1 is a semiconductor substrate. 200 is the main circuit section of the semiconductor device, 300 is the substrate voltage V1. is generated and vl is applied to the board 1,
400 is the internal power supply voltage V
This diagram schematically shows an internal power supply voltage generation circuit that generates □ and supplies V□ to 200, and each of these parts is built in a semiconductor substrate or chip. 1
00 is the external power supply voltage V. . Here, the main circuit section 200 includes various circuits, such as a memory circuit as shown in FIG. 1, or other microcomputers, depending on the type of semiconductor device.

In the present invention, the main circuit section 200 mainly operates as an external v1 power supply as in the conventional case, but the circuit section that causes the transient power supply current generation when the power is turned on is as follows.
Transient current is suppressed by operating with internal power supply voltage V□7.

The figure (B) shows V in the present invention. tVjltV I
II? FIG. As shown in the figure, V□7 is vo. , ■, , are set as ■ or ■ to suppress the transient current. First, in (2), transient current is suppressed by slowing down the rise of V□7 when the power is turned on and reducing the current due to the capacitive coupling described above. i.e. 9
This is based on the fact that the transient current becomes smaller as the rise time of the current and voltage increases, as shown in equation (1). ■
IV! II? By setting the rise start time of V to be almost the same as the fall start time of V, , even if a transient current due to a displacement current flows due to capacitive coupling, by making the rise start time of V The fluctuation of the substrate voltage is suppressed so that the voltage is in the positive direction, or more precisely, the bipolar transistor or thyristor described in FIGS. 1 and 2 is not sufficiently turned on, and the transient power supply current is suppressed. (2) further improves the effect described in (2) by further delaying the rise start time of (2) and (2).

As described above, in the present invention, when the power is turned on, a transient 1! The transient power supply current can be reduced by slowing down the rise time of the operating voltage of the circuit section that causes g current generation, or by slowing down the rise start time. In addition, V + W
Of course, it is also possible to simultaneously suppress the rise time and rise start time of t.

As described above, according to the present invention, it is possible to effectively suppress the transient power supply current when the power is turned on.

FIG. 4 shows an embodiment of an internal power supply voltage generating circuit that realizes the above characteristics. R111 in the same figure? is the resistance,
C4,1 is a capacitance that parasitically occurs in the output 401 of this circuit.According to this embodiment, vtwt is R,,T and C4゜1.
The voltage rises with a time constant determined by vo, as shown in FIG. It is possible to realize V□7 with a slower rise. In other words, this embodiment makes it possible to realize the characteristic (2) shown in FIG.

As a result, transient power supply current can be effectively suppressed as described above. In this embodiment, a parasitic capacitance of C4°1 is used, but if the value is small, it is of course possible to add a separate capacitor.

FIG. 5 shows still another embodiment of the internal voltage generation circuit,
Vllll here? A charge pump circuit is used to generate this.

In the figure, C1 and C2' are circuits serving as units of a charge pump circuit, and osc' is a charge pump signal line, which is constructed of, for example, a self-oscillation type ring oscillator circuit as described above.

INV is an inverter circuit for creating an inverted signal.

C2□, C□′ are charge pump capacities, D to
Di' l D21 D2' is a rectifying diode. FIG. 3B shows the operation in a steady state of operation. As shown in the figure, the pulse φoac of amplitude v0° from the oscillator ○SC' in the chip changes from Ov to V. cl
vo in advance by (T,) and D.

The node 421, which had been charged to -vo (vo is the forward voltage of the diode), is boosted to 2V, -V. Accordingly, the node 422°421' becomes a voltage 2 (V, .-V,) which is dropped by v due to D2. Next is φ′. ,. becomes Ov, and node 420' becomes V. . When the voltage rises to T3 (T3), the voltage at the node 421' is further boosted to T3V, -2VD. Therefore node 422', i.e. V I N ? Hari, 'L, -
Therefore, the voltage dropped by VD becomes 3 (V..-Vゎ),
By repeating this cycle many times, a DC voltage 3 (vo.-V O) can be obtained at the output 401. The operation in the steady state has been described above, but when the power is turned on, the operation is as shown in FIG.

When the power is turned on, Vc+c+ rises, but osc
' does not work immediately as explained in Figure 1,
va. When the voltage reaches a certain voltage V'crt, the operation starts and one oscillator signal φ oa is output.

Therefore, ■8. ? As shown in the figure, it starts up after a certain period of time has elapsed since the power was turned on. At this time, since the operation start voltage of osc' is approximately equal to (or can be designed to be approximately equal to) the operation start voltage of OSC, shown in FIG. 1, vX□ and ■, as shown in FIG. 5(e).

stand up almost simultaneously (v m B stands up)
In other words, according to this embodiment, the characteristics shown in FIG. 3 can be realized.

Thereby, it is possible to effectively suppress the transient power supply current that occurs when the power is turned on. Further, according to this embodiment, the rising speed tbllll of v, llT? is almost t, □? Down ((C□＋
Cp'+)f'. ,. )-1...(2). Here f′. 1o is the oscillation frequency of osc'. In this way, the driving ability as a power supply voltage source is determined by CP
□t CF'xtf'. ,. can be controlled by Therefore, C□t Cr' ref fog.

By arbitrarily selecting t1□7, it is possible to control t1□7. For example, by increasing t and □7, it is possible to further suppress the transient power supply current.

Further, in this embodiment, the values of v, l, and a are theoretically 3 (vo.-V,), but can be controlled by the number of connected charge pump circuits C7. In other words, if the number of connections of C□ is n, then V X II? teeth.

vt*t= (n+1) (VC(l vl))
"' (3) By changing n, ■□□ can be controlled. For details, refer to osc'.

The circuit including the INV circuit is described in Japanese Patent Application No. 57-220083.

Now, in the embodiment described above, voo is V'a
■ and □ start to rise when they exceed t&, but if V'. , t is larger than 2V, D, l, in FIG. 5(A) before the charge pump operation starts.
There is a possibility that D and l are turned on and vIoA rises as shown by the broken line in FIG.

Even if this happens, the rise start of vl2a is v. Since the delay is longer and the rise time can be controlled by the above-mentioned equation (2), it is possible to suppress the transient power supply current, but in order to make it more complete, the following embodiment is available.

FIG. 6 shows an embodiment that makes the above possible, and differs from the embodiment in FIG. 5 in that the nodes 423 and 423' of cp and cp' are grounded (vcc in FIG. 5). Therefore, the operating waveform during normal operation of this embodiment is as shown in FIG. 5(B).The 0gJ operating principle is the same as in FIG.
Since it operates with reference to v, the output V I II 1 becomes 2(va.-Vo) Ve. This value is lower than the embodiment of FIG. 5, but if higher voltage is required,
As mentioned before, the voltage can be increased by increasing the number of charge pump circuits connected. In this embodiment, vl, l? When the number of circuits is n, the value of is □t
=n (Vcc VD) Vo...(4
).

According to this embodiment described above, Vll7 is oSC'
It will not be output unless it starts operating, and as shown in Figure 3 (■ in F()
It is possible to realize the characteristic that the current starts to rise almost at the same time as , and it is possible to effectively suppress the transient current.

FIG. 7 shows another embodiment of the V Ill'r generation circuit, in which it is operated based on the ground, that is, Ov, as in FIG. 6, and the output voltage value similar to that in FIG. This is an example of what can be obtained. As is clear from the figure, the circuit configuration differs from that in Figure 6 in that the INV output is applied to 423. The operating waveform during normal operation of the zero circuit is as shown in Figure (B); Similar to the figure, 3 (V..-V
, ) is obtained, and the number of CP circuits n and the output voltage V
Ill? The relationship is exactly the same as equation (3).

According to this embodiment, ■,,I? is the same as in Figure 6, osc
' is not output until it starts operating, and the output voltage value can be as high as in FIG. 5.

If the voltage value is higher than necessary, remove C'P,
It is clear from equation (3) that it can be lowered by reducing the number of stages in the charge pipe circuit. According to this embodiment,
It becomes possible to more effectively suppress the transient current when the power is turned on.

By using each of the embodiments shown in FIGS. 4 to 7 described above as the internal voltage generation circuit 400 shown in FIG. 3, it becomes possible to significantly suppress the transient current that occurs when the power is turned on.

In the embodiments shown in FIGS. 5 and 6, it was mentioned earlier that the value of VXTLT can be controlled by the number of charge pump circuits connected, but if more detailed control is required,
Embodiments such as those shown in FIGS. 8 and 9 may be used. These embodiments include a clamp circuit C, , consisting of diodes D,
is inserted into the output terminal 401 of the internal voltage generating circuit 400, and in FIG. 8 it is inserted between Vac and in FIG. 9 between it and ground. The value of VXTLT at this time is as shown in FIG. 8, where the forward voltage of the diode is VD and the number of connections is m.

V x * t = Vac + Tn Vo
”・(5) In the case of Figure 9, VIll?= m Vo
"' (6) Therefore, by changing the number of m, it is possible to set the value of VXTLT to an arbitrary value.

Now, in each of the embodiments described above, a diode is used as a component of a charge pump circuit, etc., but as shown in FIG. 10, the diode D is a MOS transistor Q, or a bipolar transistor Q,
You can replace it as is. In that case,
The forward voltage VD of the diode used in the explanatory diagrams and formulas mentioned above is the threshold voltage v? in the case of a MOS transistor. , in the case of a bipolar transistor, should of course be replaced by its base-emitter voltage Vmy.

In the embodiment described above, the internal voltage V□7 and the substrate voltage V when the power is turned on. It has been stated that it is desirable for the rise start times or rise times of the two to be synchronized with each other in order to reduce transient current.

It goes without saying that this object can be achieved in each of the embodiments described above, but the following embodiments are provided to ensure completeness. That is, ■,,7 and v,.

Method 11 of sharing the charge pump signal used for generation
The figure shows an example of this, in which the oscillation output of an oSC composed of a ring oscillator etc. is shared between v1s generation and v8.7 generation. In the same figure, INV' is an inverter circuit, Q,
, Q are MOS transistors, which constitute a push-pull type buffer circuit. CpHlQ
te Q# is bump capacitance for substrate voltage generation and MO for rectification
This is an example in which the diode in the circuit shown in FIG. 1 is replaced with a MOS transistor. This is as explained in FIG. The details of these operations are omitted as they are described in Japanese Patent Application No. 57-220083. In this embodiment, the output of the buffer circuit is
Charge pump signal φ for V INT generation in Figures to Figures 7
'10. used as As a result, vs, and v1□ are o
Even if the oscillation start voltage of the SC changes variously due to usage conditions, manufacturing conditions, etc., it will rise almost simultaneously or synchronously.■, 1, 1. It is possible to always keep the mutual relationship constant, and it is possible to more effectively suppress transient current when the power is turned on.

FIG. 12 shows yet another embodiment.

In this example, the 11th! In the example of jl, C0'.

Q7'lQI' is further added to increase the supply capacity of the V mm generating circuit. ■□1 generating circuit operates with the output of the buffer circuit composed of Q, , Q, as before. According to this, V when the power is turned on as shown in the same figure (B). The fall time of is reduced.

V! II? It becomes possible to set vss to a predetermined value before the voltage rises sufficiently, and the effect described in FIG. 12 can be further perfected. In addition, here V,
,? In order to change the supply capacity of can. Furthermore, the frequency is counted down by a counter circuit, and φ0. . ' can also be used to differentiate the supply capabilities of VXKT and vlS.

In addition, in this example, in order to increase the supply capacity of V1111, %CPII'IQ? ' t Q@' was added, but this mainly functions when the power is turned on, so during normal operation, turn off the switch SW,
It is also possible to reduce power consumption by stopping the operation.

Since the SW only needs to have a function to stop its operation, it can be inserted at any position as long as it can have the same function.For example, CpB' and Qt't
The switch may be placed anywhere, such as between Qs' and ground, or between Q, / and 731, and the switch may be constructed of any other material, such as a MOS transistor. Also, its on/off control is controlled by, for example, the power supply voltage v0° or V! W? There is a method that detects when a certain value has been reached and then turns off the switch. Also, ■1. The value of MOS
Turns on by utilizing changes in the threshold voltage of the transistor.

It is also conceivable to control off. These specific configuration methods are, for example, 1979 l5SCCI) igest o
fTechnical Papers, pp, 142
-143. It is stated in the following.

In addition, in FIG. 11 and FIG. 12, each charge pipe circuit shares the same. The output signal of SC is Q,.

However, the basic idea of each embodiment is to share the oSC, and the signal can be taken out from any position. For example, a signal may be directly branched from the output of the oSC and supplied to each charge pump circuit, and a buffer circuit may be provided if necessary.

In the above, we have described an example of the method for generating (1), , lT, and v. Next, we will describe an example in which these methods are applied to a specific semiconductor device.

Figure 13 shows the effect of the parasitic capacitance C□ formed between the plate electrode 4b of the information charge storage capacitor and the substrate, which particularly affects the generation of transient current when the power is turned on, in the MOS dynamic memory shown in Figure 1. In order to suppress this, the plate electrode 4b is connected to the internal voltage V IN? This is an example of driving with In addition, applying an internally generated voltage to the plate electrode in this way, Oct., 1980, pp. 839-846,
is known, but no consideration is given to the transient current at power-on, and nothing is mentioned about the relationship between V□1 and vl, which is particularly important in the present invention. In this example, V I I+ ? The generation circuit is φ
0. . ' is used as the oscillation signal of the VI1M generation circuit,
The method shown in FIG. 7 is used. In addition, other figures 4~
Of course, the circuit of the type shown in FIG. 6 or the circuit of a combination type thereof can also be applied as is.

According to this embodiment, as shown in FIG.
and V I HT start rising almost simultaneously.

As a result, as mentioned before, even if the displacement current due to CPa flows, the bipolar transistors Q,...
V ml does not rise to the extent that Q is turned on, making it possible to significantly suppress transient current. Furthermore, as shown in equation (2), the rise time of v, 1 can be made longer than that of vcc, so the displacement current itself due to CF2 can be made much smaller.

Figure 14 shows the present invention in a CMOS type (7) DRAM
In this example, V x *t is supplied to the plate electrode 4b as in FIG. 13.

In the same figure, as in FIG. 2, an N-well type CMOS is illustrated, 9' is an N-well, 3d' and 3e' are P9 diffusion layers, and together with the gate electrode 4c', a P-channel type MOSFET is shown.
It constitutes an S transistor.

In this embodiment, as in FIG. 13, when the power is turned on, 3. Since the amount of fluctuation in the positive direction can be reduced,
It is possible to solve the problem of latch-up caused by parasitic bipolar transistors such as Q3'IQ4', suppress transient currents, and solve the problem of element destruction caused by this.

In this embodiment, an N-well type CMOS is used as an example, but the present invention can also be applied to a P-well type CMOS 8 by simply reversing the potential relationship.

FIG. 15 shows an example in which, in the embodiment of FIG. 14, a trench-shaped capacitor known from Japanese Patent Laid-Open No. 49-57779 is used as the storage capacitor of the memory cell. The capacitor is formed on the sidewall of a trench dug into the Si substrate.
In this embodiment as well, the same effects as in FIG. 14 can be obtained, and at the same time, the following advantages are also provided. In order to eliminate the transient current due to C
It was mentioned earlier that there is a method of making the potential of the ground potential the ground potential.

To this end, even if 4b' is at ground potential, it is necessary to always form an N-type impurity layer along the side surfaces of the trench to form the channel 5'. However, it is extremely difficult to realize the above in such a structure. Thus according to the present invention.

Even when using a memory cell in which it is extremely difficult to set the plate electrode to ground potential, the transient current at power-on can be effectively reduced.

FIG. 16 shows another embodiment for making the present invention more effective, in which vl,7 applied to the plate electrode is
This figure shows an embodiment suitable for reducing fluctuations caused by memory operations.

In the figure, D, D', and D' are data lines, W is a word line, and a memory cell MC is arranged at the intersection of these lines.

As the MC, for example, memory cells as shown in FIGS. 13 to 15 are used.

38 is connected to the data line, and 4a is connected to the word line.

The plate electrode 4b or 4b' is distributed throughout the memory cell array as a common plate electrode among a plurality of memory cells arranged in a two-dimensional matrix,
Here it is PL, PL, PL'.

It is expressed as PL'. Here beams, D and D
', D' are paired, and MC Karari,
The minute readout signals appearing on D, D', and D' are
Differential amplification is performed by a sense amplifier SA placed in the center of each. In this way, this embodiment uses a so-called open data line configuration in which the paired data lines are spaced apart on the left and right.
This shows the case where Data Line5structure) is used. Details of this can be found in IEE PROC, V
oQ, 130. pt, 1. No, 3Jun
e 193g, pp, 127 135, for details.

Now, in such a memory, there is a parasitic capacitance IC between the data line and the plate, and since many data lines operate at once, the plate power supply fluctuates accordingly. Especially the VIN generated internally like the present invention? When driving the plate electrode with.

Since the driving ability of the VIHT generation circuit is small, its fluctuation becomes extremely large. This variation causes problems such as memory malfunction.

Therefore, in this embodiment, vIN? Generation circuit 40
SW' is inserted between 400 and the plate electrode, and when the plate electrode changes, SW' is turned off to prevent noise from occurring in the output of 400. Now, only the selected memory cell array among the memory cell arrays operates.

That is, D, MC in a part of the memory cell array to which D belongs.
When D' is selected, the memory cell array to which D' belongs is assumed to be in a dormant state, and its operation will be explained with reference to FIG.

D-D' is precharged to VI,p in advance,
Time 1. When a signal is applied to the word line, a small signal is output from the memory cell onto D or -b-.

At this time, since D' and D' are in a rest state, the 0 and SA operate to maintain a constant value, and the minute signal on D is amplified and output to the outside. At the end of the memory operation, it is precharged to VDF again. When this data line operates, the plate electrode fluctuates, but in this embodiment, when the data line fluctuates, it is turned off, so the fluctuation is not transmitted to 401 and no problem occurs.On the other hand,
If the potential fluctuation of the plate electrode is large, it may also cause malfunction. In this embodiment, this problem is solved as follows.

First, when amplifying a minute signal from the MC with SA or SA', PL and PL or PL' are connected so that non-in-phase noise is not generated in each of PL, PP or PL', PL'.
and H' are connected by low resistance wirings 403 and 403' so that they are always at the same potential. This is important in open data line structures where paired data lines are capacitively coupled to different plate electrodes. (IEE PROC, Vol. 130
．． pt, no, 3゜June1983. PP127-1
35) Furthermore, in this example, 403.403'
are also connected by low-resistance wiring 402, so that the parasitic capacitance of the non-operating memory cell array group acts as a filter, thereby reducing the amount of variation in the plate electrode.

In the above, it has been explained that SW' is turned off during memory operation (for example, from 1 until the data line is precharged to V, . . . ), but there are other control methods that can be considered. There is also a method of turning off SW' only during times when the data line potential changes significantly, that is, during periods when the sense amplifier operates, or during periods when the data lines are precharged to V□ at the end of memory operation. Furthermore, if necessary, resistors such as R3, R, etc. may be added to adjust the time constant against noise.

FIG. 17 shows a more preferred embodiment of the present invention, which differs from FIG. 16 in that a so-called folded data line configuration in which paired data lines are arranged substantially flat is used.
The difference is that the precharge voltage of the data line is approximately 1/2 of the power supply voltage Vcc.

In this embodiment, the paired data line, D= or D'
, D' are capacitively coupled with the same planes PL and PL', so there is no need to worry about non-common mode noise, which was a problem in FIG. As shown, the data line is precharged to approximately 1/2 of vcc, and the paired data lines always operate in opposite directions, so even if there is no coupling capacitance between the data line and the plate electrode. Even if they exist, they cancel each other out, so the plate electrode has the advantage of hardly changing. Therefore, in such a configuration,
In some cases, even if the output of 400 is directly connected to the plate electrode without going through SW', V i s will hardly fluctuate. In this embodiment, the data line precharge voltage was set to vcc/2, but as in FIG.
. . Needless to say, it can be closed or set to any other voltage.

Although the present invention has been described in detail in each embodiment, the scope of application of the present invention is not limited thereto, and various modifications are possible. For example, although the internal voltage is applied to the plate electrode in the explanation, it can also be applied to other parts, such as precharging a data line that has a large coupling capacitance with the substrate. This makes it possible to further improve the effect of reducing transient current. Note that the method of precharging the data line with an internally generated voltage is described in Japanese Patent Application No. 1986-10.
It is stated in No. 5710. Further, it is also possible to provide a current amplification circuit at the output stage of the internal voltage generation circuit to increase its driving capability and stabilize the operation.

In Fig. 5 to Fig. 7, Fig. 12 to Fig. 13, etc., V
Although INT is shown to have a higher voltage than VCe,
This does not have a particularly important meaning, and the value of V□7 can be changed variously as necessary using the circuits shown in FIGS. 8 and 9. Further, the clamp circuits shown in FIGS. 8 and 9 can also be constructed using other known Zener diodes. Further, in the embodiments shown in FIGS. 13 to 15, a memory having a MOS transistor as a main component has been described as an example, but the present invention can also be applied to a memory having a bipolar transistor as a main component.

FIG. 18 shows another embodiment suitable for preventing fluctuations in the internal voltage Vx, . In this embodiment, the necessary circuit parts are driven by the internal voltage generation circuit output only when the power is turned on, where transient current becomes a problem.
During the subsequent stable operation period, it is directly driven by the external power supply voltage vcC. Therefore, in this embodiment, fluctuations in VIIIT during normal operation are no problem at all.

In the same figure, 500 is a switch means that is turned off when the power is turned on and turned on thereafter.
Assuming that it is configured with an OS, a P-channel MOS transistor Q. . An example is shown below. Reference numeral 600 denotes a means having a function of recognizing and detecting the state when the power is turned on and after that, and here, V I I T and va. This example shows a case where the above function is realized by detecting that the voltage difference between the two has become a certain value or less, and an example is constructed using a CMOS inverter circuit composed of a P-channel MOS transistor Q6 and an N-channel transistor Qsaz. It shows. Here, Q6°, g is Q6. , set it sufficiently larger than that of vo and V X M ? The difference is almost Q
6°, threshold voltage V? When it becomes less than P, the output is “0”.
” (low voltage).

The outline of the operation is shown in (B) of the same figure. Power supply voltage 100
When 401 is turned on, 401 starts up with a delay as described above. At this time, since g of Q6°1 is sufficiently large compared to Qs02, 601 rises almost simultaneously with 100. Therefore, Q. .

is turned off, and the voltage of 401 increases according to the output of 400. After that, 401 increases with a constant time constant, and 1
When the difference from 00 becomes less than vvr, 601 becomes low voltage (~O
v) becomes Q,. . turns on. As a result, 401 is vo with the same potential as 1oo.

As a result, it becomes possible to completely solve the problem that the potential of 401 fluctuates during normal operation.

In this embodiment, the detection means 600 detects the state based on the voltage of vxlIT.1. In addition, V...
V, or other voltages may be detected, and the circuit 600 is not limited to the one shown in the figure and can be modified in various ways. For example, various circuits such as an operational amplifier circuit and a Schmitt trigger circuit can be used. Also, here vo. and V□.

I am trying to detect when the voltage difference between is below a certain value.■,? , val, , ■, may be detected based on the level of the supply voltage, and the voltage level to be detected may be varied depending on the purpose.Furthermore, the switch means 500 is composed of a P-channel MOS transistor. Although an example has been shown, any type of element may be used as long as it has other switching functions. Also, in a steady state, V□7 is va. Although 401 has been shown as an example, it is also possible to connect 401 to another voltage generated in an internal circuit whose output impedance is relatively lower than that of 400. If necessary, a resistor R may be connected in series with 500.
1°. You may also insert something like.

FIG. 19 is one of the other embodiments for preventing fluctuation of the plate electrode. In the figure, MC is an equivalent circuit of the memory cell shown in FIG. 7, D is a data line, W is a word line, QM is a switching MOS transistor, and O8 is a storage capacitor. Note that C8 is formed between 4b and 5 in FIG. 1, for example. Although only one MC is shown here, it goes without saying that a plurality of MCs are actually arranged.In the embodiment shown in FIG. Variation of the plate electrodes was prevented by reducing the equivalent impedance between them. In contrast, in this embodiment, a charge pump circuit consisting of a diode D1 and a capacitance C2° is used to reduce the equivalent impedance to the plate electrode and prevent voltage fluctuations therebetween.

That is, when the plate electrode fluctuates, the pulse φ is approximately synchronous with it. is applied to perform the charge pump operation described in FIG. 5 etc., thereby supplying charge to 401 and preventing fluctuation of the plate electrode. φ. The timing of application of is appropriately selected depending on the cause of fluctuations in the plate electrode6.For example, when the plate electrode fluctuates during sense-up operation or precharge operation due to the coupling capacitance between the data line and the plate mentioned above, is the above φ.

is applied substantially in synchronization with the sense-up operation or precharge operation or at a cycle longer than that (preferably an integer multiple). In addition to the above, the plate electrode may vary due to the coupling between the node 3a in the memory cell and the plate electrode through C6. That is, through memory read and write operations.

When the voltage at 3a fluctuates, the fluctuation is transmitted to the plate via C1, resulting in a fluctuation in the voltage at the plate electrode. Therefore, in order to suppress this fluctuation, φ is synchronized with the above-mentioned reading and writing or at a period longer than that (preferably several times more than 1). For example, address multiplex DRAM
In other words, in a DRAM that uses the same address signal input pin to input row and column address signals in synchronization with the RAS and CAS clocks, the plate electrode voltage during normal read or write operations. If fluctuation is a problem, φ in synchronization with the RAS clock. In addition, the row address can be determined by applying
If voltage fluctuations on the plate electrode become a problem during vane mode read and write operations in which only the column address is changed, φ is set in synchronization with the CAS clock. In addition, if the column address is input in the same way as static column mode to operate the static column mode, or if the voltage fluctuation of the plate electrode during write operation is a problem, the address Detects the change in the signal and outputs φ in synchronization with that signal. Just apply.

According to the embodiments described above, V X N ? It can be applied to any value of and can effectively suppress voltage fluctuations of the plate electrode. Note that in FIG. 19, the diodes D3 and D can be replaced with diodes of various shapes shown in FIG. 10. Also, depending on the case, one end may be connected to an external electrode v0° instead of 401, or may be removed. Furthermore, D4. C,c
is removed and 451 is φ. In some cases, direct driving is also possible.

In the above, embodiments have been described in which a voltage generating circuit is provided in a chip to suppress a transient current when power is turned on, or to suppress noise. These embodiments can be applied not only to the generation of the voltage applied to the plate electrode but also to the generation of the precharge voltage of the data line. A preferred embodiment for applying t will be described with reference to FIG.

In the figure, 700 is an internal voltage generation circuit that generates a data line precharge and voltage V□, and SW' is a switch for data line precharge, which is turned on during the precharge operation. This switch is usually configured as a MOS transistor.

``(B) in the same figure shows the 40% change in V□y+vop when SW' is on, that is, in the precharge operation state, and V□y+vop varies due to changes in the external power source or other reasons.
0,700 each output 401.701. The operating waveforms of the data line, node 3a in the memory cell, and word line W are shown. Here, information "O" is stored in the memory cell, and the voltage at 3a is at a low potential (≦Ov).

Also, the voltage of the word line W is Ov since it is in a precharged state -0 Note that the relative difference in voltage between each waveform has no particular meaning here, and the absolute voltage value of each waveform is Needless to say, it is a feature that can be set in various ways depending on the purpose.

Now, the external power supply 100 changes from vo to VC during time t4 to b8.
6'(< Vea), V XMTe
VDP also follows the change in vce, and each V (l C
’, the possible value V I11? ', VDP', but the following problems occur at this stage.

That is, as V□1 changes, the voltage of 3a changes in the negative direction due to capacitive coupling of C6. As a result, when the voltage of 3a decreases from ov to the threshold voltage 77 of the MOS transistor Q, since W is Qv, Q is turned on. As a result, current flows from the data line toward C8, and the voltages at D and 701 drop. This change is due to capacitive coupling, so it gradually moves toward the original voltage.

3a, 701. Both D and D return, but the return time is delayed, and if the precharge state is completed and memory operation is started during this return, a serious malfunction will occur. Also, the substrate voltage is negative V. (as shown in Fig. 3), due to the leakage current between 3a and the substrate, in the worst case, the voltage of 3a becomes the critical voltage at which Q is turned on, that is, -v1 voltage. Therefore, at the same time as ■8.7 starts to change, Q turns on, and the above problem becomes even more noticeable.
In order to solve this problem by following the changes in
It is slower than that of 0. That is, the current supply capacity IDP of 700 is increased. This current supply capacity can be selected approximately as follows.

Here, n is the number of memory cells to be taken into account when changing, and usually the number of bits of memory coalescing is selected. C1 is the storage capacity value per memory cell, ΔV□7 is V I
II? The amount of change in , At is its change time, A V
xwv/ A t is vx,? By satisfying this condition, which indicates the average amount of change per unit time, ■, P becomes V
□7, and the problem mentioned above does not occur. Furthermore, if At is extremely short, the minimum specification of the memory precharge period t, (20
~100. , degree), V D P returns to its original value V
. , ', so A in equation (7)
1 instead of t. It is sufficient to use the value of .

Various modifications can be made to this embodiment described above. For example, the value of Vote V1++t can be set variously depending on the purpose. For example, the present invention can also be applied to the previously described method in which the data line is precharged to v0c/2. In addition, 1985 (ISCC Digest of Technical Papers l5SCC Digest of Tec
VIN?, as disclosed in Hnical Papers) pp. 250-251. TV □ va. The same value of /2 can be applied as is by designing the common internal power supply capacity and formula (7). Note that the method for setting the current drive capacity differs depending on the circuit type used.
For example, when realized with a circuit as shown in FIG.
, can be set arbitrarily by the resistance value of .

In addition, when realized with a circuit as shown in Fig. 5, the capacitance C□
The driving capacity can be arbitrarily set by controlling the frequency of the oscillator osc'.

[Effects of the Invention] According to the present invention described above, problems such as excessive transient power supply current or malfunction caused by voltage fluctuations when the power is turned on or during operation can be effectively solved.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams explaining problems of the prior art, and FIGS. 3 to 20 are diagrams showing embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating film, 3a, -, 3e...
Impurity 2nd country (A) (B) CC VJJ 口 (A) (B) 11 ÷ Gin r'i'I < t) 廼 4 Figure (A) (B) -1-Chiginn 小5 figure CB ) m-54rtI □Ginniku4ρ14ρl No. 1O Figure '115II Kuchitomi IZ Figure <A) (El) -IchikiKutomi 17 Ku (A) (δ) --Chi BJtyfl Atsushi 18 Figure (A) (B) □Ginniku ′ M(.

Claims (1)

[Claims] 1. At least one or more voltage converting means for converting an external power supply voltage to another internal voltage within the chip, and at least some circuits within the chip In a semiconductor device characterized in that it operates, the time at which the internal voltage starts to change or the time required for the change when the external power supply voltage is turned on is determined by the rise (rise) of the external power supply voltage.
A semiconductor device characterized by a falling start time or a rising (or falling) time that is later or longer than the rising time. 2. A semiconductor device comprising voltage conversion means for converting an external power supply voltage to another internal voltage within the chip, and at least a part of the circuits within the chip operate based on the internal voltage, The semiconductor device has a built-in substrate voltage generating means for applying voltage to the semiconductor substrate of the chip inside the chip,
The development time of the change in the internal voltage and the substrate voltage when the external power supply voltage is turned on, or the time required for the change, is slower or longer than the change start time or the time required for the change of the external power supply voltage. semiconductor device. 3. The time at which the internal voltage starts changing or the time required for the change when the external power supply voltage is turned on is approximately the same as or slower than the time at which the substrate voltage generation means starts changing or the time required for the change. 3. The semiconductor device according to claim 2, wherein the semiconductor device is large. 4. A semiconductor device comprising voltage conversion means for converting an external power supply voltage to another internal voltage within the chip, and at least a part of the circuits within the chip operate based on the internal voltage, The voltage converting means has at least one
2. The semiconductor device according to claim 1, comprising at least one charge pump circuit and a charge pump signal generation circuit. 5. The semiconductor device according to claim 2, wherein the substrate voltage generating means comprises at least one charge pump circuit and a charge pump signal generating circuit. 6. The semiconductor device according to claim 4 or 5, wherein the charge pump signal generation circuit comprises a self-excited oscillation circuit. 7. The semiconductor device according to claim 6, wherein the self-excited oscillation circuit is shared by both the voltage conversion means and the substrate voltage generation means. 8. The semiconductor device is an information storage device, and is constituted by a memory cell group consisting of a capacitor for storing information charge and a MOS type transistor for switching, and the semiconductor device is a first 2. The semiconductor device according to claim 1, wherein the electrode group is connected to the internal voltage output from the voltage conversion means. 9. The internal voltage is supplied to the first electrode group through switching means whose opening and closing are controlled in conjunction with the operation of the semiconductor device, as set forth in claim 8. semiconductor devices. 10. The first electrode group is divided into a plurality of groups, and at least two or more groups share the switching means, and in the active state of the information storage device, at least one of the two or more groups 10. The semiconductor device according to claim 9, wherein the group is in an inactive state. 11. The semiconductor device is an information storage device, and includes a capacitor for information charges, a source (drain) electrode is one end of the electrode of the capacitor, the drain (source) electrode is a first signal line, and the gate electrode is a second signal line. An information storage device constituted by a memory cell group consisting of switching MOS transistors connected to a signal line, characterized in that the first signal line is precharged by the internal voltage output from the voltage conversion means. A semiconductor device according to claim 1. 12. The voltage conversion means is I_D_P≧n・Cs (ΔV_I_N_T/Δt), where n: the number of memory cells to be considered during fluctuation (number) Cs: the value of the storage capacity per memory cell ΔV_I_N_T: the value of V_I_N_T Amount of change Δt: ΔV
12. The semiconductor device according to claim 11, wherein the semiconductor device has a driving capability corresponding to a change time of _I_N_T. 13. The semiconductor device according to claim 12, wherein the Δt is a precharge period tp of the memory.