JPS6232826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and particularly to a memory circuit having an error correction function.

In general, semiconductor memory elements (especially dynamic M
In storage devices using S RAM, the storage capacity of the device is also increasing with the rapid increase in the degree of integration of storage elements, and the reliability of the storage device greatly influences the system reliability. Against this background, many memory devices employ memory circuits having an error correction function capable of 1-bit error correction and 2-bit error detection (hereinafter referred to as SEC-DED).
By means of this error correction function SEC-DED, most errors caused by faults in storage elements are corrected or detected. The same applies to errors caused by failures in some logic circuits surrounding the memory element, and as a result, the reliability of the memory device is greatly improved.

A conventional storage device includes a storage circuit that outputs read data and writes write data and check bits during partial writing, a parity generation circuit that generates read data parity in bytes for the read data, and a parity generation circuit that outputs read data and writes write data and check bits during partial writing. The device includes a write data selection circuit that generates the write data based on data and the read data, and an encoding circuit that generates the check bit based on the write data.

However, even if the write data that generates the check bit contains an error, the check bit generated using this write data as is is normal for that data, so if this write data and the check bit are written. If read later, it will not contain any errors, and this error correction function SEC
-DED cannot detect errors.

A conventional storage device will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional storage device, which has an error correction function SEC-DED and a partial write function. It is composed of a decoding circuit 4, an error correction circuit 5, and a parity generation circuit 6.

In a write or partial write operation, write data (including the case of rewrite data) generated by the write data selection circuit 1 and check bits generated by the encoding circuit 2 are transferred to the storage circuit 3. will be written to.

Even if an error (particularly a 1-bit error) occurs in the write data output from the write data selection circuit 1, the check bit written in the memory circuit 3 is normal with respect to the write data.

Therefore, even if the write data and check bits containing errors written from the memory circuit 3 are read as read data and checked by the decoding circuit 4, no errors can be detected, and the read data containing errors is not detected by the error correction circuit. The parity generation circuit 6 generates a read data parity bit for the data.

Such a conventional storage device sends read data output from the error correction circuit 5 and read data parity bits generated by the parity generation circuit 6 to the central processing unit. At this time, since a predetermined correct parity bit is added to the read data that should be erroneous, the central processing unit cannot detect the error. As a result, so-called "data garbled"
occurs and the system goes down.

As explained above, conventional storage devices do not check the normality of write data (including rewrite data) that generates check bits during write or partial write operations. It has the disadvantage that the problems mentioned above occur.

That is, conventional storage devices have the disadvantage that data garbled occurs during partial writing.

An object of the present invention is to provide a storage device that does not cause data corruption even during partial writing.

That is, an object of the present invention is to provide write data with parity bits added to a selection circuit that generates write data (including rewrite data) during a write or partial write operation in order to improve the above-mentioned drawbacks. By inputting read data and performing a parity check on the generated write data (or rewrite data), it detects odd bit failure errors, and uses the error signal to detect errors in erroneous data. An object of the present invention is to provide a storage device that protects storage contents by controlling data so that it is not written into a storage circuit as if it were normal data.

The memory circuit of the present invention is based on a memory circuit that outputs read data during partial writing, a parity generation circuit that generates read data parity in units of bytes for the read data, and the partial write data and the read data. a write data selection circuit that generates write data based on the write data; an encoding circuit that generates check bits based on the write data; and write data parity bits and read data parity bits supplied from the central processing unit. a parity selection circuit that selects one of the above and outputs it as a data parity bit; and a parity selection circuit that performs a parity check using the write data and the data parity bit, and when an error is detected, writes the write data and the data to the storage circuit. and an error detection circuit that generates an error detection signal for inhibiting writing to the check bit.

That is, the memory device of the present invention has a memory circuit that has a partial write function and is made up of semiconductor memory elements, a parity generation circuit that generates parity bits in bytes for data read from the memory circuit, and a parity generation circuit that generates parity bits for data read from the memory circuit. a parity selection circuit which receives as input a write data parity bit from a central processing unit which is stored in the storage circuit and a read data parity bit which is an output of the parity generation circuit, and selects a parity bit for data to be written to the storage circuit; and an error detection circuit that performs a parity check using write data to a storage circuit and an output of the parity selection circuit, and the error detection circuit detects an error in a write operation and a partial write operation. In this case, writing to the memory circuit is prohibited to protect the memory contents.

That is, when selecting data to be written or rewritten to a memory circuit composed of semiconductor memory elements, the memory device of the present invention selects write data from the central processing unit with a parity bit added and data from the memory circuit. It has a means for inputting and selecting read data, and an error detection means for performing a parity check using the selected write data or rewrite data and parity bits, and the error detection means performs a parity check in a write or partial write operation. If an error is detected by the means, the storage contents are protected by controlling to prohibit writing to the storage circuit.

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 2 is a block diagram of a storage device showing an embodiment of the present invention, including a write data selection circuit 1, an encoding circuit 2, a storage circuit 3, a decoding circuit 4, an error correction circuit 5, and a parity generation circuit 6. , a parity correction circuit 7, a parity selection circuit 8, and an error detection circuit 9, and has an error correction function SEC-
Has DED and partial write functions.

The functions of each block in the embodiment shown in FIG. 2 are as follows.

The write data selection circuit 1 includes a flip-flop F/F that holds write data from the central processing unit CPU.
This circuit receives the output of F and the output of the error correction circuit 5 as inputs and selects data to be written to the memory circuit 3. The encoding circuit 2 is a circuit for generating check bits to be written into the memory circuit 3 using the output of the write data selection circuit 1. The memory circuit 3 is a circuit for storing and holding the write data and check bits in response to a write signal from a control circuit (not shown in the drawing). The decoding circuit 4 is the storage circuit 3
This is a circuit for generating error detection and error correction signals using read data and check bits from. The error correction circuit 5 is a circuit for correcting the read data using an error correction signal from the decoding circuit 4. The parity generation circuit 6 is a circuit for generating parity bits for each byte of the read data. The parity correction circuit 7 is a circuit for correcting the read data parity bit using the parity correction signal from the decoding circuit 4. The parity selection circuit 8 inputs the output of the flip-flop F/F that holds the write data parity bit from the central processing unit CPU and the read data parity bit from the parity correction circuit 7, and selects the parity bit to be sent to the error detection circuit 9. This is a circuit for The error detection circuit 9 performs error detection using the write data from the write data selection circuit 1 and the parity bit selected by the parity selection circuit 8, and sends an error signal to the control circuit.

The operation of the storage device shown in FIG. 2 will be explained below.

When performing a write operation, the write data selection circuit 1 selects write data from the central processing unit CPU,
Using this data, the encoding circuit 2 generates check bits. In parallel with check bit generation,
Central processing unit selected by parity selection circuit 8
The write data parity bit from the CPU and the write data are input, and an error detection circuit 9 performs a parity check for each byte. If there is no error, the write data and check bit are written into the memory circuit 3 by a write signal from the control circuit.
If an odd bit error is detected, an error detection signal is sent from the error detection circuit 9 to the control circuit, and writing signals to the memory circuit 3 are inhibited to protect the stored contents.

When performing a read operation, the stored contents (data and check bits) of the memory circuit 3 are read out in response to a read signal from the control circuit, and the read data and check bits are used for inspection by the decoding circuit 4. In parallel with this, the parity generation circuit 6 generates read data parity bits for each byte of the read data. When a 1-bit error is detected in the decoding circuit 4, an error bit indication signal is sent to the correction circuit 5, and corrected read data is output. Further, the parity correction signal of the byte containing the error bit is sent to the parity correction circuit 7, and the read data parity bit of the corresponding byte is inverted. Furthermore, when there is no error or when there is a 2-bit error, the read data from the storage circuit 3 and the read data parity bit from the parity generation circuit 6 are sent to the central processing unit CPU via the error correction circuit 5 and the parity correction circuit 7. Sent out.

Next, when performing a partial write operation, the corrected read data and read data parity bits obtained in the same manner as in the read operation described above are input to the write data selection circuit 1 and the parity selection circuit 8, and the central From the write data from the processing unit CPU and the data from the flip-flop F/F that holds the write data parity bit, the rewrite data and its data are generated by the byte position designation signal that specifies the partial write byte. The parity bit for is selected. Using this rewrite data and parity bits, the encoding circuit 2 generates check bits, and the error detection circuit 9 performs a parity check for each byte, in the same way as described in the write operation above.

Therefore, even in a partial write operation, if an odd bit error is detected in any byte, the memory circuit 3
Protects the memory contents by prohibiting write signals to the memory.

Below, the conventional example shown in FIG. 1 and the embodiment of the present invention shown in FIG. 2 will be compared.

In the configuration of a conventional storage device as shown in FIG. 1, the normality check for write data that generates check bits is not performed, and even erroneous write data is treated as normal write data in the memory circuit. As a result, so-called "garbled data" occurs.

However, as is clear from the above explanation, in the configuration of the present invention, a byte-based parity check is performed on write data that generates check bits, so if an error is detected, writing is prohibited and the stored contents are can be protected.

However, although even-numbered bit errors within each byte cannot be detected, the probability of this type of failure occurring is high due to a one-bit error, and the effects of the present invention are considered to be sufficient for practical use.

By adding an error detection circuit to the storage device of the present invention, when an error occurs in the written data, it is possible to generate an error detection signal and prohibit writing of the written data, so that data corruption can be prevented. There is.

That is, the memory circuit of the present invention protects the memory contents by providing an error detection circuit for write data that is input to the encoding circuit, and prohibiting writing to the memory circuit when an error is detected. death,
This has the effect of reducing the occurrence of "data corruption."

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional storage device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...Write data selection circuit, 2...Encoding circuit, 3...Storage circuit, 4...Decoding circuit, 5...
Error correction circuit, 6... Parity generation circuit, 7...
Parity correction circuit, 8... Parity selection circuit, 9
...Error detection circuit.

Claims (1)

[Claims] 1. A memory circuit that outputs read data during partial writing, a parity generation circuit that generates read data parity in byte units for the read data, and a parity generation circuit that generates write data based on the partial write data and the read data. a write data selection circuit to generate a check bit; an encoding circuit to generate a check bit based on the write data; and a write data parity bit supplied from the central processing unit or the read data parity bit. a parity selection circuit that selects and outputs the data parity bit as a data parity bit; and a parity check circuit that performs a parity check using the write data and the data parity bit, and writes the write data and the check bit to the storage circuit when an error is detected. and an error detection circuit that generates an error detection signal for inhibiting.