JPS62293772A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62293772A JPS62293772A JP13761386A JP13761386A JPS62293772A JP S62293772 A JPS62293772 A JP S62293772A JP 13761386 A JP13761386 A JP 13761386A JP 13761386 A JP13761386 A JP 13761386A JP S62293772 A JPS62293772 A JP S62293772A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- gate electrode
- oxide film
- gate
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 10
- 238000002844 melting Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 abstract description 20
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 239000000463 material Substances 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- 238000001020 plasma etching Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】 五 発明の詳細な説明 〔産業上の利用分野〕 本発明はＭＯＳ型半導体装置の構造に関する。[Detailed description of the invention] V. Detailed description of the invention [Industrial application field] The present invention relates to the structure of a MOS type semiconductor device.
本発明け、ＭＯＳ型半導体装置の構造においてゲート電
極の側壁に高融点金属のケイ化物（以下シリサイドと略
記）を設けることにより、ゲート配線材料の低抵抗化と
ゲート材料の薄膜化を同時に行い、段差の低減をばかろ
ことで、上層配線材料のｎ線を防ぐとい５効果を提供し
たものである。According to the present invention, by providing a refractory metal silicide (hereinafter abbreviated as silicide) on the side wall of the gate electrode in the structure of a MOS type semiconductor device, the resistance of the gate wiring material and the thickness of the gate material can be reduced at the same time. By not only reducing the level difference, but also preventing n-line radiation from the upper layer wiring material, this provides five effects.
従来のＭＯＳ型半導体装置、％Ｋｙ型の構造ｎ面図を算
２図に示す。同図において２０１け一導電型半導体基板
、２Ｑ２１ｄ素子分離用酸化模、２０３けゲート酸化膜
、２０４は多結晶シリコン、２０５け高融点金属ケイ化
物、２０６け酸化膜サイドウオール、２０７け低濃度不
純物拡散層、２０８は高濃度不純物拡散層、２０９け眉
間絶縁用酸化膜、２１０け配線材料用ｄである。An n-plane view of the structure of a conventional MOS type semiconductor device, %Ky type, is shown in Figure 2. In the same figure, 201 is a single conductivity type semiconductor substrate, 2Q21d is an oxide pattern for element isolation, 203 is a gate oxide film, 204 is a polycrystalline silicon, 205 is a high melting point metal silicide, 206 is a silicon oxide film side wall, and 207 is a low concentration impurity. Diffusion layer 208 is a high concentration impurity diffusion layer, 209 is an oxide film for insulation between the eyebrows, and 210 is for wiring material.
しかし、上述の従来技術では、ゲート１！極が多結晶シ
リコン及び金属ケイ化物の二層構造であるため大きな段
差ｈ；生じ、そのため上層のａがａｌしやすいとい５欠
点ｂ’−あった。However, in the prior art described above, gate 1! Since the electrode has a two-layer structure of polycrystalline silicon and metal silicide, a large step h; is generated, and therefore, the upper layer a tends to be alkalized.
そこで本発明はこのような問題点を解決するもので、そ
の目的とすることは、多結晶シリコンの側壁に高融点金
属ケイ化物を設けることでより、段差の低減と、ゲート
配線材料の低抵抗化を同時に満たしうる半導体装置の構
造を提供することにある。The present invention aims to solve these problems, and its purpose is to reduce the level difference and reduce the resistance of the gate wiring material by providing a high melting point metal silicide on the sidewalls of polycrystalline silicon. An object of the present invention is to provide a structure of a semiconductor device that can simultaneously satisfy the following requirements.
本発明の半導体装置け、多結晶シリコンゲート電極ｈｔ
側壁に高融点金属ケイ化物を有することを特徴とする。Semiconductor device of the present invention, polycrystalline silicon gate electrode ht
It is characterized by having a high melting point metal silicide on the side wall.
以下図面により詳細に説明する。 This will be explained in detail below with reference to the drawings.
第１図れ）は本発明の半導体装置の構造、第１図の）は
製造方法をあられす断面図であり、工程を追って説明す
る。FIG. 1) is a cross-sectional view showing the structure of the semiconductor device of the present invention, and FIG. 1) is a cross-sectional view showing the manufacturing method, and the steps will be explained step by step.
工程（１）第１図（ｂ） −１
Ｐ型半導体基板１０１上に素子分離用酸化膜１０２を形
成した後、ゲート酸化ｉｌｌ １０３を熱酸化法で１５
０〜２００λ形成し、その上だ多結晶シリコンを１００
０〜２０００人化学的気相成長法で形成し、８００〜１
０００℃でリンを熱拡散する。次忙レジストパターンを
マスクに前記多結晶シリコンをエツチングし、ゲート電
極１０４を形成しに後、低濃度リンのイオン注入を行い
Ｎ型低濃度拡散層１０５を形成する。Step (1) FIG. 1(b) -1 After forming an oxide film 102 for element isolation on a P-type semiconductor substrate 101, a gate oxide ill 103 is formed using a thermal oxidation method.
0 to 200λ is formed, and then polycrystalline silicon is deposited on top of 100λ.
0-2000 people Formed by chemical vapor deposition method, 800-1
Thermal diffusion of phosphorus is carried out at 000°C. The polycrystalline silicon is etched using the busy resist pattern as a mask to form a gate electrode 104, and then low concentration phosphorus ions are implanted to form an N type low concentration diffusion layer 105.
工程（２） 笹１図の）−２
スパッタ法により高融点金属ケイ化物を１０００〜２０
００Ａ全面に形成する。Step (2) Bamboo shoots (Fig. 1)-2 Sputtering high melting point metal silicide to 1000 to 20%
Formed on the entire surface of 00A.
工程（３） ｆｉｔ １図（ｂ）−３リアクテイブイ
オンで全面をエツチングすることにより、ゲート電極の
側壁部の入に高融点金属ケイ化物の側壁（以下シリナイ
ドサイドウオールと記す）１０７が形成される！次に９
００〜１０００’Ｃの酸素雰囲気中で７二−ルを行う。Step (3) fit 1 Figure (b)-3 By etching the entire surface with reactive ions, a high melting point metal silicide sidewall (hereinafter referred to as silicide sidewall) 107 is formed at the entrance of the sidewall of the gate electrode. It will be done! Next 9
A 7-year reaction is carried out in an oxygen atmosphere at 00-1000'C.
その後、高濃度リンのイオン注入を行いＮ型高濃度拡散
層１０８を形成する。Thereafter, high concentration phosphorus ions are implanted to form an N-type high concentration diffusion layer 108.
工程（４）第１図の）−４
熱アニールを行い前記ｙ型低濃度拡散１１１０５及び、
Ｎｍ、高濃度拡散層１０８を活性し次後、層間絶縁用酸
化膜１０９を化学的気相成長法で４０００〜６０００λ
形成し、レジストパターンをマスクに前記層間絶縁用酸
化膜１０９をエツチングし、コンタクトホールを形成し
比後配線材料用Ａ／： １１０を形成する。Step (4) in FIG. 1)-4 Thermal annealing is performed to remove the y-type low concentration diffusion 11105 and
After activating the high concentration diffusion layer 108, an oxide film 109 for interlayer insulation is formed with a thickness of 4000 to 6000λ by chemical vapor deposition.
Then, using the resist pattern as a mask, the interlayer insulating oxide film 109 is etched to form a contact hole, and then a wiring material A/: 110 is formed.
以上述べたように、木発ｅＡＫよればゲート配線材料は
側壁のシリサイドにより低抵抗化がはかられるｔめ、従
来のようなゲート電極による段差はかなり低減される。As described above, according to the Kihoku eAK, the resistance of the gate wiring material is lowered by the silicide on the side walls, so the step difference caused by the gate electrode as in the conventional method is considerably reduced.
これにより上層配線の断線の発生ｈ；おさ先られるとい
う効果を有する。This has the effect of preventing the occurrence of disconnection in the upper layer wiring.
さらに従来の２ＤＤｐ造をもつトランジスタ製造工程に
比較し、工程を削減できるという効果も有する。Furthermore, it has the effect of reducing the number of steps compared to the conventional 2DDp transistor manufacturing process.
第１図れ）は本発明の半導体装置の構造を表わす断面図
、１１１１図（ｂ）の（１）〜（４）Ｆ′ｉその製造方
法を表わす主要ｌ！Ｆ１面図。
第２図は、従来の半導体装置の構造を表わす断面図。
１０１・・・・・・Ｐ型半導体基板
１０２・・・・・・素子分離用酸化膜
１０３・・・・・・ゲート酸化膜
１０４・−・・・・ゲート１！極
１０５・・・・・・Ｎ型低濃度拡散層
１０６・・・・・・高融点金属ケイ化物１０７・・・・
・・シリナイドサイドウオール１０８・・・・・・Ｎ型
高濃度拡散層
１０９・・・・・・層間絶縁用酸化膜
１１０・・・・・・配線材料用ａ
２０１・・・・・・Ｐ型半導体基板
２０２・・・・・・素子分離用酸化膜
２０３・・・・・・ゲート酸化膜
２０４・・・・・・ゲート電極算１層（多結晶シリコン
）２０５・・・・・・ゲート１！甑第２層（高融点金属
ケイ化物）２０６・・・・・・酸化膜サイドウオール２
０７・・・・・・Ｎ型低濃度不純物拡散層２０８・・・
・・・Ｎ型高濃度不純物拡散屡２０９・・・・・・層間
絶縁用酸化膜
２１０・・・・・・配線材料用ａ
以 上
出願人 セイコーエプソン株式会社
Ｘ１ｏｌ
（１ン ７゜７
す０
第１図（ｂ）FIG. 1) is a cross-sectional view showing the structure of the semiconductor device of the present invention, and (1) to (4) F'i in FIG. F1 view. FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device. 101...P-type semiconductor substrate 102...Element isolation oxide film 103...Gate oxide film 104...Gate 1! Pole 105...N-type low concentration diffusion layer 106...High melting point metal silicide 107...
... Silinide sidewall 108 ... N-type high concentration diffusion layer 109 ... Oxide film for interlayer insulation 110 ... Wiring material a 201 ... P Type semiconductor substrate 202...Element isolation oxide film 203...Gate oxide film 204...Gate electrode total 1 layer (polycrystalline silicon) 205...Gate 1! Second layer (high melting point metal silicide) 206... Oxide film side wall 2
07... N-type low concentration impurity diffusion layer 208...
...N-type high concentration impurity diffusion layer 209...Oxide film for interlayer insulation 210...For wiring material a Applicant: Seiko Epson Corporation Figure 1(b)
Claims (1)
体装置において、前記多結晶シリコンゲート電極が側壁
に高融点金属ケイ化物を有することを特徴とする半導体
装置。1. A MOS semiconductor device using polycrystalline silicon as a gate electrode, wherein the polycrystalline silicon gate electrode has a high melting point metal silicide on its sidewalls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13761386A JPS62293772A (en) | 1986-06-13 | 1986-06-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13761386A JPS62293772A (en) | 1986-06-13 | 1986-06-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62293772A true JPS62293772A (en) | 1987-12-21 |
Family
ID=15202772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13761386A Pending JPS62293772A (en) | 1986-06-13 | 1986-06-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62293772A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63115377A (en) * | 1986-11-04 | 1988-05-19 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5023679A (en) * | 1988-06-30 | 1991-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US5031008A (en) * | 1989-03-10 | 1991-07-09 | Kabushiki Kaisha Toshiba | MOSFET transistor |
| KR20000073372A (en) * | 1999-05-10 | 2000-12-05 | 김영환 | Fabricating method of semiconductor device |
-
1986
- 1986-06-13 JP JP13761386A patent/JPS62293772A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63115377A (en) * | 1986-11-04 | 1988-05-19 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5023679A (en) * | 1988-06-30 | 1991-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US5031008A (en) * | 1989-03-10 | 1991-07-09 | Kabushiki Kaisha Toshiba | MOSFET transistor |
| KR20000073372A (en) * | 1999-05-10 | 2000-12-05 | 김영환 | Fabricating method of semiconductor device |
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