JPS622485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic type D flip-flop circuit operated by a single-phase pulse signal. The device shown in FIG. 1 operates using a two-phase pulse signal of φ. 2 is a configuration diagram of a conventional two-phase dynamic type D flip-flop circuit, and FIG. 2 is a timing chart showing its operation. In the figure, two P-channel MOS transistors 1, 2 and 2
Two N-channel MOS transistors 3 and 4 constitute a clocked inverter 5 , and two P-channel MOS transistors 6 and 7 and two N-channel MOS transistors constitute a clocked inverter 5.
Channel MOS transistors 8 and 9 constitute a clocked inverter 10 . The input signal IN is supplied to one clocked inverter 5 , and the output signal A of this clocked inverter 5 is supplied to the other clocked inverter 10 . Also, in the figure, a P channel MOS transistor 11 and an N channel MOS transistor 1
2 constitutes an inverter 13 for obtaining a pulse signal from the input clock signal CLOCK, and this pulse signal is transmitted to the MOS transistors 4 and 6.
supplied to each gate. Furthermore, the P channel MOS transistor 14 and the N channel MOS transistor 15 are connected to an inverter 16 for obtaining a pulse signal φ that is 180° out of phase with the above pulse signal.
This pulse signal φ is connected to the above MOS
It is supplied to the gates of transistors 1 and 9, respectively. Conventional dynamic type D configured in this way
In a flip-flop circuit, from a low level (ground level) to a high level ( _VDD level),
t ₁ when φ flips from high level to low level, respectively
When the input signal IN is inverted from a low level to a high level at the timing of , the output signal OUT is inverted from a low level to a high level after this or at a timing of _t2 delayed by half a bit of φ, and then the output signal OUT is inverted from a low level to a high level. When the input signal IN is inverted from high level to low level at timing _t3 when φ is inverted from high level to low level, the output signal OUT is output after this or at timing _t3 delayed by half a bit of φ. is reversed from high level to low level. In this way, when the input signal IN changes in synchronization with the rise of and the fall of φ, the output signal OUT becomes a half-bit delayed signal with respect to the input signal IN or φ. When the input signal IN is inverted from low level to high level at timing _t4 , when 0 is inverted from high level to low level and φ is inverted from low level to high level, the input signal IN is inverted from low level to high level after this or by one bit of φ.
At timing t ₅ , the output signal OUT is inverted from low level to high level, and at timing t ₆ , when φ is inverted from high level to low level and from low level to high level, input signal IN is inverted from high level to high level. When it is inverted to low level, the output signal is output after this or at timing _t7 delayed by 1 bit of φ.
OUT flips from high level to low level. In this way, when the input signal IN changes in synchronization with the falling of and rising of φ, the output signal OUT
becomes a 1-bit delayed signal with respect to the input signal IN or φ. Therefore, the above circuit operates as a D flip-flop circuit. By the way, the above circuit requires two pulse signals, φ and φ, and they must be out of phase by 180° from φ. However, since the number of inverter stages that obtain φ is different, it is difficult to accurately shift the phase with φ by 180° due to the inverter delay time, which may cause circuit malfunction or unstable operation. Become. This phenomenon becomes more significant as the frequency of the input clock signal CLOCK increases. For example, as shown by the broken line in FIG. 2, when φ is delayed, a state occurs in which both φ and φ become low level at timing _t6 , and MOS transistors 1 and 2 are both turned on and the signal A is turned on. is at a high level. After this φ
When OUT is delayed and inverted to a high level, both MOS transistors 8 and 9 are turned on, and the output signal OUT becomes a low level, resulting in malfunction. This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a dynamic D flip-flop circuit that does not malfunction even when operated at high frequencies and can always operate stably. It is about providing. Embodiments of the present invention will be described below with reference to the drawings. Figure 3 shows the dynamic type D according to this invention.
1 is a circuit configuration diagram of a first embodiment of a flip-flop circuit, and this circuit is composed of first, second, and third units 21 , 22 , and 23. FIG. In the first unit 21 , two P-channel MOS transistors are connected between the positive potential V _DD supply point and the reference potential GND supply point.
Transistors 24, 25 and two N-channels
MOS transistors 26 and 27 are inserted in series in this order, and an N-channel MOS transistor 28 is connected in parallel to the N-channel MOS transistor 27.
The series connection point with the channel MOS transistor 26 is used as the output end. Further, the second unit body 22
Then, there are two P channel MOS between V _DD and GND.
Transistors 29, 30 and two N-channels
MOS transistors 31 and 32 are inserted in series in this order, and the series connection point between P channel MOS transistor 30 and N channel MOS transistor 31 is used as an output end. Furthermore, the third unit 23
Now, there are two P channels between V _DD and GND.
MOS transistors 33, 34 and one N-channel MOS transistor 35 are inserted in series in this order, and the series connection point between P-channel MOS transistor 34 and N-channel MOS transistor 35 is used as an output end. The input signal D is then supplied to each gate of the P channel MOS transistor 25 and the N channel MOS transistor 26. Further, the signal A at the output end of the first unit 21 is supplied to each gate of the P channel MOS transistor 30 and the N channel MOS transistor 31. Further, the second unit 22
A signal B at the output terminal of is supplied to each gate of the P-channel MOS transistor 34 and the N-channel MOS transistor 28, and is output to the outside. Furthermore, the signal C at the output end of the third unit 23 is applied to the N-channel MOS transistor 27 and the P-channel MOS transistor 2.
9 gates. Further, the one-phase pulse signal φ is applied to the P channel MOS transistor 24,
N-channel MOS transistor 32, P-channel
It is supplied to each gate of MOS transistor 33 and N-channel MOS transistor 35. Next, the operation of the circuit configured as described above will be explained in the fourth section.
This will be explained using the timing chart shown in the figure.
First, when φ is low level (GND level), the input signal D
At the timing of t ₁ when is at a low level,
Both MOS transistors 24 and 25 turn on,
Signal A becomes high level ( _VDD level). When φ flips to high level at timing t ₂ ,
The MOS transistor 35 is turned on and the signal C becomes low level. At this time, the MOS transistor 24 to which φ, which is at a high level, is input is turned off, and the MOS transistor 26 to which the input signal D, which is still at a low level, is input is also turned off, so that the output terminal of the unit 21 is V _DD and GND, and signal A is held at its previous high level state. When signal A is held high, the MOS
The transistor 31 is turned on, and the MOS transistor 32 to which φ, which is at a high level at this time, is input
Since the output signal is also turned on, the signal B, that is, the output signal, becomes low level. At timing _t3 , φ is again inverted to low level and input signal D is inverted to high level. When φ is inverted and becomes low level, MOS transistor 3
3 turns on. If the signal B is held at a low level at this time, the MOS transistor 34
is also turned on, so the signal C is inverted to high level.
When the signal C is inverted and becomes high level, the MOS transistor 27 is turned on. At this time, the input signal D is also at a high level, so the MOS transistor 26
is also turned on, and signal A is inverted to low level. Signal A
When the signal is inverted and becomes a low level, the MOS transistor 31 is turned off. At this time, the MOS transistor 29 to which the signal C, which is at a high level, is input is also turned off, and the signal B is maintained at the previous low level state as described above. When φ flips to high level at timing t ₄ ,
The MOS transistor 35 is turned on and the signal C is inverted to low level. When the signal C is inverted and becomes a low level, the MOS transistor 29 is turned on. If signal A is still at a low level at this time, then
Since the MOS transistor 30 is also turned on, the signal B
is reversed to high level. Further, when the signal B is inverted and becomes high level, the MOS transistor 28 is turned on. At this time, since the MOS transistor 26 to which the input signal D, which is at a high level, is input is also turned on, the signal A remains at the low level as described above. At timing _t5 , φ is inverted to a low level and the input signal D is inverted to a low level. When φ is inverted and becomes a low level, the MOS transistor 35 is turned off. If the signal B is held at a high level at this time, the MOS transistor 34 is also turned off, and the signal C is held at its previous low level. Furthermore, when φ becomes a low level, the MOS transistor 24 is turned on, and the MOS transistor 2 to which the input signal D, which is at a low level at this time, is input.
5 is also turned on, so the signal A is inverted to high level. When the signal A is inverted and becomes high level, the MOS transistor 30 is turned off. MOS transistor 32 to which φ, which is at a low level at this time, is input
Since the signal B is also turned off, the signal B remains at a high level. When φ flips to high level at timing t ₆ ,
The MOS transistor 35 is turned on and the signal C becomes low level. At this time, the MOS transistor 26 to which the input signal D, which is at a low level, is input is turned off, and the MOS transistor 26, which is at a high level, is input to the MOS transistor 26.
Since the transistor 24 is also turned off, the signal A is maintained at the high level state. When signal A is held at a high level, MOS transistor 31 is turned on. At this time, the MOS transistor 32 to which φ, which has reached a high level, is input is also turned on, so that the signal B is inverted to a low level. When the input signal D changes in synchronization with the fall of φ in this manner, the signal B, that is, the output signal becomes a half-bit delayed signal of φ with respect to the input signal D. Furthermore, the input signal D is inverted to high level at the timing _t7 when φ is inverted to high level. At this timing, if φ is reversed and becomes high level, the MOS
Transistor 35 turns on and signal C is inverted to low level. When signal C is inverted and becomes low level
MOS transistor 27 is turned off. At this time, the MOS transistor 24 to which φ, which is at a high level, is input is also turned off. Furthermore, if the signal B is at a low level at this time, the MOS transistor 28 is also turned off, so that the signal A is held at the previous high level state. If the signal A is held at a high level, the MOS transistor 31 is turned on.
At this time, φ, which is at a high level, is input.
MOS transistor 32 is also turned on, and signal B becomes low level. Next, when φ is inverted to a low level at timing _t8 , the MOS transistor 33 is turned on. If signal B is held at a low level at this time, then
The MOS transistor 34 is also turned on, and the signal C is inverted to high level. When the signal C is inverted and becomes high level, the MOS transistor 27 is turned on. At this time, input signal D, which is at a high level, is input.
Since the MOS transistor 26 is also turned on, the signal A
is inverted to low level. When the signal A is inverted and becomes a low level, the MOS transistor 31 is turned off.
At this time, signal C, which is at a high level, is input.
The MOS transistor 29 is also turned off, and the signal B is kept at the previous low level state. When φ is again inverted to a high level at timing _t9 , the MOS transistor 35 is turned on, and the signal C is inverted to a low level. When the signal C is inverted and becomes a low level, the MOS transistor 29 is turned on. At this time, if the signal A is at a low level, the MOS transistor 30 is also turned on, and the signal B is inverted to a high level. When signal B is inverted and becomes high level, MOS
Transistor 28 turns on. At this time, since the MOS transistor 26 to which the input signal D, which is still at a high level, is input is also turned on, the signal A remains at a low level. When φ is reversed to a low level at timing _t10 , the MOS transistor 35, which had been on, turns off, and the MOS transistor 33, which had been off, turns on, but if signal B remains at a high level, For example, the MOS transistor 34 is turned off,
Signal C is held in a low level state. If the signal C is maintained at a low level, the MOS transistor 29 is turned on. At this time, if the signal A remains at a low level, the MOS transistor 30
is also turned on, and signal B becomes high level. If signal B is at a high level, MOS transistor 28 is turned on. At this time, since the input signal D is still at a high level, the MOS transistor 26 is also turned on, and the signal A becomes a low level. Therefore, no level change of each signal occurs at the timing _t10 . Next, at timing _t11 , φ is inverted to high level, and the input signal D is inverted to low level.
When φ is inverted and becomes a high level, the MOS transistor 35 is turned on and the signal C becomes a low level. Since the signal C is at a low level, the MOS transistor 29 remains on. If the signal A is held at a low level at this time, the MOS transistor 30 also remains on, and the signal B also remains at a high level. Therefore, MOS transistor 2
8 will also remain on, but input signal D has been inverted to low level, so it was on until now.
The MOS transistor 26 is turned off, and conversely, the MOS transistor 25, which had been off until now, is turned on. However, the MOS transistor 24 to which φ, which is at a high level, is input is turned off, so the signal A remains at its low level state. is maintained. When φ is reversed to low level at timing t ₁₂ ,
MOS transistor 24 is turned on. At this time, since the input signal D is at a low level, the MOS transistor 25 is also turned on, and the signal A is inverted to a high level. When signal A is inverted and becomes high level, MOS
Transistor 30 is turned off. MOS transistor 3 to which φ, which is at a low level at this time, is input
Since signal B is also turned off, signal B is held at its high level. If signal B is held at a high level, MOS transistor 34 is turned off. At this time, φ, which is at a low level, is input.
Since the MOS transistor 35 is also turned off, the signal C
remains at its current low level. When φ flips to high level at timing _t13 ,
The MOS transistor 35 is turned on and the signal C becomes low level. Furthermore, when φ becomes a high level, the MOS transistor 24 is turned off, and the MOS transistor 26 to which the input signal D, which is at a low level at this time, is input is also turned off, so that the signal A is maintained at its previous high level state. . If signal A is held at high level, MOS transistor 31
turns on. At this time, since the MOS transistor 32 to which φ, which is at a high level, is input is also turned on, the signal B is inverted to a low level. When the input signal D changes in synchronization with the rise of φ in this way, the signal B, that is, the output signal becomes a 1-bit delayed signal of φ with respect to the input signal D.
Therefore, the circuit of the above embodiment has D as well as the conventional circuit.
It will operate as a flip-flop circuit. Furthermore, since it uses a single-phase pulse signal φ, there is no need to consider the phase difference between φ and φ, unlike conventional circuits, and it is possible to operate stably up to extremely high frequencies without causing malfunctions. It is effective. Incidentally, in the first embodiment circuit shown in FIG . The N-channel MOS transistor 28, whose gate is supplied with the signal B, can be omitted. In addition, FIG. 5 shows the above MOS transistor 28.
This is a timing chart showing the operation when omitted. FIG. 6 is a circuit diagram of a second embodiment of the invention. This second embodiment circuit has a reset function added to the first embodiment circuit shown in FIG. 3 above. In order to provide this reset function, a P channel is connected between the output terminal of the unit 21 and _VDD .
A MOS transistor 36 is inserted in parallel and this output terminal is connected to the N-channel MOS transistor 26.
An N channel MOS transistor 37 is inserted in series between the P channel MOS transistor 29 and _VDD , and a P channel MOS transistor 38 is inserted between the P channel MOS transistor 29 and VDD.
are inserted in series, and an N-channel MOS transistor 39 is inserted in parallel between the output end of the unit 22 and GND, and a reset signal that becomes high level at reset is applied to each gate of the MOS transistors 38 and 39.
RESET is supplied, and an inverted signal of the reset signal by an inverter 40 is supplied to each gate of the MOS transistors 36 and 37. In such a configuration, the reset signal RESET
When is at a low level, that is, when no reset is applied, MOS transistors 37 and 38 are turned on and MOS transistors 36 and 39 are turned off, so that this circuit operates normally. Furthermore, when the reset signal RESET becomes high level and a reset is applied, the MOS transistors 36 and 39
is turned on, signal B is forced to a low level, and signal A is forced to a high level. FIG. 7 is a circuit diagram of a third embodiment of the present invention. This third embodiment circuit has a set function added to the first embodiment circuit shown in FIG. 3 above. In order to provide this set function, a P channel MOS transistor 41 is connected between the output end of the unit 21 and the P channel MOS transistor 25.
are inserted in series, and an N-channel MOS transistor 42 is inserted in parallel between this output terminal and GND, and a P-channel MOS transistor 43 is inserted in parallel between the output terminal of the unit 22 and _VDD . N between transistor 32 and GND
Channel MOS transistor 44 is inserted in series,
A set signal SET, which becomes high level when set, is supplied to each gate of the MOS transistors 41 and 42, and an inverted signal of the set signal from an inverter 45 is supplied to each gate of the MOS transistors 43 and 44. . In such a configuration, when the set signal SET is at a low level, that is, when no set is applied, the MOS transistors 41 and 44 are turned on.
Since MOS transistors 42 and 43 are turned off,
This circuit will operate normally. Also, when the set signal SET goes high and the set is applied, the MOS transistors 42 and 43 turn on,
Signal B is forced to a high level, and signal A is forced to a low level. FIG. 8 is a circuit diagram of a fourth embodiment of the present invention. This fourth embodiment circuit combines the circuits shown in FIG. 6 and FIG.
This circuit has a reset function and a set function added to the circuit of the first embodiment shown in the figure.
When both SET and reset signal RESET become high level, MOS transistors 36 and 3
9 is turned on, signal B is forcibly set to low level, and signal A is forcibly set to high level. Therefore, in this case, priority is given to reset. FIG. 9 is a circuit diagram of a fifth embodiment of the present invention. This fifth embodiment circuit shows another example in which a reset function and a set function are added to the first embodiment circuit shown in FIG. 3 above. In order to have this reset function and set function,
A P-channel MOS transistor 46 is inserted in series between the P-channel MOS transistor 24 and _VDD , and a P-channel MOS transistor 47 is inserted between this P-channel MOS transistor 46 and the output end of the unit 21 . and N
An N-channel MOS transistor 48 is inserted in series between the channel MOS transistor 26, and an N-channel MOS transistor 49 is inserted in parallel between the output terminal of the unit 21 and GND _. A P channel MOS transistor 50 is inserted in series between the unit 22 and _VDD .
A MOS transistor 51 is inserted in parallel, an N-channel MOS transistor 52 is inserted in series between the N-channel MOS transistor 32 and GND, and an N-channel MOS transistor is inserted between this N-channel MOS transistor 52 and the output end of the unit 22 . 53 is inserted, a set signal SET is supplied to each gate of the MOS transistors 46 and 49, and an inverted signal of the set signal by an inverter 54 is supplied to each gate of the MOS transistors 51 and 52. Supply the reset signal RESET to each gate of
An inverted signal of the reset signal from an inverter 55 is supplied to each gate of MOS transistors 47 and 48. In this example circuit, the set signal SET and reset signal RESET
When both become high level, MOS transistors 49 and 51 are turned on, and signal B is forcibly set to high level and signal A is forcibly set to low level. Therefore, in this case, priority is given to set. FIG. 10 is a circuit diagram of a sixth embodiment of the present invention. This sixth embodiment circuit is a circuit in which the channel type of each MOS transistor in the first embodiment circuit shown in FIG. 3 is replaced with an opposite channel type. The relationship is also reversed. In FIG. 10, the number 1 is prefixed to the parts corresponding to those in FIG. 3 above. Also, Figure 11 shows the above 1
2 is a timing chart showing the operation of the embodiment circuit shown in FIG. As is clear from this timing chart, when the input signal D changes in synchronization with the falling of φ, the signal B becomes a 1-bit delayed signal of φ with respect to the input signal D, and conversely, when the input signal D changes in synchronization with the falling of φ, the signal B changes in synchronization with the falling of φ. When changing synchronously, it becomes a half-bit delayed signal of φ. By the way, in the sixth embodiment circuit shown in FIG. 10, if the period during which the input signal D is at a low level is one bit of φ,
1, a P-channel MOS transistor 128
can be omitted. Figure 12 shows the above MOS
This is a timing chart showing the operation when the transistor 128 is omitted. FIG. 13 is a circuit diagram of a seventh embodiment of the present invention. In this seventh embodiment circuit, the above-mentioned 10th embodiment
This circuit has a reset function added to the circuit of the sixth embodiment shown in the figure. In order to provide this reset function, a P channel MOS transistor 136 is inserted in parallel between the output terminal of the unit 121 and _VDD , and an N channel MOS transistor 137 is inserted between this output terminal and the N channel MOS transistor 125. A P-channel MOS transistor 138 is inserted in series between the P-channel MOS transistor 132 and _VDD , and an N-channel MOS transistor 139 is inserted in parallel between the output terminal of the unit 122 and GND. A reset signal RESET, which is at a high level during reset, is supplied to each gate of transistors 138 and 139, and an inverted signal of the reset signal from an inverter 140 is supplied to each gate of MOS transistors 136 and 137. In such a configuration, the reset signal RESET
When is at a low level, that is, when no reset is applied, the MOS transistors 137 and 138
is turned on and MOS transistors 136 and 139 are turned off, so this circuit operates normally. Also, when the reset signal RESET goes high and a reset is applied, MOS transistor 1
36,139 is turned on, signal B goes to low level,
Signal A is respectively forced to a high level. FIG. 14 is a circuit diagram of an eighth embodiment of the present invention. In this eighth embodiment circuit, the above-mentioned 10th embodiment
This circuit has a set function added to the circuit of the sixth embodiment shown in the figure. In order to provide this set function, a P-channel MOS transistor 141 is inserted in series between the output end of the unit 121 and the P-channel MOS transistor 126, and this output end and
N-channel MOS transistor 14 between GND and
2 are inserted in parallel, a P channel MOS transistor 143 is inserted in parallel between the output terminal of the unit body 122 and _VDD , and an N channel MOS transistor 129 is inserted in parallel.
N-channel MOS transistor 1 between
44 is inserted in series, and the above MOS transistor 14
A set signal SET, which becomes high level when set, is supplied to each gate of the MOS transistors 1,142, and an inverter 145 is supplied to each gate of the MOS transistors 143, 144.
The inverted signal of the set signal is supplied. In such a configuration, when the set signal SET is at a low level, that is, when no set is applied, MOS transistors 141 and 144 are turned on and MOS transistors 142 and 143 are turned off, so that this circuit operates normally. Also, when the set signal SET becomes high level and the set is applied, the MOS transistors 142 and 143
is turned on, signal B is forcibly set to high level, and signal A is forcibly set to low level. FIG. 15 is a circuit diagram of a ninth embodiment of the present invention. In this ninth embodiment circuit, the thirteenth
By combining the circuits shown in FIG. 14 and FIG. 14, a reset function and a set function are added to the circuit of the sixth embodiment shown in FIG. MOS transistor 1
36 and 139 are turned on, signal B is forced to a low level, and signal A is forced to a high level.
Therefore, in this case, priority is given to reset. FIG. 16 is a circuit diagram of a tenth embodiment of the present invention. This tenth embodiment circuit shows another example in which a reset function and a set function are added to the sixth embodiment circuit shown in FIG. 10 above. In order to provide this reset function and set function, a P-channel MOS transistor 146 is inserted in series between the output end of the unit 121 and the P-channel MOS transistor 126, and this P-channel MOS transistor
A P channel MOS transistor 147 is inserted in parallel between the MOS transistor 146 and _VDD , and the N
An N channel MOS transistor 148 is inserted in series between the channel MOS transistor 124 and GND, and an N channel MOS transistor 148 is inserted between the output terminal of the unit body 121 and GND.
A channel MOS transistor 149 is inserted in parallel, and the P channel MOS transistor 132 and V _DD
A P-channel MOS transistor 150 is inserted in series between the output terminal of the unit 122 and _VDD , a P-channel MOS transistor 151 is inserted in parallel between the
N-channel MOS transistor 15 between GND and
2 are inserted in series, and an N-channel MOS transistor 153 is inserted in parallel between this N-channel MOS transistor 152 and the output end of the unit body 122 .
A set signal SET is supplied to each gate of the MOS transistors 146 and 149, and an inverter 1 is supplied to each gate of the MOS transistors 151 and 152.
54, and the above
A reset signal RESET is supplied to each gate of the MOS transistors 150 and 153, and an inverter 1 is supplied to each gate of the MOS transistors 147 and 148.
55, an inverted signal of the reset signal is supplied. In this embodiment circuit, when the set signal SET and reset signal RESET both become high level, MOS transistors 149 and 151 are turned on, and signal B becomes high level.
Signal A is respectively forced to a low level. Therefore, in this case, priority is given to set. As explained above, according to the present invention, it is possible to provide a dynamic type D flip-flop circuit which can operate stably without causing malfunction up to extremely high frequencies because it is operated by a single-phase pulse signal. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional two-phase dynamic type D flip-flop circuit, FIG. 2 is a timing chart showing its operation, FIG. 3 is a circuit configuration diagram according to a first embodiment of the present invention, and FIG. 4 and FIG. 5 are timing charts showing the operation of the above embodiment circuit, FIG. 6 is a circuit diagram of a second embodiment of the present invention, and FIG. 7 is a circuit diagram of a third embodiment of the present invention. , FIG. 8 is a circuit configuration diagram of a fourth embodiment of this invention, FIG. 9 is a circuit diagram of a fifth embodiment of this invention, and FIG. 10 is a circuit configuration diagram of a sixth embodiment of this invention. 11 and 12 are timing charts showing the operation of the circuit of the sixth embodiment, FIG. 13 is a circuit diagram of the seventh embodiment of the present invention, and FIG. 14 is a timing chart showing the operation of the circuit of the sixth embodiment. FIG. 15 is a circuit diagram of the ninth embodiment of the present invention, and FIG. 16 is a circuit diagram of the ninth embodiment of the present invention.
FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. 21, 22, 23, 121, 122, 123...
...unit body, 40, 45, 54, 55, 140, 1
45,154,155...Inverter.

Claims (1)

[Claims] 1 between the first potential supply end and the first output end
The first and second IGFETs of one channel are inserted in series, and the third and fourth IGFETs of the other channel are inserted in series between this first output terminal and the second potential supply terminal. A unit body is constructed, and one-channel fifth and sixth IGFETs are inserted in series between the first potential supply terminal and the second output terminal, and the second output terminal and the second potential supply terminal are connected in series. The seventh and eighth IGFETs of the other channel are inserted in series between the terminal and the second unit, and the seventh and eighth IGFETs of the one channel are inserted in series between the first potential supply terminal and the third output terminal. 9. 10th
An IGFET is inserted in series and the third output terminal of the other channel is inserted between this third output terminal and the second potential supply terminal.
Insert 11 IGFETs to form the third unit,
An input signal is supplied to the gates of the second and third IGFETs, an output signal of the first unit is supplied to the gates of the sixth and seventh IGFETs, and the tenth
The output signal of the second unit body is supplied to the gate of the IGFET, the output signal of the third unit body is supplied to the gates of the fourth and fifth IGFETs, and the output signal of the third unit body is supplied to the gates of the fourth and fifth IGFETs. , a dynamic type D flip-flop circuit characterized in that a one-phase pulse signal is supplied to the gate of an eleventh IGFET.