JPS6223097Y2 - - Google Patents
Info
- Publication number
- JPS6223097Y2 JPS6223097Y2 JP1981093946U JP9394681U JPS6223097Y2 JP S6223097 Y2 JPS6223097 Y2 JP S6223097Y2 JP 1981093946 U JP1981093946 U JP 1981093946U JP 9394681 U JP9394681 U JP 9394681U JP S6223097 Y2 JPS6223097 Y2 JP S6223097Y2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- semiconductor device
- plastic package
- soft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920005989 resin Polymers 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 17
- 239000004033 plastic Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 5
- 238000004382 potting Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 description 15
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置用プラスチツクパツケージ
の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in plastic packages for semiconductor devices.
半導体装置は、素子の機械的な固定、外気から
の保護、外部への電気的引き出し、素子の放熱等
の目的をもつてパツケージに封入されて使用され
るが、封止方法には気密封止型と樹脂封止型とが
ある。封止特性は気密封止型がすぐれているが、
原価面からは樹脂封止型がすぐれているので、樹
脂封止型も多用されている。樹脂封止型パツケー
ジの代表的な一例にDIP型パツケージがあり、お
おむね第１、２図に示す構造を有する。第１図は
従来技術におけるDIP型プラスチツクパツケージ
の平面図であり、第２図はそのＡ−Ａ断面図であ
る。図において、１は半導体装置素子であり、
２，２′はリードフレームであり、その一部２は
外部引き出しリード線として、又、他の一部２′
はダイアタツチ部３において半導体装置素子１を
支持するフレームとして機能する。そして、この
リードフレームの材料としては熱膨張率が大きく
電気伝導性の良好な材料として、銅、銀、ニツケ
ル等でメツキなされた42アロイが主として使用さ
れる。４はピンであり、リードフレーム２と一体
である。５は成形された樹脂部であり、主とし
て、エポキシ系樹脂が使用される。 Semiconductor devices are used by being sealed in a package for the purpose of mechanically fixing the device, protecting it from the outside air, drawing electricity to the outside, and dissipating heat from the device. There are molds and resin-sealed types. The hermetically sealed type has excellent sealing properties, but
Since the resin-sealed type is superior in terms of cost, it is also frequently used. A typical example of a resin-sealed package is a DIP package, which has a structure roughly shown in Figures 1 and 2. FIG. 1 is a plan view of a conventional DIP type plastic package, and FIG. 2 is a sectional view taken along line A-A. In the figure, 1 is a semiconductor device element,
2 and 2' are lead frames, part 2 of which is used as an external lead wire, and the other part 2'
functions as a frame that supports the semiconductor device element 1 in the die attach section 3. As the material for this lead frame, 42 alloy plated with copper, silver, nickel, etc. is mainly used, as it has a large coefficient of thermal expansion and good electrical conductivity. 4 is a pin, which is integrated with the lead frame 2. 5 is a molded resin part, and epoxy resin is mainly used.
ところが、従来技術におけるこの種プラスチツ
クパツケージには、使用中、第２図に６をもつて
示す領域において、成形された樹脂部５にクラツ
クが発生して、封止機能が阻害されることが往々
認められるという欠点がある。 However, in this type of plastic package in the prior art, during use, cracks often occur in the molded resin part 5 in the area indicated by 6 in FIG. 2, which impairs the sealing function. It has the disadvantage of being recognized.
本考案の目的は、この欠点を解消することにあ
り、サーマルサイクルに曝されても成形樹脂にク
ラツクが発生しにくく、堅牢であり、良好な封止
機能を保持しうる高信頼性を有する半導体装置用
プラスチツクパツケージを提供することにある。 The purpose of this invention is to eliminate this drawback, and to create a highly reliable semiconductor that is hard to cause cracks in the molded resin even when exposed to thermal cycles, is robust, and maintains good sealing function. An object of the present invention is to provide a plastic package for a device.
その要旨は、リードフレームが半導体装置素子
を支持するダイアタツチ部下面に樹脂ポツテイン
グ法を施こしてシリコン樹脂、軟質エポキシ樹
脂、ポリイミド樹脂等よりなる層を形成すること
にある。この樹脂ポツテイングは、リードフレー
ムに半導体装置素子をダイアタツチした後、これ
を上下に方向転換して施せば、容易に実施するこ
とができる。 The gist is to form a layer made of silicone resin, soft epoxy resin, polyimide resin, etc. on the lower surface of the die attach where the lead frame supports the semiconductor device element by applying a resin potting method. This resin potting can be easily carried out by die-attaching the semiconductor device element to the lead frame and then changing the direction up and down.
以下、図面を参照しつつ、本考案の一実施例に
ついて説明し、本考案の構成と特有の効果とを明
らかにする。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings, and the configuration and unique effects of the present invention will be clarified.
第３図は本考案の一実施例を示し、第２図に対
応する面における断面図である。図において、
１，２，２′，３，４，５は第２図に示すところ
と全く同一であり、夫々、半導体装置素子、リー
ドフレーム、ダイアタツチ部、ピン、成形された
樹脂部である。７が本考案の要旨である軟質樹脂
層であり、ダイアタツチ部３において、半導体装
置素子１を支持するリードフレーム２′の下面に
形成されている。この軟質樹脂層を形成する材料
は(イ)軟質であり、(ロ)耐熱性があり、(ハ)熱伝導度が
大きく、(ニ)化学的に安定な樹脂であれば足りる
が、α線対策として半導体装置素子表面に樹脂ポ
ツテイングするために通常使用されるシリコン樹
脂、軟質エポキシ樹脂、ポリイミド樹脂等におい
て、効果が確認されており、これらを使用すれ
ば、事実上追加的工程とはならないので、工程上
の不利益も惹起しない。 FIG. 3 shows an embodiment of the present invention, and is a sectional view in a plane corresponding to FIG. 2. In the figure,
1, 2, 2', 3, 4, and 5 are exactly the same as shown in FIG. 2, and are respectively a semiconductor device element, a lead frame, a die attach portion, a pin, and a molded resin portion. Reference numeral 7 denotes a soft resin layer, which is the gist of the present invention, and is formed on the lower surface of the lead frame 2' supporting the semiconductor device element 1 in the die attach portion 3. It is sufficient that the material forming this soft resin layer is (a) soft, (b) heat resistant, (c) has high thermal conductivity, and (d) chemically stable. As a countermeasure, the effectiveness of silicone resin, soft epoxy resin, polyimide resin, etc., which are usually used for resin potting on the surface of semiconductor device elements, has been confirmed, and if these are used, there will be no additional process in fact. , does not cause any disadvantages in the process.
以上の構成を有する半導体装置用プラスチツク
パツケージに対し、−50℃乃至＋150℃の温度間を
往復するサーマルサイクルを100回繰り返し施こ
したが、第２図に６をもつて示すクラツクの発生
を認めなかつた。 The plastic package for semiconductor devices having the above configuration was repeatedly subjected to thermal cycles of going back and forth between -50°C and +150°C 100 times, but the occurrence of cracks as shown at 6 in Figure 2 was observed. Nakatsuta.
以上説明せるとおり、本考案によれば、リード
フレームのダイアタツチ部下面に樹脂ポツテイン
グ法をもつて形成された軟質層が設けられてお
り、リードフレームと樹脂との間のストレスを吸
収するので、サーマルサイクルを受けても、成形
された樹脂にクラツクが発生する等の欠点を有す
ることなく、信頼性の高い半導体装置用プラスチ
ツクパツケージを提供することができる。 As explained above, according to the present invention, a soft layer formed by the resin potting method is provided on the lower surface of the die attach of the lead frame, and as it absorbs the stress between the lead frame and the resin, thermal It is possible to provide a highly reliable plastic package for a semiconductor device without having defects such as cracks occurring in the molded resin even after being subjected to cycles.
第１図は従来技術にかかる半導体装置用プラス
チツクパツケージの概念的平面図であり、第２図
はそのＡ−Ａ断面図である。第３図は本考案の一
実施例に係る半導体装置用プラスチツクパツケー
ジの、第２図に対応する面における断面図であ
る。
１…半導体装置素子、２，２′…リードフレー
ム、３…ダイアタツチ部、４…ピン、５…成形さ
れた樹脂部、６…クラツク、７…軟質樹脂層。
FIG. 1 is a conceptual plan view of a plastic package for a semiconductor device according to the prior art, and FIG. 2 is a cross-sectional view taken along the line AA. FIG. 3 is a cross-sectional view of a plastic package for a semiconductor device according to an embodiment of the present invention, taken along a plane corresponding to FIG. 2. DESCRIPTION OF SYMBOLS 1... Semiconductor device element, 2, 2'... Lead frame, 3... Die attach part, 4... Pin, 5... Molded resin part, 6... Crack, 7... Soft resin layer.
Claims (1)
てモールドされてなるプラスチツクパツケージに
おいて、前記リードフレームが前記素子を支持す
る前記リードフレームのダイアタツチ部下面に樹
脂ポツテイング法をもつて形成された軟質樹脂層
を有することを特徴とする、プラスチツクパツケ
ージ。 In a plastic package in which an element mounted on a lead frame is molded with resin, the lead frame has a soft resin layer formed by a resin potting method on the lower surface of a die attach of the lead frame that supports the element. A plastic package comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9394681U JPS58440U (en) | 1981-06-25 | 1981-06-25 | plastic packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9394681U JPS58440U (en) | 1981-06-25 | 1981-06-25 | plastic packaging |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58440U JPS58440U (en) | 1983-01-05 |
| JPS6223097Y2 true JPS6223097Y2 (en) | 1987-06-12 |
Family
ID=29888902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9394681U Granted JPS58440U (en) | 1981-06-25 | 1981-06-25 | plastic packaging |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58440U (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0744241B2 (en) * | 1984-02-06 | 1995-05-15 | 日東電工株式会社 | Method for manufacturing semiconductor device mounting substrate |
| JPH0334920Y2 (en) * | 1986-06-30 | 1991-07-24 | ||
| JPH0526760Y2 (en) * | 1987-03-11 | 1993-07-07 | ||
| US7719096B2 (en) * | 2006-08-11 | 2010-05-18 | Vishay General Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS498596A (en) * | 1972-05-15 | 1974-01-25 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5461556U (en) * | 1977-10-07 | 1979-04-28 |
-
1981
- 1981-06-25 JP JP9394681U patent/JPS58440U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS498596A (en) * | 1972-05-15 | 1974-01-25 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58440U (en) | 1983-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR960009136A (en) | Semiconductor package and manufacturing method | |
| KR960019676A (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| JPS6223097Y2 (en) | ||
| JPH04249348A (en) | Resin sealed semiconductor device and manufacture thereof | |
| JPS60136347A (en) | Semiconductor device and manufacture thereof | |
| JPH0254665B2 (en) | ||
| JPS6086851A (en) | Resin sealed type semiconductor device | |
| JPH04340751A (en) | Plastic molded type semiconductor device | |
| JP3134445B2 (en) | Resin-sealed semiconductor device | |
| JPH0135478Y2 (en) | ||
| JPS5986251A (en) | Leadframe for resin-sealed semiconductor device | |
| JPS60175433A (en) | Manufacture of resin-sealed semiconductor device and lead frame | |
| JP2601033B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JPS60229352A (en) | Resin sealed type semiconductor device and resin sealing method thereof | |
| KR200148634Y1 (en) | Semiconductor package | |
| JPS6220352A (en) | Semiconductor device | |
| KR950000101Y1 (en) | Semiconductor package lead frame | |
| KR930008864B1 (en) | Semiconductor pakage and manufacturing method thereof | |
| KR940008328B1 (en) | Film type package and manufacturing method thereof | |
| JPS6246268Y2 (en) | ||
| JPH02246143A (en) | Lead frame | |
| JPH02202042A (en) | Resin-sealed semiconductor device | |
| JPS6112682Y2 (en) | ||
| KR0119764Y1 (en) | Semiconductor package | |
| JPS6046058A (en) | Semiconductor device |