JPS62203067A - Display apparatus - Google Patents

Abstract

PURPOSE:To enhance the reliability of testing operation, by fixing not only the drive clock of a horizontal scanning circuit but also an input signal starting scanning operation. CONSTITUTION:Writing MOSFET T1ij, display element driving MOSFET T2ij, input signal accumulating capacity Cij, driving voltage reading MOSFET T3ij and row selecting MOSFET T4i are arranged to a display element 3ij and this unit picture element is formed as a matrix pattern. At the time of usual scanning operation, clocks phi1, phi2 are given to a horizontal scanning unit 2 and the output Hi thereof is successively brought to a row selecting state. At the time of testing, when an input signal I and a clock are set to '1', all of outputs Hi go to the row selecting state without supplying drive clocks. By this method, the testing of a picture element circuit can be performed for a plurality of lines selected by a vertical scanning circuit 1 without generating the erroneous operation due to the effect of the drive clock of the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a technique for speeding up testing of circuits in a pixel section of a display device.

<Prior art> In an active matrix type display device, a means for testing the circuit constituting each pixel is disclosed in Japanese Patent Laid-Open No. 57-9.
9688.

In a display device capable of this test, when detecting a short circuit in a MO5I transistor for driving a display pixel in a pixel portion, that is, a leakage abnormality in a transistor, it is possible to simultaneously test a plurality of pixels. In conventional display devices, a dynamic type circuit is usually used as a horizontal scanning circuit due to the relationship between the number of elements and operating speed. Therefore, in such a device, even when all the outputs of the horizontal scanning circuit are selected, it is impossible to stop the clock, and it is necessary to keep the scanning circuit running at a clock frequency higher than a certain frequency. There is.

For this reason, if a clock is superimposed on an input signal, an output signal, etc. for testing, it becomes impossible to input and output correct signals, and the reliability of the test operation may be significantly reduced. That is, as is well known, in a dynamic circuit, when the clock is stopped, data held in a capacitive portion (including parasitic capacitance) in the circuit disappears, and the state of the circuit becomes undefined. Therefore, in the prior art, it is impossible to stop the clock even when all outputs of the shift registers are kept constant. Since lines for inputting video signals and outputting test signals run parallel to the line to which this clock is supplied, the test signals are disturbed by capacitive or inductive coupling, making it impossible to input and output correct signals. .

<Object of the Invention> In view of the above-mentioned problems, the present invention provides a MadUx display system;
Fix the driving clock of the horizontal scanning circuit connected to Raku,
By fixing the input signal that starts scanning, it is possible to select all the outputs of the horizontal scanning circuit and perform testing without supplying the driving clock to the scanning circuit, improving the reliability of test operations. The present invention provides a display device characterized by the following.

<Example> FIG. 1 is a block diagram of a display device according to the present invention.

In the figure, 1 is a vertical scanning circuit, 2 is a horizontal scanning circuit, and 3 is a vertical scanning circuit.
ij (i = 1. . . . 1m, j = 1. . . ., n) is a display element, Tl1j is a writing MO5 transistor, T
2ij is MO5I-transistor for display element driving, C1J
T3i is an input signal storage capacitor, T3i is a drive voltage readout MOS transistor, and T4i (i=1.., m) is a column selection MO5l-range nut. Further, R is a pull-up resistor, and 4 is a determination circuit.

FIG. 2 shows an example of a circuit implementing the present invention when a conventionally used two-phase clock drive shift register is used as the horizontal scanning circuit 2. In FIG.

The inverter Inv, I (I=1.2.-) is a circuit for amplifying and inverting the signal applied to the input I and transferring it to the next stage. Tr, I is a transfer transistor that controls the transmission of a signal from the output of inverter Inv, I to the input of Inv, I+1. In a normal scanning operation, as shown in FIG.
2. . The timing chart in this case is shown in Figure 3.

On the other hand, when performing a test operation, Tr, 21'-1+
By setting all the signals supplied to the Tr, 2 I' to "1" and setting the input signal to "1", all outputs Hi are brought into the column selection state without supplying a drive clock. With this, the horizontal scanning circuit 2
Testing of pixel circuits at the same time without causing malfunctions due to the influence of drive clocks, that is, MO for driving display elements.
A leakage abnormality detection test of the 3I-transistor T2ij becomes possible.

The circuit when outputting the test signal is as shown in FIG.

That is, since all of the transistors to be tested T2ij are connected in parallel, if even one has a "short circuit" abnormality, it is determined to be "defective". Therefore, all pixels can be tested in parallel.

FIG. 5 shows that in normal scanning operation (It=1), two-phase clock φ1. 5 is an embodiment of a circuit that outputs φ2 and can easily fix all drive clocks to the state of "1" by setting the external input signal It to "0" during testing. This is a normal two-phase lock generation circuit.

Note that the circuit shown in FIG. 2 can also be driven by a pseudo two-phase clock. A timing chart in this case is shown in FIG.

FIG. 7 shows that in normal scanning operation, the external signal It is set to "1".
An embodiment of a circuit that generates a pseudo two-phase clock from the clock φ and can easily fix all driving clocks to the state of "1" by setting the external signal It to "0" during testing. It is.

FIG. 8 shows an example of a circuit in which the present invention can be implemented when a conventionally used shift register using a clocked CMO 5 driven by a two-phase clock is used as a horizontal scanning circuit. This embodiment includes a CMOS inverter that inverts and amplifies an input signal and outputs the inverted signal, and a clocked CMOS inverter that inverts and amplifies the input signal and outputs the inverted and amplified input signal in response to external clock signals φ and φ.

In normal scanning operation, the clocks φ, φ are set to φ, Tr,
8I-7,Tr, 8I-4,Tr, 8I-3
, Tr, 8I (I=1.2. ・), φ is Tr, 8I -6, Tr, 8I-5, Tr, 81
-2. By supplying the signal to the Tr and BT-1 (1=L2.-), the selection signal output Hi is sequentially brought into the selected state. A timing chart in this case is shown in FIG.

On the other hand, when performing a test, all the signals given to the Tr are set to "1" and the input signal I is set to "0", so that all the outputs are set to Hi without supplying a drive clock.
becomes the column selection state. This makes it possible to simultaneously test the pixel circuits for the rows selected by the vertical scanning circuit without causing malfunctions due to the influence of the drive clock of the horizontal scanning circuit.

Note that the clock φ and φ generation circuit may have the same configuration as that shown in FIG.

<Effects of the Invention> As explained in detail above, according to the present invention, pixels in a row selected by a vertical scanning circuit can be simultaneously tested with high reliability without driving the horizontal scanning circuit. This makes it possible to reduce test time and test costs.

[Brief explanation of drawings]

1, 2, 4, 5, 7 and 8 are circuit diagrams, and FIGS. 3, 6 and 9 are timing charts. Explanation of symbols 1: Vertical scanning circuit, 2: Horizontal scanning circuit, 3ij: Display element, Tl1j: MOS transistor for writing, T2ij: MOS transistor for driving display element, Cij: Input signal storage capacitor, T3ij: For reading drive voltage MO5I-Language nut, T41: MO for column selection
5l-transistor, R nibble-up resistor, 4: Judgment circuit. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Procedural amendment April 30, 1985 Palace of the Chief Patent Office 2, Invention title display device 3, Relationship with the person making the amendment case Patent applicant 4, The following statement is inserted between lines 19 and 20 of page 7 of the statement of contents of the amendment. In addition, in a circuit that requires an output of opposite polarity to that shown in this configuration example as an output of a horizontal scanning circuit, all columns can be selected by appropriately converting and fixing the polarity of the drive clock and input signal. It is possible to make it into a state.”

Claims (1)

[Claims] 1. Unit pixels are arranged in a matrix, each unit pixel has a transistor for driving the pixel, and further has a transistor for taking out the drive signal level to the outside. In a display device that enables electrical testing, by fixing the driving clock of the scanning circuit and fixing the signal that starts scanning, the output of the horizontal scanning circuit is set to the selected state for all columns, and one row Alternatively, a display device characterized in that it is possible to simultaneously test pixels in two or more rows.