JPS62197838A - Watchdog timer controller - Google Patents

Abstract

PURPOSE:To set freely a long monitor time by producing a time-out signal without resetting a watchdog timer counter in case a computer system has the abnormality and the generating frequency of interruption signals exceeds a certain level. CONSTITUTION:When the interruption signal IRQ is produced from a D flip-flop circuit 3 by a clock pulse CL, a microprocessor receives the cyclic IRQ and resets the circuit 3 by means of the firmware. Then the value of a register CNT set in a RAM area is increased by 1 in order to count the generating frequency of said cyclic IRQ. If the value CNT of the IRQ generating frequency is less than (t1/t0)+2, a watchdog timer counter 1 is reset by the data signal obtained at the microprocessor side. While the counter 1 is not reset when the value CNT exceeds (t1/t0)+2.

Description

Detailed Description of the Invention <Field of Industrial Application> The present invention provides a watch dog timer control device for improving the monitoring time constraints of a watch dog timer that monitors the operation of a t1 smart system. It is something to do.

<Prior Art> The configuration of a conventional watch dog timer circuit is shown in FIG. 4(a), and its operation flow is shown in FIG. 4(1)).

As shown in FIG. 4(a), the watch dog timer circuit is constructed by connecting an address decoder 2 to a watch dog timer counter 1.

In this circuit, as shown in FIG. 4(b), the total ci
When the processing program of the gi system is started, the chip select from the address decoder 2 is also executed by the circle C8. C
Start counting L, the processing program returns ttN '7,
That is, l) is reset by the address decoder 2 after an interval T has elapsed. Address decoder 2 even after time T has elapsed.
If a reset signal (signal@CS) is not given from the watch dog timer counter 1, the watch dog timer counter 1 will time out, output a timeout signal 9, and notify the M1 smart system that an abnormality has occurred. . This supervisor? jA time T is set smaller than time t determined by each circuit element that constitutes the computer system.

In this way, in the conventional watch dog timer circuit, the monitoring time T of the watch dog timer is
Since it is uniquely determined by each element that makes up the smart system, firmware that uses this watch dog timer circuit has I! , a situation arises in which 11 ladles are given. In order to increase the monitoring time of the watch dog timer, it was necessary to change the hardware that made up the computer system.

・Problems to be solved by the invention> The technical problems to be solved by the invention are as follows:
It is an object of the present invention to enable the monitoring time of a dog timer to be set regardless of the hardware configuration, and an object of the present invention is to realize a watch dog timer control device that can freely set a long monitoring time. .

・Means for Solving the Problems> The present invention that solves the above problems includes a watch dog timer counter that counts clock pulses and generates a time-out signal to monitor the operation of the computer system. In the watch dog timer control il+ device, means for starting the watch dog timer counter, and means for inputting the clock pulse to start the watch dog timer counter,
an interrupt signal generation circuit that provides an interrupt signal to a microprocessor in the computer system; a means for storing the number of times this interrupt signal has been generated; and a means for resetting the watch dog timer counter using the interrupt signal; The watch dog timer control device is characterized in that it has a circuit means for not resetting the watch dog timer counter when the watch dog timer counter is in a state of tension.

The watch dog timer control device of the present invention resets the watch dog timer counter every time an interrupt signal is generated by the interrupt signal generation circuit, and
When the machine system becomes abnormal and the number of times an interrupt signal is issued exceeds a certain value, a time-out signal is generated without resetting the watch dog timer counter.

<Embodiment> FIG. 1 shows an example of a watch dog timer control device embodying the present invention.

In this figure, 1 is a C notch dog timer counter, and 2 is an address decoder, which are the same as those in the conventional two A notch dog timer circuit shown in FIG. 4(a). 3 inputs the clock pulse CI-, outputs a periodic interrupt (3Q I RQ) to the microprocessor (not shown) in this machine system, and outputs a D flip signal which is reset by the address decoder 2.・The flop circuit F[, 4 is a D flip-flop that outputs an enable fffi/disable signal from the microprocessor side to the watch dog timer counter 1, and is reset by the reset signal of the n system. Circuit FF, 5 is Q of D flip-flop circuit 4
This is a gate circuit to which an output and a watch dog timer counter reset signal of the address decoder 2 are applied. Note that the clock terminal of the D flip-flop circuit FF4 receives the watch dog timer counter chip select signal C8 (
The microprocessor's data strobe signal DS and read/write signal QR/W are applied via the gate circuit 9, and this clock pulse enables the watch dog timer counter. /Set disable.

Now, the operation of the device of the present invention configured as described above will be explained in the first section.
The explanation will be made using the motion 1'1" 1:1- shown in FIG.

Operation 20- in FIG. 2(a) represents a series of operations of the apparatus of the present invention, in which the processing program is activated, watch dog timer counter 1 is enabled, and a series of processes is started, and the time interval T Each microprocessor has a memory circuit (random access memory RAM: not shown)
The firmware register CNT provided in the area is reset (by writing 1 °'0'' into CNT), and the series of processing is continued again.

Figure 2(b) shows the interrupt signal IRQ that occurs at regular intervals.
represents the action performed by

When the interrupt signal IRQ is generated from the D flip-flop circuit 3 by the clock pulse CL, the microprocessor receives this fixed-cycle IRQ and resets the D flip-flop circuit 3 using the firmware. To count how many times a periodic IRQ has occurred,
Set 11t1 of register CNT provided in the RAM area to 1'"
Increment.

Then, this constant frequency 11111 fiff of the number of RQ occurrences
When cNT is less than or equal to (i+/'jO)+2, watch dog timer counter 1 is reset by the data signal on the microprocessor IJ' side, and (t+
/lo)+2, the watch dog timer counter 1 is not reset.

Here, 111(j+/lo)+2 will be explained.

At time t1, the processing program starts and the time ill! After that, the watch dog timer counter 1 itself starts counting, and when time t2 has elapsed, this value becomes the monitoring time t of this watch dog timer control device (t
-tI+t2). Therefore, from the supervision time t of the watch dog timer control device, the watch dog timer
The value obtained by subtracting the time t2 until the time-out signal is generated if counter 1 is not reset, 1゜<-t
1:2) is the generation cycle 1 of the fixed-cycle interrupt signal IRQ.
．． By dividing by, the time to reset the watch dog timer counter 1 can be calculated.

Furthermore 1. By adding 2 to the value of /10, the generation of periodic interrupt signal IRQ and the watch dog timer
Eliminates the time error due to asynchronous timing when counter 1 is enabled, and eliminates the time error in which watch dog timer counter 1 is not reset unless a periodic interrupt IRQ occurs even if "O" is written to register CNT. can do.

By performing such processing, the monitoring time of the watch dog timer device can be extended, and a specific example thereof is shown in FIG.

The example shown in this figure operates according to the following conditions.

Monitoring time of watch dog timer device: -8s Firmware processing time: Tk4S Fixed period scraping signal IRQ period: tO=ls Watch
Counting time of dog timer counter 1; t2-2S t+ (-1: l:2); 6s(j+/
lo) +2;8s When the subtraction machine system starts, a fixed period interrupt signal IRQ is generated by the clock pulse CL and is applied to the microprocessor side.

When the microprocessor receives the interrupt signal IRQ, it resets the D flip-flop circuit 3 and stores the RAM.
After incrementing Ia of register CNT provided in the area by “1”, register value CNT≦i+/(jo+2)
In this case, watch dog timer counter 1 is reset. In this example, the firmware processing time T is 4S, so during normal operation, the firmware writes II O! to the register CNT every 4s. Write l.

Then, the fixed periodic interrupt I RQ is divided again, but some abnormality occurs in this control system, such as 111.
If an error occurs, the microprocessor does not perform O40NT operation even if CNT=4, and the register C
NT increases its value.

When the number of register CNT exceeds 9, CNr≦(j+/
lo)+2 is no longer true, and the microprocessor does not reset watch dog timer counter 1. Therefore, the watch dog timer counter 1 continues counting pulses CL and outputs a time-out signal at time t2 (-2s), indicating that an abnormality has occurred in this sieve system. Notify.

As described above, by configuring as in the present invention, the actual monitoring time of the watch dog timer counter 2
Despite S, the monitoring time can be extended to 85.

Note that this monitoring time can be extended arbitrarily by setting firmware values on the microprocessor side.

<Effects of the Invention> As described above, according to the watch dog timer device of the present invention, the watch dog timer counter is reset each time an interrupt signal is generated from the interrupt signal generation circuit, If the computer system becomes abnormal and the number of occurrences of interrupt signals exceeds a certain value, the watch dog
Since a time-out signal is generated without resetting the timer/counter, the watchdog timer monitoring time can be set regardless of the software configuration, making it possible to freely set a long monitoring time. A ΔTchi dog timer control device can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a "watch dog timer control" device embodying the present invention, and FIG. 2 (a) is a diagram showing an example of a watch dog timer control device according to the present invention. Flow, Figure 3 shows the watch flow of the present invention.
Diagrams for explaining the actual operation of the dog timer control device. FIG. 4(a) is a block diagram showing a conventional watch dog timer device, and FIG. 4(b) is a diagram showing its operation. It's a flow. 1... Watch dog timer counter, 2...
- Address decoder, 3, 4...D flip-flop circuit, 5.9... gate circuit.

Claims (1)

[Claims] A watchdog that monitors the operation of a computer system by counting clock pulses and generating time-out signals.
In a watch dog timer control device comprising a timer counter, means for activating the watch dog timer counter, and an interrupt for inputting the clock pulse and providing an interrupt signal to a microprocessor in the computer system. a signal generating circuit; a means for storing the number of times the interrupt signal has been generated; 1. A watch dog timer control device comprising circuit means that does not perform reset.