JPS62179723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62179723A JPS62179723A JP2155286A JP2155286A JPS62179723A JP S62179723 A JPS62179723 A JP S62179723A JP 2155286 A JP2155286 A JP 2155286A JP 2155286 A JP2155286 A JP 2155286A JP S62179723 A JPS62179723 A JP S62179723A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- titanium
- contact hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 15
- 239000010936 titanium Substances 0.000 claims abstract description 15
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000005360 phosphosilicate glass Substances 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野ｌ
この発明は、・半導体装置の製造方法に関し、特に大規
模集積回路（ＶＬＳＩ）装置における金属電極膜の形成
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] This invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming a metal electrode film in a large scale integrated circuit (VLSI) device.
〔従来の技術Ｊ
第２図は、絶縁膜として、リンシリケートガラス膜（以
下Ｐ８Ｇ膜と記す）を、配線用金属膜として、アルミニ
ウム合金膜（主にＡ６ｉ膜、・・・以下Ａ／Ｓｉ膜と代
表して、記す）を用いた従来の電極配線構造の断面図で
あり、以下これを用いて従来の主要製造工程を説明する
。[Prior art J Figure 2 shows a phosphosilicate glass film (hereinafter referred to as P8G film) as an insulating film and an aluminum alloy film (mainly A6i film, hereinafter referred to as A/Si film) as a metal film for wiring. 1 is a cross-sectional view of a conventional electrode wiring structure using a conventional electrode wiring structure (representatively written as .
まず、図に示す様に、シリコン基板（１）の主面上ＫＰ
ＳＧ暎（２２）をＣＶＤ法、スパッタ法等により形成し
た後、写真製版、エツチング法により選択的にコンタク
ト穴を形成する。その後、スパッタ法或いはＣＶＤ法な
どによりＡ／８１膜（５）を形成し、熱処理を行ってこ
の合金膜のシンターを行う。この際、コンタクト穴内に
おけるＡ／８１合金膜（５）とシリコン基板（１）との
間には低抵抗の電気的接合をとることが必要であるが、
Ａ／ Ｓｉ膜（５）を形成して熱処理を行うと、ＰＳＧ
膜（２２）の表面にＡ／ ８ｉ膜（５）中のシリコン（
６）が同相エピタキシャル成長により析出し°Ｃ１その
一部がコンタクト穴を覆う為、コンタクト穴でのＸ負抵
抗が高くなる問題が発生している。とりわけ、この現象
はｌｐｍ角以下のコンタクト穴の場合に著しく、半導体
素子を微細化する上で障害となる。First, as shown in the figure, KP is placed on the main surface of the silicon substrate (1).
After forming the SG layer (22) by CVD, sputtering, or the like, contact holes are selectively formed by photolithography or etching. Thereafter, an A/81 film (5) is formed by a sputtering method or a CVD method, and a heat treatment is performed to sinter this alloy film. At this time, it is necessary to establish a low resistance electrical connection between the A/81 alloy film (5) and the silicon substrate (1) in the contact hole.
A/ When the Si film (5) is formed and heat treated, PSG
Silicon in the A/8i film (5) is coated on the surface of the film (22).
6) is precipitated by in-phase epitaxial growth, and part of it covers the contact hole, causing a problem in which the negative X resistance in the contact hole becomes high. In particular, this phenomenon is remarkable in the case of contact holes smaller than lpm square, and becomes an obstacle to miniaturization of semiconductor elements.
上記Ａｔ Ｓｉ膜（５）は、アルミニウムのみの材料か
ら電極を形成し、これをシリコン基板（１）とコンタク
トさせた場合、アルミニウムがシリコン基板（１）中に
拡散し、シリコン基板中の接合（ｐ ｎ接合）を破壊
する現象（アロイ、スパイク現象）がある為、これを防
止する目的で一般に用いられているものである。In the At Si film (5), an electrode is formed from only aluminum, and when this is brought into contact with the silicon substrate (1), aluminum diffuses into the silicon substrate (1), forming a bond ( Since there is a phenomenon (alloy, spike phenomenon) that destroys p-n junctions, it is generally used for the purpose of preventing this.
〔発明が解決しようとする問題点Ｊ
絶縁膜ＫＰＳＧ膜が用いられる従来の半導体装置では、
第４図に示す様に、素子の微細化に伴う回路パターンで
、層間膜の埋込みを要する場所においては、段差の埋込
み箇所の幅に対する深さの比が増加するに従い、良好な
平坦化を行う為には、熱処理温度を上げるか、リンの含
有量を増やす必要があった。しかしながら前者は、素子
中の不純物分布や接合に対して影響を与え、素子特性が
変化し、後者では耐湿性が劣化するといった問題が発生
した。この為、ＰＳＧ膜に比べ粘度が低く、従来の処理
温度のままでより平坦化が可能なりＰＳＧ膜が次材料と
して注目されてきたが、ＢＰＳＧ膜を絶縁膜に用いて第
２図に示す様な従来の構造をとると、第３図に示す様に
、熱処理時にＢＰＳＧ膜（２１）とＡ７８１膜（５）と
の界面には、絶縁膜としてＰＳＧ膜（２２）を用いた従
来の構造の場合以上に多竜のシリコン（６）が固相エピ
タキシャル成長により析出した。その結果、接触電気抵
抗が大きくなり、場合によっては、コンタクト穴を析出
シリコン（６）が完全に覆ってしまい、導通不良を起こ
すといった問題が発生した。[Problem to be solved by the invention J In a conventional semiconductor device using an insulating film KPSG film,
As shown in Figure 4, in circuit patterns that accompany the miniaturization of elements, where interlayer film embedding is required, as the ratio of the depth to the width of the step embedding area increases, good planarization is achieved. To achieve this, it was necessary to raise the heat treatment temperature or increase the phosphorus content. However, the former has an effect on the impurity distribution in the element and the bonding, changing the element characteristics, and the latter has caused problems such as deterioration of moisture resistance. For this reason, the PSG film has attracted attention as the next material because it has a lower viscosity than the PSG film and can be flattened at conventional processing temperatures. As shown in Figure 3, the conventional structure uses the PSG film (22) as an insulating film at the interface between the BPSG film (21) and the A781 film (5) during heat treatment. More than ever, polyester silicon (6) was deposited by solid-phase epitaxial growth. As a result, the electrical contact resistance increases, and in some cases, the contact hole is completely covered with the deposited silicon (6), causing a problem of poor conduction.
この発明は、上記の様な問題点を解決する為になされた
もので、大規模集積回路における回路パターンの良好な
平坦化を行う為Ｋ、絶縁膜にＢＰＳＧ膜（２１）を利用
したまま、低抵抗のオーミック接触を得る為にコンタク
ト穴の底部、及び側部にチタンシリサイドｆｉｌ（４２
）を延在させ、そのチタンシリサイド膜（４２）上にＡ
ｊＳｉ膜（５）を用い、コンタクト穴部分で直接ＢＰＳ
Ｇ膜（２１）とＡｊＳｉ膜（５）が接しない様にした構
造を簡単な工程で製造することを目的とする。This invention was made to solve the above-mentioned problems, and in order to achieve good planarization of circuit patterns in large-scale integrated circuits, while using the BPSG film (21) as an insulating film, In order to obtain a low resistance ohmic contact, titanium silicide film (42
) on the titanium silicide film (42).
BPS directly at the contact hole using the jSi film (5)
The purpose is to manufacture a structure in which the G film (21) and the AjSi film (5) are not in contact with each other through a simple process.
〔問題点を解決するための手段Ｊ
この発明に係る半導体装置の製造方法は、シリコン基板
（Ｌ）の主向上に絶縁膜としてＢＰＳＧ膜（２１）を形
成し、この絶縁膜に選択的に形成したコンタクト穴の底
部にシリコン基板に接してチタン層（４１）を形成し、
熱処理により上記チタン層（４１）をシリサイド化する
と同時に、コンタクト穴の側部に迄、チタンシリサイド
膜（４２）をセルファライン的に形成し、この上に電極
としてＡｊ８１膜（５）を形成する様にしたものである
。[Means for Solving Problems J] A method for manufacturing a semiconductor device according to the present invention includes forming a BPSG film (21) as an insulating film mainly on a silicon substrate (L), and selectively forming a BPSG film (21) on this insulating film. A titanium layer (41) is formed at the bottom of the contact hole in contact with the silicon substrate,
At the same time as the titanium layer (41) is silicided by heat treatment, a titanium silicide film (42) is formed in a self-lined manner up to the side of the contact hole, and an Aj81 film (5) is formed on this as an electrode. This is what I did.
「作用」
この発明におけるチタンシリサイド膜（４２）の形成工
程はチタン（４１）をコンタクト穴底部のシリコン基板
（１）上に形成後、熱処理を行う簡単な工程だけで、そ
の両側の先端が、コンタクト穴側面上に沿ってはい上が
抄、 Ｂ Ｐ ８ Ｇｉｌ！（２１）の上面と一致する
ように連続して形成される。また、この様にして形成さ
れたチタンシリサイド膜（４２）は、ＢＰｓ ａ ＠
（ｚｌ）とコンタクト穴内のＡｊＳｉ膜（５）との間の
バリアメタルともなる。"Operation" The process of forming the titanium silicide film (42) in this invention is a simple process of forming titanium (41) on the silicon substrate (1) at the bottom of the contact hole and then performing heat treatment. The upper part is cut along the side of the contact hole, B P 8 Gil! (21) is formed continuously so as to coincide with the upper surface. Moreover, the titanium silicide film (42) formed in this way is BPsa @
(zl) and the AjSi film (5) in the contact hole.
〔実施例］
以下、この発明の一実施例を図について説明する。第１
図（ａ）〜＠は本発明における半導体装置の各製造段階
における断面図を示す。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
Figures (a) to (a) show cross-sectional views at each manufacturing stage of the semiconductor device according to the present invention.
まず、第１図（ａ）に示す様に、シリコン基板（１）の
主面上にＢ Ｐ Ｓ Ｇ ＠ （２１）を形成し、その
上部にシリコン窒化膜からなる開口部形成用膜（３）を
プラズマＣＶＤにより形成する。次に同図（ｂ）に示す
様に、ドライエツチング法により開口部形成用膜（３）
に選択的に開口部を形成する。次に同図（Ｃ）に示す様
に、ウェットエツチング法により、開口部を通してＢＰ
ＳＧ膜（２１）をエツチングし、コンタクト穴を形成す
る。その後、同図（ｄ）に示す様に、例えば、スパッタ
蒸着法により、コンタクト穴の底部、即ちシリコン基板
の表向（１）、及び開口部形成用膜（３）の表面上にチ
タン膜（４１）を蒸着する。次に熱処理を行ない、同図
（ｅ）に示す様に、チタンシリサイド膜（４２）を形成
する。この場合、チタンのはい上がり現象により、チタ
ンシリサイド膜（４２）の両端はコンタクト穴のＢＰＳ
Ｇ膜（２１）側壁に沿ってはい上がり、開口部形成用膜
（３）に当接した形状となる。さらに、ウェットエツチ
ング法により、開口部形成用膜（３）をエツチングする
。この場合、開口部形成用ＩＩ （３）上のチタンＩ！
（４１）はり７トオ７法で除去され、同図（ｆ）に示
す形状となる。最後に、スパッタ蒸着法、或いはＣＶＤ
法等により、Ａ／Ｓｉ膜（５）を形成し、熱処理を行う
。その様にして完Ｔした図が、同図（２）に示すもので
ある。First, as shown in FIG. 1(a), a B P S G @ (21) is formed on the main surface of a silicon substrate (1), and an opening forming film (3) made of a silicon nitride film is formed on top of the B P S G @ (21). ) is formed by plasma CVD. Next, as shown in the same figure (b), the opening forming film (3) is formed by dry etching.
selectively forming openings in the area. Next, as shown in the same figure (C), BP is etched through the opening by wet etching.
The SG film (21) is etched to form a contact hole. Thereafter, as shown in FIG. 4(d), a titanium film ( 41) is deposited. Next, heat treatment is performed to form a titanium silicide film (42) as shown in FIG. In this case, due to the creeping phenomenon of titanium, both ends of the titanium silicide film (42) are exposed to the BPS of the contact hole.
The G film (21) crawls up along the side wall and comes into contact with the opening forming film (3). Furthermore, the opening forming film (3) is etched by a wet etching method. In this case, titanium I on II (3) for opening formation!
(41) It is removed using the beam 7-to-7 method, resulting in the shape shown in FIG. Finally, sputter deposition method or CVD
An A/Si film (5) is formed by a method or the like, and heat treatment is performed. The diagram completed in this way is shown in figure (2).
大規模集積回路装置において、第１図＠に示す様に、絶
縁膜としてＢＰＳＧ膜（２１）を用いた事により、従来
の処理温度でより効果的なりフローを行う事が出来る為
、アスペクト比の大きな回路ノ（ターンの平坦化が出来
る。In large-scale integrated circuit devices, as shown in Fig. 1 @, by using a BPSG film (21) as an insulating film, it is possible to perform a more effective flow at conventional processing temperatures, so The circuit (turns can be flattened).
また、コンタクト穴の底部のシリコン基板（１）表面と
、コンタクト穴でのＢＰＳＧ膜（２１）の側壁にバリア
メタルとしてのチタンシリサイド膜（４２）を連続して
形成させたので、Ａｔ Ｓｉ膜（５）とＢＰＳＧ膜（２
１）とが直接、接しない為、Ａ／Ｓｉ膜（５）中のシリ
コンがコンタクト穴部に固相エピタキシャル成長する現
象を防止できる。これにより、具体的には、ｌｘｌｌＩ
ｍ２ノ大キさのコンタクト穴の場合でも、−例として１
００以下のオーミック接触を得る事が出来る。In addition, since a titanium silicide film (42) as a barrier metal was continuously formed on the surface of the silicon substrate (1) at the bottom of the contact hole and on the sidewall of the BPSG film (21) in the contact hole, the At Si film ( 5) and BPSG film (2
1), it is possible to prevent the silicon in the A/Si film (5) from solid-phase epitaxial growth in the contact hole. This allows, specifically, lxllI
Even in the case of a contact hole with a diameter of m2 - for example 1
It is possible to obtain ohmic contact of 00 or less.
コンタクト穴内のチタンシリサイド膜（４２）の形成工
程は、第１図（ｄ）〜（ｆ）に示した通りであるが、チ
タンの熱処理による、はい上がり現象を利用したので簡
単な工程で効果的に形成できる。The process of forming the titanium silicide film (42) in the contact hole is as shown in Figures 1(d) to (f), and it is a simple and effective process because it takes advantage of the creeping phenomenon caused by heat treatment of titanium. can be formed into
尚、以上は開口部形成用膜（３）としてシリコン輩化膜
を用いたものについて説明したが、他の材料、例えば８
ｉＱＮを主成分とするオキシナイトライド膜を用いても
よい。In addition, although the above description has been made using a silicone layer as the opening forming film (3), other materials such as 8
An oxynitride film containing iQN as a main component may also be used.
また、シリコン基板（１）とＢＰＳＧ膜（２１）との間
にシリコン熱酸化膜を介在させてもよく、さらにチタン
シリサイドＮ （４２）はシリコン基板（１）の主表面
に形成した不純物陰域と接触させてもよいことは明らか
である。Furthermore, a silicon thermal oxide film may be interposed between the silicon substrate (1) and the BPSG film (21), and the titanium silicide N (42) is an impurity shadow region formed on the main surface of the silicon substrate (1). It is clear that contact with
［発明の効果］
以上の様に、この発明によれば、絶縁膜としてＢＰＳＧ
膜を用い、バリアメタルとしてチタンシリサイド膜を形
成したので、回路パターンの微細化にもかかわらず、平
坦化を行いながら、熱処理時にもコンタクト穴部でのシ
リコン析出もなく、低抵抗で優れたオーミック接触を有
する半導体装置を製造できる。また、コンタクト穴底部
に形成したチタン膜を熱処理によりシリサイド化してコ
ンタクト穴側壁にはい上がらせたので、簡単な工程で、
コンタクト穴内側にチタンシリサイド膜を形成すること
が出来る。[Effects of the Invention] As described above, according to the present invention, BPSG is used as an insulating film.
Since a titanium silicide film is formed as a barrier metal using a titanium silicide film, despite the miniaturization of the circuit pattern, it can be flattened and there is no silicon precipitation in the contact hole during heat treatment, resulting in low resistance and excellent ohmic performance. A semiconductor device having contacts can be manufactured. In addition, the titanium film formed at the bottom of the contact hole was turned into silicide through heat treatment and then crawled onto the side wall of the contact hole, making it possible to
A titanium silicide film can be formed inside the contact hole.
第１図（、）〜０は、本発明の一実施例における半導体
装置の各製造工程を示す断面図、第２図は従来の半導体
製造装置を示す断面図、第３図は絶縁膜にＢＰＳＧ膜を
用いた場合での従来構造の半導体装置の断面図、第４図
は素子の微細化に伴う回路パターンのアスペクトの増加
を示す図である。
ｌ・・・シリコン基板、２１・・・ＢＰＳＧ膜、２２・
・・ＰＢＧｐ、３・・・開口部形成用ｆｌｉ（−例とし
てプラズマ窒化［１１） 、４１・・・チタン膜、４２
・・・チタンシリサイド膜、５・・・アルミニクムシリ
コン合金膜（代表例、Ａ／８１膜）、６・・・析出シリ
コン
なお、図中、同一符号は、同−又は相当部分を示す。1(,) to 0 are cross-sectional views showing each manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional semiconductor manufacturing apparatus, and FIG. FIG. 4 is a cross-sectional view of a semiconductor device having a conventional structure using a film, and is a diagram showing an increase in the aspect of a circuit pattern due to miniaturization of elements. l...Silicon substrate, 21...BPSG film, 22.
... PBGp, 3... fli for opening formation (-example: plasma nitridation [11), 41... titanium film, 42
. . . Titanium silicide film, 5 . . . Aluminum silicon alloy film (typical example, A/81 film), 6 .
Claims (3)
ラス膜（以下ＢＰＳＧ膜と略す）を形成する工程、上記
ＢＰＳＧ膜上に開口部形成用膜を形成する工程、上記開
口部形成用膜を選択的に開口して開口部を形成する工程
、上記開口部より上記ＢＰＳＧ膜を等方性エッチングす
る事により、上記ＢＰＳＧ膜に上記開口部よりも大きい
コンタクト穴を形成する工程、上記コンタクト穴の底部
にチタン（Ｔｉ）層を形成する工程、熱処理により上記
チタン層をシリサイド化して、上記コンタクト穴底部並
びに側壁に延在してチタンシリサイド膜を形成する工程
、上記チタンシリサイド膜上に、少なくともシリコンを
含むアルミニウム合金膜を形成する工程を含むことを特
徴とする半導体装置の製造方法。(1) Step of forming a boron phosphosilicate glass film (hereinafter abbreviated as BPSG film) on the main surface of a silicon substrate, forming a film for forming an opening on the BPSG film, and selecting the film for forming an opening. forming a contact hole larger than the opening in the BPSG film by isotropically etching the BPSG film from the opening; a bottom of the contact hole; a step of forming a titanium (Ti) layer on the titanium silicide film; a step of siliciding the titanium layer by heat treatment to form a titanium silicide film extending to the bottom and sidewalls of the contact hole; and a step of forming at least silicon on the titanium silicide film. 1. A method for manufacturing a semiconductor device, comprising the step of forming an aluminum alloy film containing aluminum alloy.
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the opening forming film is a silicon nitride film.
ｉＯＮを主成分とする膜）であることを特徴とする、特
許請求の範囲第１項記載の半導体装置の製造方法。(3) The above opening forming film is an oxynitride film (S
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a film containing iON as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2155286A JPS62179723A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2155286A JPS62179723A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62179723A true JPS62179723A (en) | 1987-08-06 |
| JPH0558564B2 JPH0558564B2 (en) | 1993-08-26 |
Family
ID=12058161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2155286A Granted JPS62179723A (en) | 1986-02-03 | 1986-02-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62179723A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01298765A (en) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9386327B2 (en) | 2006-05-24 | 2016-07-05 | Time Warner Cable Enterprises Llc | Secondary content insertion apparatus and methods |
| US8024762B2 (en) | 2006-06-13 | 2011-09-20 | Time Warner Cable Inc. | Methods and apparatus for providing virtual content over a network |
-
1986
- 1986-02-03 JP JP2155286A patent/JPS62179723A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01298765A (en) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US5384485A (en) * | 1988-05-27 | 1995-01-24 | Fujitsu Limited | Contact structure for connecting an electrode to a semiconductor |
| US5512516A (en) * | 1988-05-27 | 1996-04-30 | Fujitsu Limited | Contact structure for connecting an electrode to a semiconductor device and a method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0558564B2 (en) | 1993-08-26 |
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