JPS62179044A - Multicomputer system - Google Patents

Abstract

PURPOSE:To improve reliability in a duplex control, and to attain an exactness in a master/slave decision by providing a duplex control circuit, and performing the duplex control by controlling each shared memory controller of two pairs of memory units in a shared memory device. CONSTITUTION:A duplex shared memory device 30 consists of independent two pairs of memory units 30a and 30b having shared memory controllers 32a and 32b. At the shared memory interfaces 44-1-44-n of respective computers 40-1-40-n, duplex control circuits 74 which perform the duplex control by controlling the shared memory controllers 32a and 32b in two pairs of the memory units 30a and 30b are provided, and even when a failure is generated in one of the duplex control circuits, a backup by another duplex control circuit can be obtained. And by providing a master/slave deciding means at respective the shared memory controllers 32a and 32b, whether an opposite memory unit is a master or a slave when a corresponding memory unit rises, is decided through an optional shared memory interface. In this way, the multiplexing and the exactness in the master/slave decision can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a compound computer system including a shared memory device with a duplex configuration that is shared by a plurality of computers.

[Technical background of the invention]

Sharing main memory is known as a means of constructing a compound computer system. For this sharing, a shared memory device is a device provided so that multiple computers can access it in the same way as their own main memory.

FIG. 3 shows a shared memory device fli10 shared by multiple computers 20
1 to 20-n share a compound computer system. Shared memory device! In order to improve reliability, 110 is generally duplicated as shown in the figure, and has two memory units of 10%.

10b. Memories) l Oa, J Ob
is mainly memory 11*, llb and memory JJ.
a, a shared memory controller 12h that controls JJb;
12b and a shared memory bus l J a p l J b
And computers 20-1 to 20-n are connected to shared memory path 13g.
, 13b (via &-) 14&-1 to J4&-n,
14b-1 to 14b-n, and memory unit 10a,
10 b Console for operation/4' channel 15m, 1
5b. Shared memory controller J2h
, 12b has a redundant control circuit 16! L.

J6b is provided. Duplex control circuit 16a.

16b is a duplex control path 1 for duplex control.
7 interconnected. Duplex control circuit 16m, 16
b is connected to the memory unit 10 via the duplex control path 17.
*, 10b master/slave determination, 21i conversion synchronization control, and copy control to match the contents of memories Jim and llb. This copy operation is performed from the master side memory to the slave side memory.

[Problems with background technology]

Memories of the system shown in Figure 3) 10&.

At 10b, a shared memory controller 12a.

Duplex control circuit 16a provided within 12b.

16b are interconnected by the duplex control path 17 as described above for duplex control, and operate in communication with each other. For this reason, in the system shown in Figure 3, since the duplex control circuit 161Lel6b is a common part, duplex control is not possible even if a failure occurs in only one circuit, and there is a problem of poor reliability. there were.

It seems that the above problem can be solved by eliminating the duplex control path 17. However, for this reason, K is the calculator 2
It is necessary to have a predetermined computer from 0-1 to 20-n determine the master/slave, and if that computer is out of order or stopped, the master/slave determination will be made. A problem arises in that the shared memory device 10 cannot be started up.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to improve the reliability of duplex control for a duplex shared memory device, and to ensure the determination of master/slave of the duplex shared memory device. The objective is to provide a multifunction computer system that can perform the following tasks.

[Summary of the invention]

According to the present invention, a compound computer system is provided that includes a dual shared memory device that is shared by a plurality of computers. The duplex shared memory device consists of two independent memory units each having a shared memory controller.

Both controllers do not have an LC duplication control circuit as in the prior art and are independent from each other. That is, in this invention, the shared memory controller itself does not have a duplication control function. Instead of providing the shared memory controller itself with a duplex control function, the shared memory interface of each computer is equipped with a duplex control function that controls each shared memory controller of the two sets of memory units described above to perform duplex control. A control circuit is provided. As a result, even if a failure occurs in one duplex control circuit, backup can be provided by another duplex control circuit.

Further, in the present invention, each of the shared memory controllers is provided with master/slave determining means. This master/slave determination means detects whether the other memory unit is a master or slave through an arbitrary shared memory interface when the corresponding memory unit is started up, and determines whether the corresponding memory unit is the master or slave according to the detection result. This determines which state the slave should be in, and it is possible to multiplex master/slave determination.

[Embodiments of the invention]

FIG. 1 shows the configuration of a compound computer system according to an embodiment of the present invention. The system shown in FIG. 1 includes a duplex shared memory device 30 and a plurality of computers 40-1 to 40-n that share the shared memory device 30.

The shared memory device 30 includes two memories 31) 30&,
Consisting of 30b. The memory units 30m and 30b are mainly a memory 31a.

31b1 shared memory controller 32*, 32b.

A shared memory path 33&, which connects the memories 31, 31b via the shared memory controller 32&, 32b.
33b, and the computers 40-1 to 40-n are connected to the memories 31m, 31b via the shared memory paths 33h, 33b (
) J4m-1 to 34
Consists of a-n, 34 b-1 to 34 b-n.

The computers 40-1 to 40-n mainly include the CPU 41-
1 to 41-n, main memories 42-1 to 42-rs which are local memories of the CPUs 41-1 to 4-n, system paths 43-1 to 43-nl, and the system path 4.
3-1 to 43-n (CPUs connected to 41-1
~41-n) and the shared memory port of the shared memory device 30) 34m-1, 34b-1 ~ 34a-n, 34b-
n and the interface line 50. -1.50b-1~
It consists of shared memory interfaces 44-1 to 44-n connected via 50a-n and 50b-n.

FIG. 1(b) shows the configuration of the shared memory controller 32 & of FIG. 1(a). The shared memory controller 32m is a memory controller that controls the memory 31a.
and a shared memory path controller 62 that controls the shared memory path JJJL. This path controller 62 holds statuses indicating various states of the corresponding memory unit 10&. This status includes a flag (g/S flag) 80 indicating whether the memory unit 10* is a master/slave thread. Furthermore, the shared memory controller 32a includes a microprocessor 63 that performs various services requested by the controller 32mK, and a shared memory path 331 that connects the microprocessor 63 to the shared memory path 331.
Shared memory path controller 6 by connecting to
It has a microcomputer interface 64 that allows control of two devices. The microprocessor 63 has a shared memory path 33&, a shared memory date 34m-1 to 34*-
n, and the computers 40-1 to 40-n via their shared memory interfaces 44-1 to 44-n.
1 to 40-n.

The microprocessor 63 also communicates with a microprocessor 75, which will be described later, with the shared memory interfaces 44-1 to 44-n. The configuration of the shared memory controller 32b is also basically the same as that of the shared memory controller 32m shown in FIG. 1(b).

Therefore, regarding the configuration of the shared memory controller 32b, if necessary, please replace it with a1fcb in the above description and the first figure).

FIG. 1(c) shows the configuration of the shared memory interface 44-1 of FIG. 1(&). Shared memory interface 4
4-1 is a shared memory port 34 of the shared memory device 30.
*-1, port interface 71a for duplication corresponding to 34b-1.

71b1 and a system path interface 72 corresponding to the system path 43-1. Date interfaces 71m, 71b and system path interface 72 are interconnected via internal path 73Vc. A duplication control circuit 74 that performs duplication control is connected to this internal path 73. The shared memory interface 44-1 further includes a microprocessor 75 that controls the duplication control circuit 74, and a microprocessor 75 that controls the duplication control circuit 74.
It has a microcomputer interface 76 that enables control of the duplication control circuit 74 by connecting 5 to the internal path 73. Note that the shared memory interface 44-n
The configuration of the shared memory interface 44 shown in FIG.
The configuration is basically the same as that of -1. Therefore, regarding the configuration of the shared memory interface 44-n, if necessary, -1 may be replaced with -n in the above description and in FIG. 1(c).

As is clear from the above description, in this embodiment, the console motherboard is not provided in the memory units 30*, 30b, and the shared memory controller 3
Note that there is no redundant control path connecting between 2a and 32b, and the shared memory controller 3
2a.

32b includes the shared memory controller 12 shown in FIG.
A circuit corresponding to the duplication control circuits 16a and 16b included in m and 12b is not provided. And Figure 1 (C)
Each shared memory interface 44-1, as represented by the -E IJ interface 44-1 shown in FIG.
It should be noted that the duplication control circuits 74 are provided in each of the circuits 44-n to 44-n.

Next, the operation of one embodiment of the present invention will be explained.

■Duplication control The duplication control of the shared memory device 30 is performed by computers 40-1 to 40-1.
40-n shared memory interfaces 44-1 to 44-
n selected duplication control circuits 74 (in the shared memory interface). Now, the duplication control circuit 74 in the shared memory interface 44-1 is
Weighting control shall be performed. In this case, the CPU 41-
1 via the system path 43-1 and the system path interface 72.

Now, the duplication control circuit 74 is the memory unit 30a of the duplexed shared memory device 30.

30b) are individually controlled.

Therefore, the duplication control circuit 74 connects the internal path 73, the port interfaces 71*, 71b, and the interface line 5.
0g-1, 50b-1, shared memory/-) 34m-1,
34b-1 and shared memory paths 33*, 33b to any shared memory controller 32m, 32b. Shared memory controller 32a.

32b is a shared memory interface 44- of the computer 40-1 for duplex control from the duplex control circuit 74.
Control result information is sent to 1.

In this case, if the duplication is under synchronization control, the shared memory controllers 32m, 32b need to notify the other shared memory controller to take the cycle of the shared memory paths 33m, 33b. For this purpose a controller 32a.

A special control signal line must be provided between 32b and 32b.

Therefore, in this embodiment, the duplex shared memory device 30 is made asynchronous as described below.

First, in this embodiment, in order to desynchronize the shared memory device 3Q, double write/single read control is applied in accessing the shared memory device RSO. When accessing the memories 31* and 32b in the shared memory device 30, the memory that can be written to and read from (the memory unit that has it) is the master, and the memory that can only be written to (the memory unit that has it) is the slave. call. When defined above, the master side access frequency (goods) and the slave side access frequency (s
) becomes as follows.

Master-side access frequency (~◇=W+R slave-side access frequency (S) = W, where W; write frequency R; read frequency, therefore (goods) ≧ (S). In this way, in this embodiment, duplication By applying 92 double write and single read under the control of the control circuit 740 and keeping the duplex access frequency at (goods)≧(S),
Even if duplex control is asynchronous, the slave can follow the master. However, it is conceivable that a state of (goods)≦(S) may temporarily occur due to interrupt control.

Therefore, the duplication control circuit 74 determines whether yj? -) Among the input/output buffers (not shown) included in the interfaces 71m and 71b, when the buffer status on the slave side is monitored, control is performed to inhibit access to the master side port.

As described above, in this embodiment, by asynchronously duplicating the duplex control, arbitrary access can be performed in units of one system. Note that the duplication control circuit 74 is controlled by C.
This is performed not only by commands from the PU 4 J-J but also by commands from the microprocessor 75 in the shared memory interface 44-1 via the microcomputer interface 76. This command includes, for example, an offline request issued from the microprocessor 63 of the shared memory controller 32m when an abnormality is detected in the shared memory controller 32a.

Note that in the above explanation, the duplex control is asynchronous in order to make the shared memory device 30 arbitrarily accessible on a single system basis despite the simple configuration, but a synchronization control method is applied. It is also possible.

(2) Master/Slave Determination Next, master/slave determination will be explained with reference to the flowchart of FIG. 2, taking as an example the case where the shared memory controller 32m detects an error.

When an error is detected in the shared memory controller 32, the microprocessor 63 in the shared memory controller 321 issues an error detection interrupt to the CPU 41-1 of the computer 40-1, for example.

From this interrupt K, the CPU 41-7 sends the memory 31b to the shared memory controller 32b via the system path 43-1, the shared memory interface 44-1, the shared memory port 34b-1, and the shared memory path 33b.
Give a command to make it the master. As a result, the microprocessor 63 in the shared memory controller 32b sets the VS flag 80 in the shared memory path controller 62 via the microcomputer interface 64 and the shared memory path 33b. Next, the CPU
4 J-1 is a shared memory interface 44-1
The microprocessor 75Vc issues an initialization request for the memory unit 30a.

When the microprocessor 75 of the shared memory interface 44-1 receives the initialization request from the CPU 4J-J, it transmits the request to the microprocessor 63 of the shared memory controller 32t in the memory unit 30a. As a result, the microprocessor 63 initializes the memory unit 30m including the memory 31a and performs an initial diagnosis. Upon normally completing the above processing, the microprocessor 63 starts up the memory unit 30a as shown in the flowchart of FIG. First, the microprocessor 63 sets the master count value MC and slave count value SC to O (Stella 7'SL).
.

Next, the microprocessor 63 of the shared memory lifter 321 connects the shared memory interfaces 44-1 to 44-
After selecting an arbitrary interface, for example, interface 44-1, from n, and confirming that the interface 44-1 has an IC in a ready state,
-1, the status of the other party's shared memory controller 30b (memory unit 30b having it) is taken in as follows (Stella7'S2).

That is, the microprocessor 63 of the shared memory controller 321 first uses the shared memory interface 44-
A 1 status acquisition request is issued to the 1 microprocessor 75. This allows the shared memory interface 44-
1 microprocessor 63 has a microcomputer interface 76, an internal path 73, and a port interface 71b1.
Interface line 50b-1, shared memory port 3
4b-1, captures the status of the shared memory controller 32b via the shared memory path 33b, and sends the same status to the microcomputer interface 76, internal path 73,
Hard interface 71*, interface line 5
0m-1, the shared memory port 34IL-1, and the shared memory controller 32& via the shared memory path 33a. The microprocessor 63 of the shared memory controller 32m takes in the status of the partner shared memory controller 32b transferred by the microprocessor 63 of the shared memory interface 44-1.

shared memory controller 32m microprocessor 6
3 reads the status of the partner shared memory controller 32b, and determines whether the memory unit 30b (memory 31b) is on the master side based on the set/reset state of the M//S flag 80 in the status. Determination is made (step S3). When one memory unit 5ob (memory 31b of it) is on the master side as in this embodiment, that is, when the determination in step S3 is YES, the microprocessor 63 of the shared memory controller 32m The yVS Hund value MC in the status is cleared to 0 and the slave count value SC is +1 (step S4). The microprocessor 63 then controls the shared memory controller 3.
2a is in a waiting state for a time t previously allocated (step S5), and then it is determined whether the slave count value SC has reached a predetermined value N (step 86).
). If SC has not reached IIC, microprocessor 63 returns to step S2.

On the other hand, the memory 31b of the memory unit 30b (
) is the slave side, that is, if the determination in step S3 is No, the shared memory controller 32h
The microprocessor 63 sets the M/S flag 80 in the status of the shared memory controller 32IL, clears the slave count value SC to 0, and increments the master count value MC by +1 (step 8).
7). The microprocessor 63 enters a waiting state for a time t (step SS), and then determines whether the master count value MC has reached a predetermined value NK (
Step 89).

If MC has not reached N, microprocessor 63 returns to step 82.

Microprocessor 6 of shared memory controller 32h
3 determines that 5C=N in step S6, it determines that (the memory 31a of) the memory unit 30a is definitely a slave, and the shared memory path controller 62
The PjVS flag 80 in the status held in is reset. Similarly, the shared memory controller 32m
The microprocessor 63 of MC=N in step S9
If it is determined that the memory unit 30a (the memory 31a thereof) is definitely the master, the M/S flag 80 in the status held in the shared memory bus controller 62 is set. This g/S flag setting operation is performed in the shared memory controllers 32m and 32b in the memory unit 30a according to the flowchart of FIG. 2 when the system power is turned on.

This can occur if 30b startups are performed in parallel.

In addition, in the flowchart of FIG. 2, Stella 7'S
Waiting time t of 5,88 is 30 m, 3
This is prepared in consideration of the status acquisition from the partner shared memory controller that occurs when 0b startup is performed in parallel. Further, the reason why the master or slave is not determined until MC or SC reaches N is to prevent the inconvenience that both the shared memory controllers 32h and 32b are determined to be master or slave. Yes, in this embodiment, 3 is adopted as N.

Now, when the microprocessor 63 of the shared memory controller 32a determines master/slave and starts up the memory unit 30a that was in the down state, that is, sets the memory unit 30a to the unit ready state, for example, the computer 40-1 A copy request is issued to the microprocessor 75 of the shared memory interface 44-1 in the shared memory interface 44-1. As a result, the microprocessor 75 controls the duplication control circuit 74 so that the duplication control circuit 74 performs a copy operation of copying the contents of the master side memory 31b to the slave side memory 31h. When this copy operation is completed, the shared memory interface 4
The microprocessor 4-1 notifies the microprocessor 631C of the shared memory controller 32h of the completion of copying. In response to this notification of completion, the microprocessor 63 of the shared memory controller 321L turns on a specific line of the shared memory path 33m that indicates whether the memory unit 30h is on-line.

This completes the start-up of memory 22 J (7m).The computers 40-1 to 40-n recognize that memory 22-30m has started due to the state of the specific line mentioned above.
In other words, you can recognize that you have returned to online therapy.

In the above embodiment, by communicating with one shared memory interface in an arbitrary ready state and detecting the state (master/slave) of the other shared memory controller, the shared memory controller can switch between master/slave. Although the explanation has been made assuming that the decision is made, it is not limited to this. For example, it is not possible to intersect with two or more shared memory interfaces, or to make master/slave decisions using a redundant method or majority logic method.
You may. In this case, master/slave determination can be made more reliably than in the previous embodiment.

[Effects of the Invention] As detailed above, according to the present invention, the following effects can be achieved.

■ A duplex control circuit is provided in the shared memory interface of each computer that shares the duplex shared memory device, and the circuit controls each shared memory controller of the two sets of memory units of the shared memory device to perform duplex control. As a result, even if a fault occurs in the duplex control circuit in a computer, there will be a backup with the duplex control circuit in another computer. This makes it possible to perform multiplexing and improves the reliability of duplex control.

(2) Since master/slave can be determined without depending on a specific computer, a shared memory device can also be started up as a master/sled.

■ Since master/slave determination can be made through a shared memory interface within any computer, multiplexing of master/slave determination can be achieved.

■ Due to the above ■, when determining master/slave, 2
Master/slave decisions can be made more reliably since multiplexing or majority logic can be introduced.

[Brief explanation of drawings]

FIG. 1(al) is a block diagram of a compound computer system according to an embodiment of the present invention, and FIG. 1(b) is a block diagram of a compound computer system according to an embodiment of the present invention.
1(C) is a block diagram of the shared memory interface shown in FIG. 1(), and FIG. 2 is a master/slave determination procedure for starting up a memory unit. FIG. 3 is a block diagram showing a conventional example. 30...Shared memory device, 30h, 30b...Memory unit, 31th, 31b--Memory, 32m. 32b... shared memory controller, 40-1 to 40
- n-computer, 41-1 to 41-n-CPU. 44-1 to 44-n... shared memory interface,
63,715...Microprocessor, 74...2
Duplex control circuit, 80...M/S flag. Applicant's agent Patent attorney Takehiko Suzue (b) Figure 1 Figure 2

Claims (1)

[Claims] A duplex shared memory device consisting of two independent sets of memory units each having a shared memory controller, and a duplex shared memory device that is independently installed in a plurality of computers that share this duplex shared memory device, and that the computers are connected to the above two sets of memory units. A shared memory interface for connecting each of the two sets of memory units, and a shared memory interface having a built-in duplication control circuit that controls each shared memory controller of the two sets of memory units to perform duplex control, and each of the shared memory controllers described above. When the corresponding memory unit is started up, it detects whether the other memory unit is a master or slave via any of the above shared memory interfaces, and depending on the detection result, the corresponding memory unit is set to either master or slave status. Master/slave determining means for determining whether the system is a master/slave.