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JPS6217666A - Apparatus for measuring current through voltage application - Google Patents

Apparatus for measuring current through voltage application

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Publication number
JPS6217666A
JPS6217666A JP60157267A JP15726785A JPS6217666A JP S6217666 A JPS6217666 A JP S6217666A JP 60157267 A JP60157267 A JP 60157267A JP 15726785 A JP15726785 A JP 15726785A JP S6217666 A JPS6217666 A JP S6217666A
Authority
JP
Japan
Prior art keywords
current
load
voltage source
capacitor
constant voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60157267A
Other languages
Japanese (ja)
Other versions
JPH0380266B2 (en
Inventor
Yoshihiro Hashimoto
好弘 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP60157267A priority Critical patent/JPS6217666A/en
Publication of JPS6217666A publication Critical patent/JPS6217666A/en
Publication of JPH0380266B2 publication Critical patent/JPH0380266B2/ja
Granted legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To contrive to increase a testing speed, by inspecting a decoupling resistor between the node of load and a smoothing capacitor and a constant voltage output terminal. CONSTITUTION:A decoupling resistor 15 is inserted between the output terminal of a constant voltage source 8 and the node of load 2 and a smoothing capacitor 9 in series and the current flowing to the load 2 from the voltage source 8 is measured by a current measuring device 4. In this case, impedance when the voltage source 8 looked the load 2 becomes high in frequency and looks constant by the impedance of the resistor 15 not dependent on frequency even if the impedance of the capacitor 9 approaches zero. Therefore, the voltage source 8 looks constant in a load condition even with respect to high frequency and the capacity of a phase compensating capacitor 13 can be set small. As a result, the time constant of the capacitor 13 is made small to make it possible to shorten a discharge time and the increase in a testing speed is attained.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は例えばCMO3構造のICに一定電圧を与え
、そのとき流れる電流を測定してそのIcが正常か否か
を試験することに用いることができる電圧印加電流測定
装置に関する。
Detailed Description of the Invention "Industrial Application Field" This invention can be used, for example, to apply a constant voltage to an IC with a CMO3 structure, measure the current flowing at that time, and test whether the IC is normal or not. The present invention relates to a voltage applied current measuring device capable of measuring voltage applied current.

「従来技術」 CMO3構造の半導体メモリのようなIcは基本的には
第2図に示すようにP形F E T Q 、とN形F 
ETQ□が互いに直流電源lに対して直列接続され、こ
れら二本のFETQ、とQ2のゲートが共通接続され、
この共通ゲー)Gに駆動信号を与えることによりF E
 T Q +又はQ2の何れか一方をオンに制御し、そ
のとき他方はオフに制御され、出力端子MにH論理信号
又はし論理信号を出力する構造となっている。このよう
な一つの構造を1論理ゲート素子等と呼んでいる。
``Prior art'' Ic, such as a semiconductor memory with a CMO3 structure, basically consists of P-type FETQ and N-type FETQ, as shown in Figure 2.
ETQ□ are connected in series with each other to the DC power supply l, and the gates of these two FETQ and Q2 are commonly connected,
By giving a drive signal to this common game) G, F E
The structure is such that either T Q + or Q2 is controlled to be turned on, and at that time, the other is controlled to be turned off, and an H logic signal or a low logic signal is output to the output terminal M. One such structure is called one logic gate element or the like.

この回路はFETQ、とQ2のオンとオフの関係を一方
から他方、他方から一方の安定状態に転喚するときFE
TQ、とQ2が同時にオンの状態を通過するため第3図
Aに示すように瞬間的に大きい電流値IFFを持つ短絡
電流が流れるが、安定した状態ではF E T Q +
又はQよの何れか一方が必ずオフとなっているからその
安定状態において流れるドレイン電流19.はわずかな
値ILLとなる。よって静止状態における電力消費量は
少なくなり、例えばメモリの場合ハックアップ用電池の
消耗を少なくできる利点が得られる。
This circuit converts the on/off relationship of FETQ and Q2 from one to the other, and from the other to one stable state.
Since TQ and Q2 pass through the ON state at the same time, a short circuit current with a large current value IFF momentarily flows as shown in FIG. 3A, but in a stable state F E T Q +
Or, since either Q is always off, the drain current 19. flows in that stable state. becomes a small value ILL. Therefore, power consumption in a stationary state is reduced, and for example, in the case of a memory, there is an advantage that consumption of a hack-up battery can be reduced.

ところでこのような構造の論理ゲート素子を集積したl
c2においてFETQ、又はQlの何れか一方又は双方
のオフ抵抗が規定値より小さい値となるように出来上が
ってしまった場合、安定状態におけるドレインN、流の
値ILLが大きくなってしまう不都合が生じる。
By the way, l which integrates logic gate elements with such a structure
If the off-resistance of either or both of FETQ or Ql is made to be smaller than the specified value in c2, a problem arises in that the drain N and current value ILL in a stable state become large.

例えば第4図に示すようにFETQIのオフ抵抗が規定
値より小さい値Rnとなって作られた場合、FETQI
がオンでFETQIがオフの状態では第3図Bに示すよ
うに規定の電流値ILLより大きい電11sxが流れる
。よってこのような不良を具備したFETが作られた場
合はこ不良のF E Tがオフの状態で持回状態に放!
されると電流消費量が大きくなり電池等の消耗が著しく
なる不都合が生じる。
For example, as shown in FIG.
When FETQI is on and FETQI is off, a current 11sx larger than the specified current value ILL flows as shown in FIG. 3B. Therefore, if a FET with such a defect is manufactured, the defective FET should be left in the OFF state and left in the running state.
If this happens, the amount of current consumption increases and the battery, etc., becomes significantly exhausted.

このような不良を検出するための一つの試験方法として
電圧印加電流測定試験が考えられる。この電圧印加電流
試験は第4図に示すように被試験IC2の電源端子VD
IIとit源1の間にit電流検出用抵抗器を直列接続
し、この電流検出用抵抗器3の両端に発生する電圧を測
定器4に取込み、その電圧測一定値から電流値を求めそ
の電流値が規定の範囲内の値であるか否かを判定し、良
否を判定する試験方法である。
One possible test method for detecting such defects is a voltage applied current measurement test. This voltage applied current test is performed at the power supply terminal VD of the IC2 under test as shown in FIG.
An IT current detection resistor is connected in series between II and IT source 1, and the voltage generated across the current detection resistor 3 is input to the measuring device 4, and the current value is determined from the constant voltage measurement value. This is a test method that determines whether the current value is within a specified range and determines pass/fail.

CMO3構造のICを電圧印加を流測定試験により良否
を判定する場合、測定すべき電流は第3図に示したよう
に微少電流値ILLを持つ定常1ittであるにもかか
わらず、F E T Q +とQtの状態を切替える時
点でILLの数千倍〜数万倍のt流値IFFを持つ短絡
電流が流れる。つまり短絡電流と測定すべき電流の比I
PF/ILLは非常に大きな値となる。因みにILL”
数lOマイクロアンペア〜数ナノアンペア、 IFF”
数100ミリアンペア〜数lθミリアンペアとなる。t
ooがIFFの期間V2O点の電圧降下を小さくするた
めには平滑用コンデンサ9が必要であり、このため短絡
電流が終了した時点から電流検出抵抗器3を流れる電流
が掻めて小さい定常電流の値ILLに安定するまでに電
流検出抵抗器3と平滑用コンデンサ9による充電時間が
長く掛かる不都合がある。つまり電流が安定するまでの
時間が長くなるとF E T Q l  とQ2の切替
周期を長く採らなければならない。この結果素子数が多
いICでは試験に要する時間が長くなる。例えば256
 x 1000個の論理ゲート素子を集積したICを1
ミリ秒周期で切替えて試験したとすると試験に要する時
間は256秒となる。1個のICを256秒も掛けて試
験したのでは量産されるICを全量試験することは到底
不可能である。このため高速化が要求される。
When determining the acceptability of a CMO3 structure IC by voltage application and current measurement test, although the current to be measured is a steady 1itt with a minute current value ILL as shown in Fig. 3, F E T Q At the time of switching between + and Qt states, a short circuit current having a t current value IFF several thousand to tens of thousands of times as large as ILL flows. In other words, the ratio of the short circuit current to the current to be measured I
PF/ILL becomes a very large value. By the way, ILL”
Several liters of microamperes to several nanoamperes, IFF”
It is several hundred milliamperes to several lθ milliamperes. t
In order to reduce the voltage drop at the V2O point while oo is IFF, a smoothing capacitor 9 is required, and for this reason, the current flowing through the current detection resistor 3 is increased from the point when the short circuit current ends, resulting in a small steady current. There is an inconvenience that it takes a long time to charge the current detection resistor 3 and the smoothing capacitor 9 until it stabilizes at the value ILL. In other words, if the time it takes for the current to stabilize becomes longer, the switching period of FETQl and Q2 must be longer. As a result, the time required for testing an IC with a large number of elements increases. For example 256
x 1 IC with 1000 logic gate elements integrated
If the test is performed by switching at millisecond intervals, the time required for the test will be 256 seconds. If one IC was tested for 256 seconds, it would be impossible to test all mass-produced ICs. Therefore, higher speed is required.

ここで従来技術で考えられる高速化のための構成を第5
図に示す。この第5図に示す回路は演算増幅器5の出力
端子を電流検出用抵抗器3を介して演算増幅器5の反転
入力端子に接続し、負帰還ループを構成すると共に演算
増幅器5の非反転入力端子に電圧源7を接続し、定電圧
源8を構成する。この定電圧源8の電圧を負荷2に供給
する。
Here, we will discuss the fifth configuration for speeding up that can be considered in the conventional technology.
As shown in the figure. In the circuit shown in FIG. 5, the output terminal of the operational amplifier 5 is connected to the inverting input terminal of the operational amplifier 5 via the current detection resistor 3, thereby forming a negative feedback loop, and the non-inverting input terminal of the operational amplifier 5. A voltage source 7 is connected to constitute a constant voltage source 8. The voltage of this constant voltage source 8 is supplied to the load 2.

この構造により演算増幅器5は反転入力端子の電圧が電
圧源7の電圧と等しくなるように帰還動作し、負荷2に
電圧源7の電圧と等しい一定電圧Vsを与える。負荷2
は先に説明したCMOS構造のICのように定常時は微
少電流しか流れずに、動作速度に比例した周期で大きな
パルス状の電流が流れる回路構造を持つものとする。
With this structure, the operational amplifier 5 performs a feedback operation so that the voltage at the inverting input terminal becomes equal to the voltage of the voltage source 7, and provides a constant voltage Vs equal to the voltage of the voltage source 7 to the load 2. load 2
Assume that the circuit has a circuit structure in which only a small current flows during a steady state, but large pulse-like currents flow at a period proportional to the operating speed, like the previously described CMOS IC.

負荷2の近くに平滑用コンデンサ9を接続する。A smoothing capacitor 9 is connected near the load 2.

この平滑用コンデンサ9は負荷2にパルス状の大電流が
流れるとき、定電圧源8の応答遅れによって発生する電
圧Vsの低下を補償するために設けられる。つまり第6
図Aに示すように負荷2にパルス状の電流が流れるとき
、負荷2への電流供給点Sにおける電圧Vsは第6図B
に示すように変化する。同図において曲線式は平滑用コ
ンデンサ9を接続しないときの電圧変動特性、曲線Bは
平滑用コンデンサ9を接続したときの電圧変動特性を示
す、平滑用コンデンサ9を接続したときの電圧変動値■
、はVr+blLt−t/CL(ItLは定常時の電流
値、tはパルス状電流のパルス幅)となる。
This smoothing capacitor 9 is provided to compensate for a drop in the voltage Vs caused by a delay in the response of the constant voltage source 8 when a large pulsed current flows through the load 2. In other words, the 6th
When a pulsed current flows through the load 2 as shown in Figure A, the voltage Vs at the current supply point S to the load 2 is as shown in Figure 6B.
Changes as shown in . In the figure, the curve formula shows the voltage fluctuation characteristics when the smoothing capacitor 9 is not connected, and the curve B shows the voltage fluctuation characteristics when the smoothing capacitor 9 is connected.The voltage fluctuation value when the smoothing capacitor 9 is connected.
, is Vr+blLt-t/CL (ItL is the current value at steady state, and t is the pulse width of the pulsed current).

一方電流検出用抵抗器3には並列にスイッチ素子11と
、逆並列接続された一対のダイオード12A。
On the other hand, the current detection resistor 3 is connected in parallel with a switch element 11 and a pair of diodes 12A connected in antiparallel.

12Bを並列接続する。これらスイッチ素子11とダイ
オード12A、1211は負荷8にパルス状電流が流れ
るとき、抵抗器3に大きな電圧降下が発生しないように
するために設けられる。従ってスイッチ素子11は第6
図Cに示すようにパルス状電流が流れる期間りを含む期
間Mの間オンに制御される。
Connect 12B in parallel. The switch element 11 and the diodes 12A and 1211 are provided to prevent a large voltage drop from occurring across the resistor 3 when a pulsed current flows through the load 8. Therefore, the switch element 11 is the sixth
As shown in Figure C, it is controlled to be on during a period M that includes a period during which a pulsed current flows.

スイッチ素子11は高速応答が可能でかつオン、オフ制
?■信号が回路に漏れなく、リーク電流の小さいものが
好ましいため一般にFETが用いられる。
Is the switch element 11 capable of high-speed response and on/off control? (2) FETs are generally used because signals do not leak into the circuit and it is preferable to have a small leakage current.

電流検出用抵抗器3には更に位相補償用コンデンサ13
が並列に接続される。この位相補償用コンデンサ13を
接続したことにより演算増幅器5の位相回転量を補償し
、不安定動作の防止とSN比の向上を達している。
The current detection resistor 3 further includes a phase compensation capacitor 13.
are connected in parallel. By connecting this phase compensation capacitor 13, the amount of phase rotation of the operational amplifier 5 is compensated for, thereby preventing unstable operation and improving the S/N ratio.

「発明が解決しようとする問題点」 ところで上述した回路構造によれば定電圧源8は帰還ル
ープを具備して(i還動作するものであるから出力イン
ピーダンスが低くなり、また平滑用コンデンサ9によっ
て負荷2に与えられる電圧の低下を阻止する構造となっ
ているため、かなり高い周波数のパルス状゛電流を供給
することができる。
"Problems to be Solved by the Invention" By the way, according to the above-mentioned circuit structure, the constant voltage source 8 is equipped with a feedback loop (i.e., operates in an i-return operation), so the output impedance is low, and the smoothing capacitor 9 Since it has a structure that prevents a drop in the voltage applied to the load 2, it is possible to supply a pulsed current with a considerably high frequency.

然し乍らパルス状電流の繰返し周波数を高めていくに従
ってパルス状電流の終了から電流が定常状態に戻るまで
の時間を短くしなければならない問題が生じる。つまり
ここでは定常状態における電流値ILLを測定すること
を目的とするものであるから、パルス状電流が終了した
時点から定常電流が流れる状態に戻った時点で定常状態
の電流を測定器4において測定しなければならない。従
ってパルス状電流の終了から定常電流に戻るまでの時間
によってパルス状電流を流し得る上限周波数が決まる。
However, as the repetition frequency of the pulsed current is increased, a problem arises in that the time from the end of the pulsed current until the current returns to a steady state must be shortened. In other words, since the purpose here is to measure the current value ILL in a steady state, the steady state current is measured by the measuring device 4 from the time when the pulsed current ends to the time when the state where the steady current flows returns. Must. Therefore, the upper limit frequency at which the pulsed current can flow is determined by the time from the end of the pulsed current until the current returns to the steady state.

第5図に示した回路ではパルス状電流が終了した時点か
ら電流が安定するまでの時間が比較的長く掛かる欠点が
ある。その理由を以下に説明する。
The circuit shown in FIG. 5 has the disadvantage that it takes a relatively long time from the point at which the pulsed current ends until the current stabilizes. The reason for this will be explained below.

第7図に第5図に示す回路の各部の電圧電流波形を示す
。第7図Aは負荷2に流れる負荷電流、第7図Bは平滑
用コンデンサ9の充放電電流を示す、つまりこの例では
−ICLを放電電流、+lCLを充電電流とする。
FIG. 7 shows voltage and current waveforms at various parts of the circuit shown in FIG. 5. 7A shows the load current flowing through the load 2, and FIG. 7B shows the charging and discharging current of the smoothing capacitor 9. That is, in this example, -ICL is the discharging current and +lCL is the charging current.

負荷2にパルス状電流が流れ始めると平滑用コンデンサ
9は放電電流−ICLを放出し、負荷2へ供給する電圧
Vs(第7図D)の低下を阻止するように動作する。ス
イッチ素子11はパルス状電流が流れ始めるタイミング
より前にオンにされている。
When a pulsed current begins to flow through the load 2, the smoothing capacitor 9 discharges a discharge current -ICL and operates to prevent the voltage Vs (FIG. 7D) supplied to the load 2 from decreasing. The switch element 11 is turned on before the pulsed current starts flowing.

パルス状電流が断になるとt’t (ir Q ’tM
 I t は直らに定常電流ILLに戻る。
When the pulsed current is cut off, t't (ir Q 'tM
I t immediately returns to the steady state current ILL.

ところでパルス状電流が流れるとき、このパルス状電流
は電流検出用抵抗器3と、ダイオード12Aと、スイッ
チ素子11と位相補償用抵抗器13とから成る並列回路
を通じて流れる。ダイオード12A及びスイッチ素子1
1はオン抵抗が存在する。つまり電流検出用抵抗器3の
両端間を完全にショート状態にすることはできない、こ
のため位相補償用コンデンサ13にはダイオード12A
及びスイッチ素子11のオン抵抗に発生する電圧が充電
される。この充電電流は出力インピーダンスが低い演算
増幅器5から与えられるためその充電時定数は極めζ小
さくコンデンサ13の両端に発生する電圧■。は第7図
已に示すように短い時間で所定の電圧MCIに達する。
By the way, when a pulsed current flows, this pulsed current flows through a parallel circuit consisting of the current detection resistor 3, the diode 12A, the switch element 11, and the phase compensation resistor 13. Diode 12A and switch element 1
1 has on-resistance. In other words, it is not possible to completely short-circuit both ends of the current detection resistor 3, so the phase compensation capacitor 13 has a diode 12A.
And the voltage generated in the on-resistance of the switch element 11 is charged. Since this charging current is given from the operational amplifier 5 with low output impedance, its charging time constant is extremely small and the voltage generated across the capacitor 13 is ζ. reaches the predetermined voltage MCI in a short time as shown in FIG.

これに対し、パルス状電流が断になると位相補償用コン
デンサ13に掛かる電圧は電流検出用抵抗器3に流れる
定常電流によって発生する電圧となる。この電圧はコン
デンサ13に充電された電圧VCIと比較すると非常に
小さい値となる。この結果コンデンサ13に充電された
’Qt荷はスイッチ素子11とダイオード12Aと抵抗
器3とから成る並列回路を通じて放電される。コンデン
サ13の充i電圧VCIがダイオード12Aを導通させ
るに充分な電圧値を持つときはダイオード12Aを通じ
て放電するが電圧の低下に伴ってダイオ−)”12Aは
漸次オン抵抗が大となりオフになる。結局ダイオード1
2Aがオフになった後はスイッチ素子11と抵抗器3を
通して放電が行われる。スイッチ素子11のオン抵抗値
をR02,抵抗器3の抵抗値をRHとし、その大小関係
がR1,N<R14であったとするとパルス状電流が立
下がった時点からスイッチ素子11がオフになるまでの
期間Ttにおける放電時定数はコンデンサ13の容量値
CHとスイッチ素子11のオン抵抗値R0、で決まる値
C1IxRHとなる。この時定数はスイッチ素子11の
オン抵抗が例えば100 Ω程度とすれば充電時の立上
り時定数より大きい値になる。
On the other hand, when the pulsed current is cut off, the voltage applied to the phase compensation capacitor 13 becomes the voltage generated by the steady current flowing through the current detection resistor 3. This voltage has a very small value compared to the voltage VCI charged in the capacitor 13. As a result, the 'Qt load charged in the capacitor 13 is discharged through a parallel circuit consisting of the switch element 11, the diode 12A, and the resistor 3. When the charging voltage VCI of the capacitor 13 has a voltage value sufficient to make the diode 12A conductive, it is discharged through the diode 12A, but as the voltage decreases, the on-resistance of the diode 12A gradually increases and it turns off. Diode 1 after all
After 2A is turned off, discharge occurs through the switch element 11 and the resistor 3. Assuming that the on-resistance value of the switch element 11 is R02 and the resistance value of the resistor 3 is RH, and the magnitude relationship is R1, N<R14, from the time when the pulsed current falls until the switch element 11 turns off. The discharge time constant during the period Tt becomes a value C1IxRH determined by the capacitance value CH of the capacitor 13 and the on-resistance value R0 of the switch element 11. If the on-resistance of the switch element 11 is, for example, about 100 Ω, this time constant has a value larger than the rise time constant during charging.

更に期間Tt後にスイッチ素子tiがオフになると、コ
ンデンサ13の放電路は抵抗器3だけとなる。
Furthermore, when the switch element ti is turned off after a period Tt, the only discharge path of the capacitor 13 is the resistor 3.

抵抗2ii3の抵抗値R,をtoo KΩに選定したと
するとその時定数はスイッチ素子11がオンの状態にお
ける時定数の1000倍の値となる。よってコンデンサ
13の電圧は第7図Eに期間Tsに示すように非常にゆ
っくりとした速度で低下していくこととなる。
If the resistance value R of the resistor 2ii3 is selected to be too KΩ, its time constant will be 1000 times the time constant when the switch element 11 is in the on state. Therefore, the voltage of the capacitor 13 decreases at a very slow rate as shown in period Ts in FIG. 7E.

コンデンサ13の放電電流が抵抗器3に流れている状態
で抵抗器3に発生している電圧を測定回路4において測
定し、抵抗器3に流れている電流値を測定したとすると
負ri12に流れる定常電流を正確に測定したとは言え
ない。
If the voltage generated across the resistor 3 is measured in the measuring circuit 4 while the discharge current of the capacitor 13 is flowing through the resistor 3, and the value of the current flowing through the resistor 3 is measured, the current flowing through the negative ri 12 It cannot be said that the steady current was accurately measured.

このためコンデンサ13の放電時間を短くすることが要
求される。コンデンサ13の放電時間を短くするために
はコンデンサ13の容N値C,を小さくするか、又は電
流積゛出用砥抗器3の抵抗値R1を小さく選定するかの
何れか一方、又は双方を小さくすること、或いはスイッ
チ素子11のオン抵抗値ROMを充分小さくすることで
実現できる。
Therefore, it is required to shorten the discharge time of the capacitor 13. In order to shorten the discharging time of the capacitor 13, one or both of the following can be done: reduce the capacitance N value C of the capacitor 13, or select a smaller resistance value R1 of the current accumulating grinder 3. This can be realized by reducing the on-resistance value ROM of the switching element 11 to a sufficiently small value.

然し乍ら電流検出用抵抗器3の抵抗値r1.の値は微少
電流を電圧として取出す条件を満たすためには小さくす
ることはできない。
However, the resistance value r1. of the current detection resistor 3. The value of cannot be made small in order to satisfy the conditions for extracting a minute current as a voltage.

またスイッチ素子11のオン抵抗値ROMはスイッチ素
子11としてリーク電流が小さく、オンオフ制御信号が
回路に漏れないようなFETを利用する限りにおいては
そのオン抵抗は数Ω〜数十Ω程度が下限でありこれ以上
小さいオン抵抗のスイッチ素子を求めることはできない
In addition, as long as the on-resistance value ROM of the switch element 11 is used as a switch element 11 with a small leakage current and an FET that prevents on-off control signals from leaking into the circuit, the lower limit of the on-resistance is about several ohms to several tens of ohms. However, it is impossible to find a switch element with a smaller on-resistance than this.

このような理由から最終的にコンデンサ13の放電時定
数を小さくするためにはコンデンサ13の容量値を小さ
く選定する方法でしか解決することはできない。然し乍
らコンデンサ13の容量値C8を小さく選定すると定電
圧源8を構成する閉ループの安定性が悪くなり負荷2に
流れるパルス状電流の繰返し周波数を高くした場合定電
圧源8が発振したりする不安定な状態となる。
For these reasons, the only way to ultimately reduce the discharge time constant of the capacitor 13 is to select a small capacitance value for the capacitor 13. However, if the capacitance value C8 of the capacitor 13 is selected to be small, the stability of the closed loop that constitutes the constant voltage source 8 will deteriorate, and if the repetition frequency of the pulsed current flowing through the load 2 is increased, the constant voltage source 8 may oscillate or become unstable. It becomes a state.

負荷2が予め一定条件で動作するものと規定される場合
はその条件下で安定に動作するようにコンデンサ13の
容量、平滑用コンデンサ9の容量、演算増幅器の周波数
特性等を適当に設定することはできる。然し乍ら汎用試
験器として動作させるには負荷の条件が変わることを想
定し、可及的に広い範囲特に負荷の駆動周波数の変化に
対して安定に動作するように作らなければならない。
If the load 2 is specified in advance to operate under certain conditions, the capacitance of the capacitor 13, the capacity of the smoothing capacitor 9, the frequency characteristics of the operational amplifier, etc. should be appropriately set so that it operates stably under those conditions. I can. However, in order to operate as a general-purpose tester, it must be designed to operate stably over as wide a range as possible, especially against changes in the load drive frequency, assuming that the load conditions will change.

換言すれば負荷2には先に説明したようにパルス状の電
流が流れるためパルス状の電流が流れるとき供給電圧の
低下を低く 1rliえるためには比較的大きい容量値
を持つ平滑用コンデンサ9がどうしても必要となる。
In other words, as explained earlier, a pulsed current flows through the load 2, so in order to keep the drop in supply voltage as low as 1rli when a pulsed current flows, the smoothing capacitor 9 with a relatively large capacitance value is required. It is absolutely necessary.

負荷2に対して大きい容量値を持つ平滑用コンデンサ1
3が並列接続さたとき、定電圧tA8から負荷2を見た
場合容量性負荷として見える。このためパルス状に流れ
る電流の周波数が高い周波数になるに伴って負荷のイン
ピーダンスは徐々に小さくなっていく傾向となる。この
結果成る周波数以上になると負荷のインピーダンスがゼ
ロに近すき、定電圧源8の動作が不安定な状態となる。
Smoothing capacitor 1 with a large capacitance value for load 2
3 are connected in parallel, when load 2 is viewed from constant voltage tA8, it appears as a capacitive load. Therefore, the impedance of the load tends to gradually decrease as the frequency of the current flowing in a pulsed manner increases. When the frequency exceeds this result, the impedance of the load approaches zero, and the operation of the constant voltage source 8 becomes unstable.

「問題点を解決するための手段」 この発明では定電圧源の出力端子と平滑用コンデンサを
含む負荷との間に減結合用抵抗器を直列に挿入する構成
としたものである。
"Means for Solving the Problems" In the present invention, a decoupling resistor is inserted in series between the output terminal of a constant voltage source and a load including a smoothing capacitor.

このように減結合用抵抗器を定電圧源と負荷との間に直
列に挿入したことにより定電流源8から負荷を見たとき
減結合用抵抗器が負荷と直列接続されて見える。この結
果平滑用コンデンサのインピーダンスがパルス状電流の
繰返し周波数の変更によって小さくなっても、減結合用
抵抗器のインピーダンスが存在するため負荷側のインピ
ーダンスが限りなくゼロに近ずくことはない。
By inserting the decoupling resistor in series between the constant voltage source and the load in this manner, when the load is viewed from the constant current source 8, the decoupling resistor appears to be connected in series with the load. As a result, even if the impedance of the smoothing capacitor is reduced by changing the repetition frequency of the pulsed current, the impedance on the load side will never approach zero because of the presence of the impedance of the decoupling resistor.

よって負荷に流れるパルス状電流の繰返し周波数が従来
の上限値より高くなっても定電圧源8の動作が不安定な
状態におちいるおそれがない、つまり平滑コンデンサの
インピーダンスが低下することの影響が軽減されるから
位相補償用コンデンサの容量値を小さく設定することが
できる。
Therefore, even if the repetition frequency of the pulsed current flowing through the load becomes higher than the conventional upper limit value, there is no risk that the operation of the constant voltage source 8 will become unstable. In other words, the effect of a decrease in the impedance of the smoothing capacitor is reduced. Therefore, the capacitance value of the phase compensation capacitor can be set small.

位相補償用コンデンサの容量値を小さくできることから
パルス状電流の立下りから比較的短時間の間に位相補償
用コンデンサに蓄えられた電荷を放電させることができ
る。この結果パルス状電流の立下りから定常電流を測定
するまでの時間を短縮することができるため、パルス状
電流の繰返し周波数を高く設定することができ、それに
伴って高速試験が可能となる。
Since the capacitance value of the phase compensation capacitor can be made small, the charge stored in the phase compensation capacitor can be discharged within a relatively short time after the pulsed current falls. As a result, the time from the fall of the pulsed current to the measurement of the steady current can be shortened, so the repetition frequency of the pulsed current can be set high, thereby enabling high-speed testing.

「実施例」 第1図にこの発明による電圧印加電流測定装置の一実施
例を示す、第1図において第5図と対応する部分には同
一符号を付し、その重複する部分の説明は省略するが、
この発明においては定電圧源8と負荷2及び平滑用コン
デンサ9の接続点との間に直列に減結合用抵抗器15を
接続した構造を特徴とするものである。
"Example" Fig. 1 shows an embodiment of the voltage applied current measuring device according to the present invention. In Fig. 1, parts corresponding to Fig. 5 are denoted by the same reference numerals, and explanations of the overlapping parts are omitted. But,
This invention is characterized by a structure in which a decoupling resistor 15 is connected in series between the constant voltage source 8 and the connection point between the load 2 and the smoothing capacitor 9.

減結合用抵抗″a15は平滑用コンデンサ9の容量値が
約O91マイクロファラドの場合10オ一ム程度となる
The decoupling resistor "a15" is about 10 ohms when the capacitance value of the smoothing capacitor 9 is about 091 microfarads.

「発明の作用効果」 このように減結合用抵抗器15を設けたことによりパル
ス状電流の繰返し周波数が各種変更されても定電圧#8
から負荷2側を見たインピーダンスの変化量が小さくな
る。特にパルス状電流の繰返し周波数を高い周波数にし
た場合、平滑用コンデンサ9のインピーダンスは限りな
くゼロに近ずくが減結合用抵抗器15のインピーダンス
は周波数の変化に依存せずに不変であるため定電圧aa
から見た負荷インピーダンスは一定に見ることができる
"Operations and Effects of the Invention" By providing the decoupling resistor 15 in this way, even if the repetition frequency of the pulsed current is variously changed, the constant voltage #8 can be maintained.
The amount of change in impedance when looking at the load 2 side becomes smaller. In particular, when the repetition frequency of the pulsed current is set to a high frequency, the impedance of the smoothing capacitor 9 approaches zero, but the impedance of the decoupling resistor 15 remains constant regardless of changes in frequency. voltage aa
The load impedance seen from can be seen as constant.

よって定電圧源8は高い周波数に対しても負荷の条件が
一定に見えるようになり、この結果として位相補償用コ
ンデンサ13の容量値を小さく選定することができるよ
うになるため、位相補償用コンデンサ13と電流検出用
抵抗器3との時定数を小さくすることができる。よって
パルス状電流の立下りから位相補償用コンデンサ13の
電荷が放電されるまでの時間を短くすることができ、高
速度の試験を実行できる。
Therefore, the load condition of the constant voltage source 8 appears constant even at high frequencies, and as a result, the capacitance value of the phase compensation capacitor 13 can be selected to be small. 13 and the current detection resistor 3 can have a small time constant. Therefore, the time from the fall of the pulsed current until the charge in the phase compensation capacitor 13 is discharged can be shortened, and high-speed testing can be performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を説明するための接続図、
第2図は電圧印加電流測定試験を行う被試験対象の一例
を説明するための接続図、第3図は被試験対象に流れる
電流波形を示す波形図、第4図は第2図で説明した被試
験対象に流れる電流を測定する構成を説明する接続図、
第5rjJは従来の電圧印加電流測定′jt¥fを説明
するための接続図、第6図及び第7図は第5図の動作を
説明するための波形図である。 2:負荷、3:電流検出用抵抗器、4:電流測定器、5
:演算増幅器、7:電圧源、8:定電圧源、9:平滑用
コンデンサ、11:スイソチ素子、12A、 12B 
:ダイオード、15:減結合用抵抗器。 特許出願人  タケダ理研工業株式会社代  理  人
    草  野     車士 1 区 オ 2図 オ6図 り、MJ 士5図
FIG. 1 is a connection diagram for explaining one embodiment of the present invention,
Figure 2 is a connection diagram to explain an example of the object under test that performs a voltage applied current measurement test, Figure 3 is a waveform diagram showing the current waveform flowing through the object under test, and Figure 4 is the same as explained in Figure 2. A connection diagram explaining the configuration for measuring the current flowing through the object under test,
5rjJ is a connection diagram for explaining the conventional voltage application current measurement 'jt\f, and FIGS. 6 and 7 are waveform diagrams for explaining the operation of FIG. 5. 2: Load, 3: Current detection resistor, 4: Current measuring device, 5
: Operational amplifier, 7: Voltage source, 8: Constant voltage source, 9: Smoothing capacitor, 11: Swiss element, 12A, 12B
: Diode, 15: Decoupling resistor. Patent Applicant: Takeda Riken Kogyo Co., Ltd. Representative: Kusano, Vehicle Engineer 1, 2, 6, MJ, 5

Claims (1)

【特許請求の範囲】[Claims] (1)A、周期的に大きな値の負荷電流を消費する負荷
に対して一定電圧を与えるように帰還回路を具備した定
電圧源と、 B、この定電圧源から上記負荷に流れる電流を測定する
ための電流検出用抵抗器と、 C、この電流検出用抵抗器に並列接続され上記定電圧源
を流れる負荷電流によって定電圧源が不安定動作となる
ことを阻止する位相調整用コンデンサと、 D、上記負荷に並列接続され負荷電流の変動に対して負
荷に与える電圧を安定化する平滑用コンデンサと、 E、上記電流積出用抵抗器の両端を大きな負荷電流が流
れる期間中短絡するためのスイッチ素子と、 F、上記定電圧源の出力端子と上記負荷及び平滑用コン
デンサの接続点の間に直列に挿入した減結合用抵抗器と
、 から成る電圧印加電流測定装置。
(1) A: A constant voltage source equipped with a feedback circuit to provide a constant voltage to a load that periodically consumes a large value of load current; B: Measure the current flowing from this constant voltage source to the load. C. a phase adjustment capacitor connected in parallel to the current detection resistor to prevent the constant voltage source from becoming unstable due to the load current flowing through the constant voltage source; D. A smoothing capacitor connected in parallel to the above load to stabilize the voltage applied to the load against fluctuations in load current, and E. To short-circuit both ends of the above current output resistor during periods when a large load current flows. A voltage applied current measuring device comprising: a switching element; and F, a decoupling resistor inserted in series between the output terminal of the constant voltage source and the connection point of the load and smoothing capacitor.
JP60157267A 1985-07-17 1985-07-17 Apparatus for measuring current through voltage application Granted JPS6217666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60157267A JPS6217666A (en) 1985-07-17 1985-07-17 Apparatus for measuring current through voltage application

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60157267A JPS6217666A (en) 1985-07-17 1985-07-17 Apparatus for measuring current through voltage application

Publications (2)

Publication Number Publication Date
JPS6217666A true JPS6217666A (en) 1987-01-26
JPH0380266B2 JPH0380266B2 (en) 1991-12-24

Family

ID=15645919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60157267A Granted JPS6217666A (en) 1985-07-17 1985-07-17 Apparatus for measuring current through voltage application

Country Status (1)

Country Link
JP (1) JPS6217666A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382377A (en) * 1986-09-26 1988-04-13 Hitachi Electronics Eng Co Ltd Current measuring circuit
US5163403A (en) * 1990-12-28 1992-11-17 Honda Giken Kogyo Kabushiki Kaisha Ignition timing control system for internal combustion engines
US5201383A (en) * 1990-12-28 1993-04-13 Honda Giken Kogyo Kabushiki Kaisha Ignition timing control system for internal combustion engines
JPH09236637A (en) * 1996-02-29 1997-09-09 Advantest Corp Voltage application current measuring circuit
DE19746113C2 (en) * 1996-10-18 2000-08-10 Advantest Corp Power supply circuit
JP2010019840A (en) * 2008-07-11 2010-01-28 Advantest Corp Measuring device, testing device, measuring method
WO2024192317A1 (en) * 2023-03-16 2024-09-19 Texas Instruments Incorporated Methods and apparatus for source measurement unit (smu) operation

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382377A (en) * 1986-09-26 1988-04-13 Hitachi Electronics Eng Co Ltd Current measuring circuit
US5163403A (en) * 1990-12-28 1992-11-17 Honda Giken Kogyo Kabushiki Kaisha Ignition timing control system for internal combustion engines
US5201383A (en) * 1990-12-28 1993-04-13 Honda Giken Kogyo Kabushiki Kaisha Ignition timing control system for internal combustion engines
JPH09236637A (en) * 1996-02-29 1997-09-09 Advantest Corp Voltage application current measuring circuit
DE19746113C2 (en) * 1996-10-18 2000-08-10 Advantest Corp Power supply circuit
JP2010019840A (en) * 2008-07-11 2010-01-28 Advantest Corp Measuring device, testing device, measuring method
WO2024192317A1 (en) * 2023-03-16 2024-09-19 Texas Instruments Incorporated Methods and apparatus for source measurement unit (smu) operation

Also Published As

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