JPS62160750A - Substrate-voltage generating circuit - Google Patents

Abstract

PURPOSE:To reduce a forward voltage, to reduce the number of elements and to obtain sufficiently low voltage, by forming an excellent substrate-voltage generating circuit in a CCD, by existing unified process of a CMOS process and a CCD process. CONSTITUTION:A P-N diode 23 is formed by a CMOS well 12 and a diffused layer 13, which is formed by source and drain regions. Only when an input pulse, which is applied to a pulse input terminal 26, is at a high level, a MOS switch 24 is conducted. Thus a voltage, which is obtained from the anode side of the diode 23, is imparted to a substrate 11. The diode 23 is formed by the CMOS well 12 and the diffused layer 13 of the source and drain regions and accommodated in the same semiconductor substrate as a charge transfer device by a unified process. By using the P-N junction diode in this way, the substrate- voltage generating circuit having excellent characteristics, can be formed on the semiconductor substrate, which is the same as the CCD, with the small number of elements.

Description

[Detailed description of the invention] The present invention relates to a substrate voltage generation circuit for a charge coupled device.

[Background of the invention]

When driving a charge-coupled device (hereinafter abbreviated as COD) with a low voltage of about 5V, the COD can be activated by applying a negative voltage to the substrate when the substrate is P-type and a positive voltage when it is N-type from the substrate voltage generation circuit. Wider channel electric field LCD
transfer efficiency can be increased. This fact is well known to those in the industry.

FIG. 4 shows an example of a substrate voltage generating circuit for a P-type substrate and signal waveforms at each point. 21.22 is a capacitor, 23 is a diode-connected MOS transistor, 24 is an NMOS
switch, 25 is a voltage source, 26 is a pulse input terminal, 2
7 is a control terminal of the switch, and 28 is a terminal for generating a substrate voltage, which is connected to the substrate. Connection point 'k of capacitor 21, diode-connected MOS transistor 23, and switch 24
Set it as point A.

Crying AM A blind Senko Masu r Ren pole 97 Hescanus line meeting terminal 26
The period is the same as that of the input pulse, but the phase is slightly advanced. The voltage of the voltage source 25 is vB, and the amplitude of the pulse that applies the potential of the output terminal 28 to the Vsuba input terminal is vP.
, the potential at the first point A is l/+.

The operation will be explained assuming that the forward voltage drop (threshold voltage) kVAx of the diode-connected transistor 23 (MO9) transistor 23 is expressed.

At time t+, the pulse applied to terminal 26 falls from high level to low level. At that time, the potential at point A is Vi
Vp: becomes v2. If the potential v2 is lower than the potential V sub by more than the threshold voltage of the diode 23, the potential at point A via the diode 23 becomes (Vsub
-VAN ), the current flows until it becomes equal to capacitor 2
2 to lower the potential at terminal 28.

In other words, depending on the ratio of capacitor 21 and capacitor 22, h
The potential at the point increases and the potential at the terminal 28 decreases.

The potential v2 at point A at this time is (V sub -VAK).

Furthermore, since the MOS switch applies a pulse that makes the pulse input to the terminal 27 go low before the pulse at the terminal 26 falls, it is turned off and no current flows.

Next, suppose that the pulse at the terminal 27 rises at time t2, and then the pulse at the terminal 26 rises. Since the MOS switch 24 is on, current flows and changes the potential at point A to V.
aK. When the pulse falls again at time ti, the potential at point A becomes (vB-Vp).

When the potential of the terminal 28 is lower than the threshold voltage of the diode 23, a current flows and lowers the potential of the terminal 28. This operation is repeated until Vsub becomes (Va+VAK-Vp). This voltage can be varied by changing the substrate voltage JMn.

As a method for realizing the diode 23 constituting this circuit, Japanese Unexamined Patent Publication No. 123126/1983 discloses an MO
An S transistor whose gate and drain are connected is used. However, the forward voltage Va of the MOS) Lancistor is
S is larger than a normal PN diode, making it difficult to generate a low voltage.

Another method of configuring a circuit without using this is to use a second MOS transistor 9 instead of the diode-connected MOS transistor 23.
There is a method using a switch. However, this method requires other drive pulses and increases the number of elements. Also, there is a possibility that the lease and drain voltages are negative and therefore cannot be turned off sufficiently.

[Purpose of the invention]

An object of the present invention is to provide an excellent substrate voltage generation circuit for COD using only existing elements through an integrated process of OMO8 and COD.

[Summary of the invention]

In the present invention, in the substrate voltage generation circuit, the 0MO8 well, the lease, and the diffusion layer formed in the drain region have a PN
By configuring a diode, the forward voltage can be made smaller than when a conventional MOS transistor is used in diode connection, the number of elements is small, and a sufficiently low voltage can be obtained.

[Embodiments of the invention]

FIG. 5 shows an example of the configuration of a diode used in the present invention. 11 is a semiconductor substrate, and 12 is a well.

13 is a diffusion layer. Also, 16 is the number of 0MO8
17L + 1QL) / L-circle h 40 is the embedded channel of COD, 10 is the input diffusion layer, 1
01 is a gate electrode. The well 12 and diffusion layer 13 constituting the diode are the well 16 and diffusion layer 1 of 0MO8.
7 can be formed at the same time. When the substrate is a P-type semiconductor, the well is N-type, the diffusion layer is P-type, terminal 14 is a cathode, and terminal 15 is an anode. If the substrate is of N type, the configuration can be reversed.

FIG. 1 shows a configuration in which the substrate voltage generation circuit shown in FIG. 4 is constructed using this, that is, a sectional view of the configuration of an embodiment of the present invention. A case where the substrate is a P-type semiconductor will be explained. 31.32 is an N type diffusion layer.

33 is the gate of a MOS transistor, and 34 is a delay circuit, which can be easily realized using a gate delay or the like.

35 is a pulse input terminal, 36 is an input diffusion layer of the COD, 37 is a buried channel of the COD, and 3 is a gate electrode of the COD. The COD portion is omitted.

Components with the same reference numerals as in FIGS. 4 and 5 have the same functions. Regarding the pulses applied to the terminals 26 and 27 via the pulse input terminal 35, the delay circuit 34 causes the pulse applied to the terminal 26 to have a later phase than the pulse applied to the terminal 27. The operation of the circuit is as explained above.
By constructing a PN junction diode using a 9CMO3 well and a diffusion layer, a substrate voltage generation circuit with good characteristics can be realized with a small number of elements on the same semiconductor substrate as the COD. Further, in order to improve the switching characteristics of the MOS switch 24, it can be made into a buoy presilane type. In that case, when forming the buried channel 37t under the COD gate electrode 3B, it should be formed under the gate 33 at the same time.
The OS switch 24 can be of a dipleg type.

In this configuration, when the pulse at the terminal 35 falls, the potential of the well 12 and the diffusion layer 31 becomes low, and current may flow from the substrate 11.

However, the current flows from the capacitor 22 through the terminal 28 and through the substrate 11 to the well 12 or the diffusion layer 31, so it has the same function as a PN diode formed by the well 12 and the diffusion layer 13, and the substrate voltage has been sufficiently lowered. There is no adverse effect other than that the potential difference at that point becomes a small value.

Furthermore, a diode can be used instead of the MOS switch 24. The circuit diagram is shown in FIG.

41 is a diode provided in place of the MOS switch.

FIG. 3 shows the structure of this circuit on a semiconductor substrate, another embodiment of the present invention. This is an example of a P-type semiconductor substrate.51
52 is an N-type well, and 52 is a P-type diffusion layer. Components with the same symbols as in FIG. 1 have the same functions. The operation was previously controlled by a MOS switch, but current is now automatically caused to flow based on the potential difference between both ends of the diode. Therefore, switching pulses are not required, and the number of elements can be reduced.

However, during a transient period when the operation of the circuit is not sufficiently advanced, the diode 41 conducts and the current flows from the diffusion layer 52 to the well 51.
When current flows to the substrate, since a PNP transistor is formed between the substrate and the substrate, the current may flow toward the substrate and cause latch-up.

For this purpose, the well 51 is used to prevent potential fluctuations in the substrate.
By providing a low-resistance contact with the terminal 28 around the periphery of the diode 41, it is possible to absorb the current flowing through the substrate into the terminal and to separate the N-type region from the periphery of the diode 41, making it possible to form a PN junction diode.

Although an example using a P-type semiconductor substrate has been described above, the substrate voltage generation circuit can be constructed in the same manner in the case of an N-type substrate.

[Effects of the Invention j] According to the present invention, it is possible to obtain a substrate voltage generation circuit having good performance in 9CCD and COD by using the existing integrated process of CMOS process and CCD process.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the structure of one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a substrate generation circuit, and FIG. 3 is a sectional view of the structure of another embodiment of the invention. FIG. 4-) is a circuit diagram showing an example of a conventionally known substrate voltage generation circuit, FIG.・Semiconductor substrate, 12.5
1... Well, 13°52... Diffusion layer, 21.22
...Capacitor, 23゜41...Diode, 24
...MOS switch. Jiuhitose 11I 11 nails 111 隨 dan'A
1 Figure 'J2 Kuchi Atsushi 5 (¥] !34 Figure (Q) Cb) Discussion 5 Figure '+ Hikimoto intrusion

Claims (1)

[Claims] 1) A substrate voltage generation circuit for generating a voltage to be applied to a substrate constituting a charge transfer device, which includes a capacitor having one end as a pulse input terminal and the other end connected to the cathode of a diode and one end of a switch, and the switch. a voltage source connected to the other end, and a smoothing capacitor connected to the anode of the diode, and only when the input pulse applied to the pulse input terminal is at a high level;
The switch is made conductive so that a voltage obtained from the anode side of the diode is applied to the substrate, and the diode is constituted by a CMOS well and a diffusion layer of a source/drain region, and the charge transfer device A substrate voltage generation circuit characterized in that it is housed on the same semiconductor substrate through an integration process.