JPS62169585U - - Google Patents
Info
- Publication number
- JPS62169585U JPS62169585U JP1986056213U JP5621386U JPS62169585U JP S62169585 U JPS62169585 U JP S62169585U JP 1986056213 U JP1986056213 U JP 1986056213U JP 5621386 U JP5621386 U JP 5621386U JP S62169585 U JPS62169585 U JP S62169585U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- switch means
- tuner circuit
- input terminal
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図、第２図、第３図は本考案の一実施例を
示す概略図である。第４図、第５図、第６図は従
来例を示す図である。第７図はマルチケーブルを
示す図である。
１４……チユーナ回路、１６……映像信号処理
回路、ｂ……２０番端子（映像信号入力端子）、
ａ……１９番端子（映像信号出力端子）、３０…
…第１スイツチ（第１スイツチ手段）、３２……
第２スイツチ（第２スイツチ手段）。
FIGS. 1, 2, and 3 are schematic diagrams showing an embodiment of the present invention. FIG. 4, FIG. 5, and FIG. 6 are diagrams showing conventional examples. FIG. 7 is a diagram showing a multi-cable. 14...Tuner circuit, 16...Video signal processing circuit, b...Terminal 20 (video signal input terminal),
a...Terminal 19 (video signal output terminal), 30...
...first switch (first switch means), 32...
Second switch (second switch means).
Claims (1)
号入力端子と、映像信号出力端子とを、備えるス
クランブル放送受信用ＶＴＲに於いて、 前記映像信号処理回路から出力された映像信号
と前記チユーナ回路から出力された映像信号とを
選択的に前記映像信号出力端子に供給する第１ス
イツチ手段と、 前記チユーナ回路から出力された映像信号と前
記映像信号入力端子からの映像信号とを選択的に
前記映像信号処理回路に供給する第２スイツチ手
段とを、備え、 スクランブル放送受信時に前記第１スイツチ手
段は前記チユーナ回路からの映像信号を選択し、
前記第２スイツチ手段は前記映像信号入力端子か
らの映像信号を選択することを、 特徴とするスクランブル放送受信用ＶＴＲ。[Claims for Utility Model Registration] In a VTR for receiving scrambled broadcasting, which includes a tuner circuit, a video signal processing circuit, a video signal input terminal, and a video signal output terminal, a first switch means for selectively supplying the video signal and the video signal output from the tuner circuit to the video signal output terminal; and the video signal output from the tuner circuit and the video signal from the video signal input terminal. and second switch means for selectively supplying the video signal to the video signal processing circuit, and when receiving scrambled broadcasting, the first switch means selects the video signal from the tuner circuit,
A VTR for receiving scrambled broadcasting, wherein the second switch means selects a video signal from the video signal input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986056213U JPH0453098Y2 (en) | 1986-04-15 | 1986-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986056213U JPH0453098Y2 (en) | 1986-04-15 | 1986-04-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169585U true JPS62169585U (en) | 1987-10-27 |
| JPH0453098Y2 JPH0453098Y2 (en) | 1992-12-14 |
Family
ID=30884823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986056213U Expired JPH0453098Y2 (en) | 1986-04-15 | 1986-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453098Y2 (en) |
-
1986
- 1986-04-15 JP JP1986056213U patent/JPH0453098Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0453098Y2 (en) | 1992-12-14 |
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