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JPS62158338A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62158338A
JPS62158338A JP60299425A JP29942585A JPS62158338A JP S62158338 A JPS62158338 A JP S62158338A JP 60299425 A JP60299425 A JP 60299425A JP 29942585 A JP29942585 A JP 29942585A JP S62158338 A JPS62158338 A JP S62158338A
Authority
JP
Japan
Prior art keywords
chip
bonding
wire
bonding wires
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60299425A
Other languages
Japanese (ja)
Inventor
Hisao Arai
久夫 新井
Taiyo Yamamoto
山本　太洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP60299425A priority Critical patent/JPS62158338A/en
Publication of JPS62158338A publication Critical patent/JPS62158338A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/43—Manufacturing methods
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/438—Post-treatment of the connector
    • H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable a semiconductor device to be inexpensively manufactured, by coupling an IC chip, a soldering bump, and conductors through bonding wires which are formed by coating a core material of high-purity copper with solder plating. CONSTITUTION:Conductors 8 are connected with an IC chip 10 through bonding wires 12, to couple the IC chip 10 and a lead pin 5. The bonding wires 12 are formed by coating a core material 12a, which is trimmed into a Cu wire of 30X in diameter by repeating wire-drawing processes and intermediate heat treatment of the high-purity copper, with solder plating 3. And, they are made to adhere to bonding leads 8a of the conductors 8 and the soldering bump 9 of the IC chip 10 by thermal pressing or supersonic bonding method or the like. Because the conductors 8 and the bonding wires 12 are coated with the solder plating 3 in this way and besides the soldering bump 9 is also formed on the side of the IC chip 10, adhesion strength of the bonding wires is further enhanced.

Description

【発明の詳細な説明】 （産業上の利用分計） 本発明はＩＣソケット等に実装される半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention relates to a semiconductor device mounted in an IC socket or the like.

（従来の技術とその問題点） 半導体装１ｉ１ｔハ、回路基板の上面に多数配列形成さ
れた導線とマウント部に塔載されたＩＣチップ及びこれ
ら４腺とＩＣチップを連結するボンディング用線とによ
シ形成され、前記導線は銅で形成されたものに導電性の
優れたニッケルメッキ及び金メッキを施して形成されて
いるＱまたボンディング用線も高純度金を線引加工と中
間熱処理とをくシ返して直径器μの金線に形成したもの
を使用している。(Prior art and its problems) The semiconductor device 1i1t has a large number of conductive wires arranged on the top surface of the circuit board, an IC chip mounted on the mount part, and bonding wires connecting these four wires and the IC chip. The conductive wire is made of copper and plated with nickel and gold, which have excellent conductivity.QAlso, the bonding wire is made of high-purity gold that undergoes drawing processing and intermediate heat treatment. A piece of gold wire with a diameter μ diameter is used.

以上の様に半導体装置におけるは□とんどの部分に金が
使用されているため、経済的に高価でめった。As mentioned above, since gold is used in most parts of semiconductor devices, it is economically expensive and rare.

（発明が解決しようとする技術的課題）以上の問題を解
決しようとする本発明の技術的課題は、半導体装置にお
いて、金メッキが施されている部分を金にかわる金より
も安価な材質で形成することである０ （技術的課題を達成するための技術的手段）以上の技術
的課題を達成するだめの本発明の技術的手段は、ＩＣチ
ップと導線のポンディ／ブリードとをボンディング用線
を介して連結した半導体装置において、前記ＩＣチップ
に半田バンプを形成すると共に、導線を半田メッキで被
覆し、これらＩＣチップの半田バンプと導線とを高純度
鋼の芯材に半田メッキを被覆して形成したボンディング
用線を介して連結することである・ （作　用） 而して、上記構成によれば、半田メッキで被覆された高
純度鋼のボンディング用線は、半田メッキが被覆された
導線のボンディングリードと半田バンプが形成されたＩ
Ｃチップとにわたって強固に連結される。(Technical Problem to be Solved by the Invention) A technical problem to be solved by the present invention is to form the gold-plated portion of a semiconductor device with a material that is cheaper than gold instead of gold. 0 (Technical Means for Achieving the Technical Problem) The technical means of the present invention to achieve the above technical problem is to connect the IC chip and the conductive wire bonding/bleeding with the bonding wire. In the semiconductor device connected through the IC chip, solder bumps are formed on the IC chip, and the conductive wire is coated with solder plating, and the solder bumps of the IC chip and the conductive wire are coated with the solder plating on a core material of high-purity steel. (Function) According to the above configuration, the bonding wire made of high purity steel coated with solder plating is connected via the formed bonding wire. I with bonding leads and solder bumps formed
It is firmly connected to the C chip.

（発明の前動） 本発明は以上の様な構成にしたことによシ下記の効果を
有する。(Preliminary Act of the Invention) The present invention has the following effects due to the above configuration.

■　導線と、ボンディング用線を高純度鋼の芯材に半田
メッキを被覆して形成したので半導体装置を安価に製造
することができる◇■　ボンディング用線を半田で被覆
することにより、該ボンディング用線の接着強度を増す
ことができる。■ Conductor wires and bonding wires are formed by coating a high-purity steel core with solder plating, making it possible to manufacture semiconductor devices at low cost.◇ ■ By coating the bonding wires with solder, the bonding wires can be coated with solder plating. It can increase the bonding strength of the wire.

（実施例） 以下、本発明の一実施例を図面によシ説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.

図中囚は本発明の半導体装置であり、該半導体装置（至
）は、セラミック、ガラスエポキン樹脂等でのプラスチ
ック等で形成された基板（１）に多数の取付孔（２）が
開穿され、その内面に鋼メッキ（２ａ）及び半田メッキ
（３）カ施されスルホール部（４）が形成され、該スル
ホール部（４）にリードピ／（５）が嵌入され、半田に
より固着されている。The cap in the figure is a semiconductor device of the present invention, and the semiconductor device (to) has a large number of mounting holes (2) drilled in a substrate (1) made of ceramic, glass-epoxy resin, plastic, etc. Steel plating (2a) and solder plating (3) are applied to the inner surface to form a through hole portion (4), and a lead pin (5) is fitted into the through hole portion (4) and fixed by solder.

また、基板（１）の上面には一端が前記リードビ／（５
）と接続されると共に他端のボンディングリード（８ａ
）がマウント部（７）に臨んだ導線（８）が多数配列形
成され、該マウント部（７）には上面に半田バンプ（９
）が形成されたＩＣチップ（ト）が塔載され又いる。Further, one end of the upper surface of the substrate (1) is connected to the lead wire/(5).
) and the other end bonding lead (8a
) facing the mount part (7), a large number of conductive wires (8) are formed in an array, and the mount part (7) has solder bumps (9) on the top surface.
) is mounted on the tower.

該導線（８）は基板（１）上面に適宜厚さの銅箔及び鋼
メッキを施して銅メツキ層を形成するメッキ工程と、前
記メッキ層にフォートレジスト印刷のレジスト塗布処理
、バター７合せ・露光処理。The conductive wire (8) is formed by a plating process in which copper foil and steel plating of an appropriate thickness is applied to the upper surface of the substrate (1) to form a copper plating layer, a resist coating process of Fortresist printing is applied to the plated layer, and a butter 7 combination process is performed. Exposure processing.

現象−焼付処理を行なってパターンを形成するパターン
形成と、該パターン形成がされた基板（１）をエツチン
グ溶液に浸漬して食刻部を食刻剥離するエツチング工程
によ）形成されて、半田メッキ（３）が被覆される。Phenomenon - A pattern is formed by performing a baking process to form a pattern, and an etching process in which the substrate (1) on which the pattern is formed is immersed in an etching solution and the etched portion is peeled off) is formed and the solder is removed. Plating (3) is applied.

また、該導線（８）はボンディング用線（６）を介して
ＩＣチップ（至）と連結されて、該ＩＣチップ（至）と
リードピン（５）とを連結している。Further, the conductive wire (8) is connected to the IC chip (to) via the bonding wire (6), thereby connecting the IC chip (to) and the lead pin (5).

該ボンディング用線（ロ）は高純度鋼を線引加工と中間
熱処理をくシ返して直経（至）μのＣｕ線に仕上げ九芯
材（１２ａ）を半田メッキ（３）で被覆して形成したも
のであシ、導線（８）のボンディングリード（８＆）と
ＩＣチップへｑの半田パップ（９）とにわたって熱圧着
法或いは超音波ボンディング法等によシ接着される。The bonding wire (b) is made of high-purity steel that has undergone wire drawing and intermediate heat treatment to become a Cu wire with a straight warp (to) μ.Nine-core material (12a) is coated with solder plating (3). This is then bonded to the bonding lead (8&) of the conductive wire (8) and the solder pad (9) of q to the IC chip by thermocompression bonding, ultrasonic bonding, or the like.

以上の様に導線（８）及びボンディング用線ｃＬ１カ半
田メブキ（３）で被覆され、かつＩＣチフプα１側にも
半田バンプ（９）カ形成されるので、ボンディング用線
（６）の接着強度がより一層強められる０As described above, the conductive wire (8) and the bonding wire cL1 are covered with the solder paste (3), and the solder bumps (9) are also formed on the IC chip α1 side, so that the adhesive strength of the bonding wire (6) is increased. is further strengthened0

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の回路基板の縦断面図、第２図は第１図
の部分拡大断面図である。 尚、図中 （Ａ）二手導体装置　　　（３）：半田メッキ（８）：
導線　　　　　　（９）二半田バンプ（ト）：工Ｃチッ
プ　　　　（６）：ボンディング用線（ｉ２ａ）　：芯
材 を夫々示す。FIG. 1 is a longitudinal sectional view of a circuit board of the present invention, and FIG. 2 is a partially enlarged sectional view of FIG. 1. In addition, in the figure (A) two-handed conductor device (3): solder plating (8):
Conductive wire (9) Second solder bump (g): C chip (6): Bonding wire (i2a): Indicates the core material.

Claims (1)

【特許請求の範囲】[Claims] ＩＣチップと導線のボンディングリードとをボンディン
グ用線を介して連結した半導体装置において、前記ＩＣ
チップに半田バンプを形成すると共に、導線を半田メッ
キで被覆し、これらＩＣチップの半田バンプと導線とを
高純度鋼の芯材に半田メッキを被覆して形成したボンデ
ィング用線を介して連結した半導体装置。In a semiconductor device in which an IC chip and a bonding lead of a conductor are connected via a bonding wire, the IC
Solder bumps were formed on the chip, and conductive wires were coated with solder plating, and the solder bumps of the IC chip and the conductive wires were connected via bonding wires formed by coating a high-purity steel core material with solder plating. Semiconductor equipment.
JP60299425A 1985-12-28 1985-12-28 Semiconductor device Pending JPS62158338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60299425A JPS62158338A (en) 1985-12-28 1985-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60299425A JPS62158338A (en) 1985-12-28 1985-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62158338A true JPS62158338A (en) 1987-07-14

Family

ID=17872399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60299425A Pending JPS62158338A (en) 1985-12-28 1985-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62158338A (en)

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