JPS62154891A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To remove flickers by simultaneously selecting three vertical photoelectric transducers or more. CONSTITUTION:A two-line simultaneous reading mode for selecting a photodiode by a selecting pulse phi' in a field to read out signal charge, selecting the same photodiode by a selecting pulse phi'' and also selecting another photodiode by the selecting pulse phi'' coincides with a two-line simultaneously reading mode for selecting a photodiode by the selecting pulse phi' in the succeeding field. For instance, photodiodes PDm-PDm+1 are simultaneously selected by the selecting pulses phi'm, phi'm+1 in a field A, but the succeeding field B, the timing of the photodiodes PDm, PDm+1 selected by the selecting pulse phi'm, phi'm+1 selected by the selecting pulses phi''m, phi''m+1 are selected with the shift of 1H in the field A, but they are simultaneously selected in the field B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solid-state imaging device used in a video camera or the like, and particularly to a solid-state imaging device that can suitably suppress flicker.

[Background of the invention]

A solid-state image sensor used as a solid-state image sensor has a light 1 [
A two-dimensionally arranged photodiode group having functions for f conversion and charge accumulation, and a circuit having a scanning function for sequentially extracting signal charges accumulated in each photodiode corresponding to each pixel in a scheduled time series are integrated. It is a solid structure.

As is well known, solid-state image sensors have many advantages over image pickup tubes, but they also have their own problems. A prime example of this is a pseudo signal called a smear. Many measures have been proposed to suppress this smear. There are three types of typical measures:

(1) A method in which the smear S: is temporarily stored in a memory provided as an external circuit, and the smear is suppressed using that information.

(11) A method of suppressing smear using the mainly vertical structure of the solid-state image sensor.

(+ii) A method of suppressing smear by devising a signal readout method.

By the way, among the methods (1) to (ii+) for suppressing smear, the method (m) is usually considered desirable. Recently, among the (111) methods, Japanese Patent Application Laid-Open No. 59-144278 (1! lower) has been published.

The method described (hereinafter referred to as Conventional Example 1) is attracting attention as being particularly excellent in suppressing smear.

However, in the invention of Conventional Example 1, no consideration was given to flicker (hereinafter simply referred to as flicker) caused by the coupling capacitance between the vertical gate line and the photodiode constituting the pixel.

Regarding the causes of flicker, see Japanese Patent Application Laid-Open No. 57-46592.
Although it is described in detail in Publication No. C (hereinafter referred to as Conventional Example 2), it will be briefly explained below.

FIG. 2 shows a solid-state imaging device similar to that described in Conventional Example 1, with the vertical scanning circuit, horizontal scanning circuit, horizontal gate line, etc. omitted to make it easier to explain flicker. be.

In the figure, FD indicates a photodiode constituting a pixel, and subscripts m and n indicate the arrangement position of the photodiode, that is, the row and column. Therefore, for example, PDm,n is the photodiode in the m-th row and n-th column. Day indicates a horizontal traffic light, and the subscript m indicates the row of the horizontal traffic light. Also, each row has two horizontal traffic lights, so check them out! or as a subscript of 2. Therefore 1
For example, sm,i and 8m,2 are the two horizontal traffic lights in the m-th row.

In addition, 1 is a vertical switching MOS transistor (hereinafter referred to as a vertical MOS switch), 2 is a vertical gate line,
3.4 is a row selection switch, 5 to 8 are signal output terminals, 9
represents the coupling capacitance between the vertical gate line and the photodiode (the one that causes flicker among the two types of coupling capacitance described in Conventional Example 21). φ is a selection pulse for selecting a photodiode, and the subscript m indicates the row of the selection pulse. Therefore, for example, φm is a selection pulse that selects the photodiode in the m-th row.

The operation shown in FIG. 2 is the same as that described in detail in Conventional Example 1, and will therefore be omitted here.

Now, the occurrence of flicker will be explained with reference to FIGS. 3 and 4, taking as an example the reading of signals in the m+1 and m+2 rows.

In a certain field (called A field), the mth row and the mth row
Suppose that +1 row is selected at the same time.

In the next field (referred to as B field), interlaced scanning is performed in such a state that the mth row is selected simultaneously with the m-1th row, and the m+1th row is selected simultaneously with the m+2th row.

Therefore, the selection pulses .phi., .phi.+1.degree. .phi.m+2 for performing such interlaced scanning have waveforms as shown in FIG. Therefore.

Charges are exchanged as shown at times t1 to t4 in FIG. 3 via the coupling capacitor t9.

First, focusing on the photodiode PDm+1 in the (m+1)th row, as is clear from FIG. 3, at time t1, the accumulated charge increases by Δ (denoted as +Δ) due to the rise of the selection pulse φm. This +Δ is read out from the output terminals 7 and 8 through the two horizontal traffic lights Sm+1 during the period T1. Along with this, the accumulated charge of photodiode PDm+1 is reset (denoted as O).

At the next time t, on the contrary, the accumulated 11C load of the photodiode PDm+1 decreases by Δ (denoted as -Δ) due to the fall of the selection pulse φm. During the 0 period T4 in which this -Δ is held until immediately before the bladder release period T4 (time ts) of the photodiode PDm+1 in the B field, the charge of -Δ accumulated in the photodiode PDm+1 is transferred to the output terminal 7. Output from 8. Along with this, the photodiode PDm+1
The accumulated charge of is reset. Note that since the above-mentioned interlaced scanning is performed, the photodiode PDm+1 receives the selection pulse φ in the %B field. In the next A field, as mentioned above, +
The accumulated charge of Δ is read out. In this way, +Δ for each field from photodiode PDm+1.

-Δ accumulated charges are read out alternately.

Next, let's focus on the photodiode PDm+2.

As is clear from FIG. 3, due to the influence of the rise and fall of the selection pulse φ+1 in the B field, in the %A field, contrary to the photodiode PDm+1, -
It can be seen that +Δ accumulated charges are read out in the Δ and B fields.

Therefore, as shown in FIG.
y), and a solid-state image sensor with green (e) as an example.
Readout signal W+' corresponding to each color filter
! f3 + (!7 + g has a waveform as shown in Fig. 4 (assuming that there is no incident light). Note that ΔW, Δae, ΔCa, and Δ6 in Fig. 4 are each color filter W,
Y6, C! y and G represent the above-mentioned one load fluctuation of each photodiode arranged. here,
The read signal "r70+07*g" can be expressed as follows.

(i) A field (if) B field Note that w' and ye in equations (1) and (2)
', ay'.

g' is the read signal "+70+Qy+g"
represents the normal signal charge of

+11, from equation (2), luminance signal Y, color signal red (R)
, blue (B) is as follows.

(1) A field Ym a, w+a, ye+a, cy+a, g# a, w
'+a, ye'+ascy'+a4g'-(a, Δv,
-a, Δy@-a3Δ6y+a4Δg)-Y'-δI ...... (3) Rw 'b, w+b, ye-b, ay-'b, g# b
, tv'+ b, ye'-'b3cy'-b, g'-
(b, Δ, -b, Δ, fist ten bsΔay -b, Δg)
-R/-δR ・・・・・・(4) Bwc, w-c, ye+c, ay-c, g'm c, w
'-c2ye'+ c! cy'-c, g'-(C1Δ
y+c, Δys-03Δ6y-Q4Δf1)y B/
-δB ・・・・・・(5) (II) B field Y-Y'+δY ・・・・・・(6) R-
R'+δR...(7) B-B'+δB...(
8) However, y/ in equations (3) to 8),
R/, B/ and δY, δR9δB are (9)
As shown in equations and α1 equations, Y', R', and B' represent the normal signal charges of the luminance signal Y11 signals R and B, respectively, a, ~a, , b.

~b4. c, ~C4 represent matrix coefficients.

As is clear from the above description, the luminance signal Y11 signals R and B obtained from the solid-state image sensor shown in FIG. 2 exhibit so-called flicker, in which the signal levels change by δY and δR9δB from field to field, respectively. As a result, the image quality will be significantly degraded.

However, as shown in FIG. 2, in a solid-state image sensor, photodiodes and vertical gate lines are arranged regularly, so ΔW - Δye - Δ. It can be regarded as Δ8. Therefore, the matrix coefficient is
If it is a formula or a betting formula, it becomes δX−δR−δB−o,
No flicker will occur.

aI～&,=a3薯a4 ・・・・・・
συ1) I-1) t-1) s-b<
...' -Q2Q, W Q-Q, # Q,
・・・・・・03 However, under the conditions of the α9 type, Shiga et al. ``Study of moiré in high-resolution MO8 type single-panel color camera J'' Proceedings of the 1984 National Conference of Television Television Society 4
-9I This will deviate from the minimum moiré condition described here@Also. Under the conditions of a'b and equation (13), proper color reproduction is usually not possible. Therefore, the resultant f
This has the disadvantage that it is difficult to satisfy the conditions of formula 1I to formula α9, and therefore flicker cannot be avoided.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a solid-state imaging device that can suitably eliminate flicker.

[Summary of the invention]

In order to achieve the above object, the present invention takes into account that there is a degree of freedom in the selection of photodiodes constituting each pixel, as is well known, and the present invention eliminates the cause of flicker by selecting more photodiodes than in the past. The present invention is characterized in that the charge variation of Δ is substantially not read out to the signal output terminal. [Embodiments of the Invention] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a solid-state imaging element according to an embodiment of the present invention. However, in FIG. 1, components not directly related to the present invention, such as photodiodes constituting pixels in the column direction, horizontal gate lines, vertical scanning circuits, and horizontal scanning circuits, are omitted.

In FIG. 1, FD indicates a photodiode constituting a pixel, and the suffix d indicates the row in which the photodiode is located. Therefore, for example, the FD is the photodiode in the m-th row. S indicates a horizontal traffic light, and the subscript 1
0 indicates the row of the horizontal traffic light. Therefore, 1, for example, Sm is the horizontal traffic light in the m-th row.

10 is a vertical MOS switch, 11 is a vertical gate line, 12
is the coupling capacitance between the vertical gate line and the photodiode, 13 is the row selection switch, 14 is the reset switch, 15 is the OR circuit, 16°17 is the signal output terminal, 18 is the reset terminal, 30 is the vertical signal line, 32 is a reset line.

Further, φ, φ' and φ" are selection pulses for selecting photodiodes, and the subscripts are each selection pulse φ, φ',
FIG. 5 is a waveform diagram (timing chart) of these selection pulses. In FIG. 5, the selection pulse φ' indicated by a solid line is the conventional example (FIG. 3).
This pulse has the same timing as the selection pulse φ, and the selection pulse φ" shown by a broken line is a selection pulse newly added in this embodiment. Also, as is clear from FIG. 1, the selection pulse φ' and φ By passing " through the OR circuit 15, a selection pulse φ is obtained. Also in this selection pulse φ, the timing portion corresponding to φ' is shown by a solid line.

The timing portion corresponding to φ" is indicated by a broken line.

As can be understood from FIG. 5, the features of this embodiment are (1
) A sickle in which a photodiode is selected with a selection pulse φ' and the signal charge is read out in a certain field, and the same photodiode is further selected with a selection pulse φ'', and (I
I) The two-row simultaneous readout mode in which photodiodes are selected by the selection pulse φ'' is the same as the two-row simultaneous readout mode in which the photodiodes are selected by the selection pulse φ' in the next field.

The feature of (11) will be explained in more detail. For example, in the A field, the selection pulse φ is applied.

Photodiodes FD, n, PD and 1 are simultaneously selected by φ-ya□, but in the primary B field.

The timing of the photodiodes PD1PD, , l+1 selected by the selection pulses φ-, φ-+1 is IH (H
is the horizontal scanning period). On the other hand, looking at the photodiode PD and PD +1 selected by the selection pulse φt, 4+□, in the A field, I
Although the selections are shifted by H, they are selected at the same time in the B field. This is the content of the feature [11] described above.

Now, in this embodiment having the above-mentioned characteristics, since the charge fluctuations that cause flicker shown in the conventional example are not read out as a signal output, the m+1. This will be explained by taking the photodiode PD□1°PDm+2 in the m+2 row as an example.

FIG. 6 shows the selection pulse force, φo+1. 2 is a diagram showing a timing chart of φ, +2 and the states of the photodiode PD +11"111+2 and the horizontal traffic signal Sm+0.Srn+2 at each time (however, when unmanned light is emitted).

First, the m+1th selected by the selection pulse φm+1
The photodiodes PDm+ in the row are layered.

(+) period T, + photodiode FD, a+1
is selected and the accumulated charge is reset (denoted as 0).

(11) At time t, the selection pulse falls, and as a result, the accumulated charge of the photodiode PD decreases by Δ (denoted as -Δ).

(*+*) In period T2, the selection pulse φ rises;
However, since the photodiodes FD, , 1 are not selected, the charge of PD, , 1+□ remains at 1Δ at time ts.

(1■) Photodiode PDffi+ in period T3
1 is selected and the accumulated charge of -Δ is horizontal signal Syi
＋□.

Reset switch 14. It is read out to the reset terminal 18 via reset +1132. Along with this, the photodiode PD1. The accumulated charge of l+1 is reset. Note that the signal read to the reset terminal 18 is not used as an image signal. (V) The selection pulse rises during period T4.

However, since photodiode PD,11+1 is not selected, photodiode PD1. The accumulated charge of l+1 remains 0 at time t.

(■1) During period T, photodiode FD, +,
is selected, and the charge of 0 is read out to the signal output terminal 17 via the horizontal signal Sm+11 row selection switch 13 and the vertical signal line 30 (7), and PD+1 is reset.

(Vil) At time t, the selection pulse φ1 rises,
Photodiode D! In l+1, the accumulated charge increases by Δ (denoted as +Δ) 0 (vn+) in period T6, photodiode PT3! ,
l+1 is selected, and the accumulated charge of +Δ is horizontal signal 5I1.
1+1, reset switch 14% O is read out to the reset terminal 1B via the reset line 32. Along with this, the accumulated charges in the photodiodes F D and +t are reset.

(1x) At time t, the selection pulse φ falls, and as a result, the accumulated charge of the photodiode PDII1+1 decreases by Δ.

(X) This -Δ is held until time t, and is canceled out by the charge increase of +Δ due to the rising edge ζ of the selection pulse φ at time t. As a result, the period T.

The charge read out to the signal output terminal 17 from the photodiode PD□1 selected at , via the horizontal signal B□1, etc. becomes 0.

(xl) Repeat the above operations @ Next, m+th selected by selection pulse φ, a+2
Focusing on the photodiode PDm+2 in the second row, the charge fluctuation of ±Δ and the charge read out to the horizontal signal I3+11+2 are similar to the photodiode PDm+1 in the sixth row.
As shown in the figure. Therefore, it can be seen that there is no charge variation in the signal read out to the signal output terminal 16 from the photodiode F D , +2 in the m+2 row, and the charge variation is read out to the reset terminal 1B.

As is clear from the above explanation, in this example,
Whereas the charge fluctuation amount of ±Δ is read out to the reset terminal 18 by the selection pulse φ".

The normal signal charge without charge fluctuation is read out to the signal output terminals 16 and 17 by the selection pulse φ'.As a result,
A flicker-free video signal can be obtained.

Here, generation of the selection pulse φ in this embodiment (first embodiment) will be explained. As mentioned above, the selection pulse φ is obtained by passing the selection pulses φ' and φ'' through the well-known OR circuit 15, and the one selection pulse φ' is the same as the conventional selection pulse (FIG. 3). In other words, it is the same as the output pulse of a conventional vertical scanning circuit. Therefore, in this embodiment, the key point is how to generate the selection pulse φ.
A vertical shift register similar to the vertical shift register for generating ``1'' is provided separately for generating 1 selection pulse φ''.

This can be obtained by performing the following actions. That is,
Assuming that the selection pulse is a mode 1 pulse in the A field and a mode 2 pulse in the B field, as is clear from Fig. 5, the 5 selection pulse φ'' is, conversely, a mode 2% in the A field and a mode 2 in the B field. It has a mode 1 pulse pattern.

Therefore, the operation of the vertical shift register for generating the selection pulse φ' in the A field is performed by the vertical shift register for generating the selection pulse φ' in the B field,
Also, the operation of the vertical shift register for generating the selection pulse φ' in the B field may be performed by the vertical shift register for generating the selection pulse φ' in the A field. An example will be explained using FIG. 7.

As is clear from FIG. 5, the selection pulse φ″1(1-1
, 2, 3...) are the selection pulses φ' and 1+
3 Same timing waveform. Therefore, it is clear that even with only five selection pulses φ', the input selection pulses φ' and φ'' of each OR circuit 15 in FIG. 1 can be obtained by configuring the circuit as shown in FIG.

FIG. 3 is a circuit diagram of a solid-state imaging device according to another embodiment of the present invention. However, in FIG. 8, as in FIG. 1, components not directly related to the present invention, such as photodiodes constituting pixels in the column direction, horizontal gate lines, vertical scanning circuits, and horizontal scanning circuits, are omitted. It is.

In FIG. 8, %FD indicates a photodiode constituting a pixel, and the subscript 1 indicates the row in which the photodiode is located. S indicates a horizontal traffic light, and the subscript 〇 indicates the row of the horizontal traffic light. 19 is a vertical gate line, 20 is a vertical MOS switch, 21
22 is the coupling capacitance between the vertical gate line and the photodiode, 23.24 is the signal output terminal, and 31 is the vertical signal line. φ is a selection pulse for selecting a photodiode, and the subscript indicates its row. Note that this selection pulse φ consists of a pulse having the same timing as the selection pulse φ of the conventional example (FIG. 3) and a selection pulse newly added in this embodiment. FIG. 9 is a waveform diagram (timing chart) of these selection pulses. The selection pulse φ of the conventional example is shown as φ' by a solid line, and the selection pulse newly added in this embodiment is shown as φ". Also, regarding the selection pulse φ of the real 1tllJ, the timing portion corresponding to V is shown by a solid line, and the timing portion corresponding to φ'' is shown by a broken line.

The key point of this embodiment is that when normal signal charges are read out using the selection pulse φ', charge fluctuations of ±Δ, which are simultaneously read out, are simultaneously read out using the selection pulse φ', while charge fluctuations with the opposite polarity are simultaneously read out. The point is that by putting out the two, you can add them together and cancel them out. This will be explained using FIG. 10.

FIG. 10 shows the charge fluctuation using the same method as in FIG. 6 for explaining the first embodiment described above, and shows the photodiode PD! at each time. Il′″”!
l+4% and horizontal signal +1115m~5I11+4
It is clear that the charge fluctuation state is as shown in the figure.

For example, looking at period T2, in this period the selection pulses φm+2. The photodiode PDffi+2. PD Yo+
3 normal signal charge to the horizontal signal S1. l+2. S...
I am trying to read out data to the signal output terminal 23.24 via the l+3% row selection switch 21 and the vertical signal line 31, but at the same time, +2 is being read from the photodiode PD +2.
The charge variation amount of Δ is also read out. Therefore, in this embodiment, 1
During the period T2, the photodiode FDrn is simultaneously selected by a selection pulse φm (details φt).

-Δ charge fluctuation is determined by the horizontal polarization line Nikko 1 line selection switch 21. The signal is read out to the signal output terminal 23 via the vertical signal @31. As a result, the charge fluctuations are canceled out and disappear, and only normal signal charges are read out to the signal output terminals 23 and 24.

Also, regarding T6 for 1 hour, the photo+
11+4 Diode PD +31 I'm trying to read out the regular signal charge of PDm+4, but the photodiode PDI! l+
3, the charge fluctuation amount of +Δ is also read out. Therefore, in this embodiment, the selection pulse φm+1 (in detail, φ
The photodiode PD+1 is simultaneously selected at m+t), and the charge variation of -Δ is read out.

As a result, the load fluctuation component is canceled out and disappears, and only normal signal charges are read out to the signal output terminals 23 and 24.

Therefore, according to this embodiment, a flicker-free video signal can be obtained.

In addition, when the photodiode is selected with the selection pulse φ",
The light conversion signal of the photodiode is also read out at the same time and is added to the light 11L conversion signal (regular optical range conversion signal) of the photodiode selected by the selection pulse φ'. However, since the photodiode is selected by the selection pulse φ'' immediately after the same photodiode is selected by the selection pulse φ', the photoelectric conversion signal of the photodiode can be ignored, and therefore the normal photoelectric conversion There is almost no damage to the signal. Here, the generation of the selection pulse φ in this embodiment will be explained.

As is clear from FIG. 9, the I selection pulse φ1. □-1
, 2, 3-1-) can be obtained by the following equation.

φ1-φ1+φ'i+2 ×φ'1+3 ・・・
...(4) However, in this formula (141), + and × indicate a logical sum and a logical product, respectively.

Therefore, it is easy to understand that the selection pulse φ of this embodiment can be obtained from the circuit configuration I of FIG. 11 using only the selection pulse (FIG. 3) φ' of the conventional example.
In FIG. 11, 25 and 26 indicate a well-known OR circuit and an AND circuit.

〔Effect of the invention〕

As is clear from the above description, in the present invention, when reading a regular photoelectric conversion signal, the ±Δ charge fluctuations that are read out at the same time are read out to the reset terminal or canceled out. Since the signal disappears, it is not read out to the signal output terminal. As a result, according to the present invention, a flicker-free video signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a solid-state image sensor according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an example of a conventional solid-state image sensor, and FIGS. 3 and 4 are circuit diagrams of a conventional solid-state image sensor. 5 is a timing chart of each selection pulse in FIG. 1, and FIG. 6 is a diagram to explain that flicker does not occur in the embodiment shown in FIG. 1. 7 is a circuit configuration diagram for generating the selection pulses φ' and φ" in FIG. FIG. 8 is a timing chart of the selection pulse, FIG. 10 is a diagram for explaining that flicker does not occur in the embodiment of FIG. 8, and FIG. 11 is a circuit configuration diagram for generating the selection pulse φ of FIG. 8. FD...Photodiode, 8...Horizontal signal, φ. φ', φ"...Selection pulse, 10.20...Vertical M
OS switch, 11.19... Vertical gate line, 12゜22... Coupling capacitance, 13.21... Row selection switch % 14... Reset switch, 15゜25... OR circuit % 26...AND circuit, 30°31...Vertical signal line, 32...Reset line agent
Patent Attorney Michihito Hiraki Figure 1 Figure 3 Figure 4 → Time Figure 5 □ Time Figure 6 A Field - B Fee 2. t,・ψ,,]-go-huge--,"--one and-first
7 Figure φ'm-1φ・m-1 Figure 8 Figure 9 Figure A field B7 double knee - □ Time Figure 10

Claims (3)

[Claims] (1) It has a pixel array consisting of a photoelectric conversion element and a switch element, and horizontal and vertical scanning circuits that sequentially selectively scan the pixel array, and the photoelectric conversion element is connected to a horizontal signal line via the switch element. and the horizontal signal is connected to the vertical signal line via another switch element driven by the vertical scanning circuit, in which three or more vertical photoelectric conversion elements are simultaneously selected. A solid-state imaging device featuring: (2) The same photoelectric conversion element is selected twice within the same field, and the accumulated charge obtained by the second selection is read out to a reset line provided separately from the vertical signal line. A solid-state imaging device according to claim 1. (3) Three vertical photoelectric conversion elements are selected at the same time,
2. The solid-state imaging device according to claim 1, wherein the accumulated charges of these three photoelectric conversion elements are read out to the vertical signal line.