JPS62122466A - Method and apparatus for compensating defects in selected ccd - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to CCD imaging cameras, and more specifically to CCD imaging cameras.
The present invention relates to a device for compensating for defects in D.

PRIOR ART AND PROBLEMS In the past, solid state imaging devices such as CCDs have been found to have a number of defects that manifest as black and/or white dots or lines on television monitors.

These defects are undesirable and can be removed from the television monitor by eliminating the signal coming out of the CCD that represents this defect before the signal reaches the television monitor circuitry and is displayed. It is highly desirable. This has been extremely difficult since a large number of such defects have been found in almost every CCD sampled in the past. As far as aesthetics are concerned, if such defects could be removed electronically, CC
It is clear that the yield of D can be significantly increased. Previous attempts to improve this aesthetic appearance have included 19
As described in U.S. Patent Application Serial No. 677.320 filed on December 3, 1984, these deficiencies were automatically corrected. However, these methods affected even clean data for spatial frequencies close to the Nyquist frequency limit, which is the υ limit.

Therefore, methods for minimizing or correcting such defects have not been well accepted in the past. However, with improvements in processing technology, CCDs are now available in which a significant percentage of those produced have only a few defects. Therefore, it has now become possible to provide a CCD using a programmable method in which defects can be easily identified and compensated for.

Measures and Actions to Solve the Problem The dark current pattern of a CCD camera such as TlC9Δ and TlC9L represents a defect in the imaging device as a saturated white image ranging from a point to aY of a linear defect. . The defect compensation system to be described sequentially disables sample and hold pulses for the intended defective pixel or group of pixels for each horizontal scan line of video.

Due to the constraints of Section 51, correction of possible defects is limited to the following:

1) One vertical line from top to bottom or one from top to bottom
Successive lines of groups.

2) 1 point defect per horizontal scan line or 1 per scan line
horizontal "streams" of pieces.

3) Double point correction if the pixels are separated by 254 pixels per scan line.

4) Double vertical lines in each horizontal scan line if the defects are 254 pixels apart.

Briefly, the present invention provides a circuit for pinpointing defects in a particular CCD and storing the address(es) in a storage device, such as a programmable memory (PROM). I will provide a. In the case of FROM, this PROM can be used as part of the CCD circuit by burning the address of the defective pixel, and it can be used as a part of the CCD circuit.
Preferably, it is unique to the CD and stores the address of the defective pixel. Since nearly all CCDs have a pixel address counter as part of their circuitry, this pixel address counter always has the address of the particular pixel in the CCD that is being scanned at any given time. This address in the pixel address counter is used by a comparator to identify the defective pixel in the CCD.
Compare with the stored address in PROM.

When the comparator makes a positive comparison, it interprets the positive comparison as scanning the defective pixel and the comparator generates an output to the inhibit circuit, which is described in pending U.S. Patent Application No. 768.077.
The TTL 5-H (sample-and-hold) trigger signal is prohibited from being applied to the sample-and-hold circuit through the sample-and-hold driver described in No. 2 (Applicant's copy number Tl-852). TTL sample hold
Since the trigger signal is inhibited, the contents of the sample and hold circuit of this US patent application are not forwarded, thereby preventing signals from defective pixels from being input to the sample and hold circuit. Therefore, the signal from the defective pixel is lost, and as a result, a non-defective pixel scanned before the defective pixel is displayed at the location of the defective pixel. Therefore, either black or white dots will not appear at the location of a defective pixel.

In FIG. 1, plane 1 of the CCD is shown diagrammatically, indicating the location of the defective pixels. Three such defects 3
．． 5.7 is shown. The defective pixel is located at address location (x), (y,).

It can be seen that it has (xb), (y,) and (xC), (y,). The exact location of the pixel with this defect is
As determined by the calibration scan, the current value of the pixel address counter at the time the defective pixel is being scanned is PRO
It is stored in the array to be used to skip M. In a typical apparatus for programming the location of defective pixels, the CCD camera with the CCD being tested is illuminated with a uniform light source at a level of 50% of all wells. A camera then scans the CCD field, and a microprocessor-controlled defect mapping device detects a nominal 1/2 well signal during the scan.
detects the location of the pixel where the signal differs by a programmable amount) and stores the address in temporary random access memory (RAM).

Do this for all defects, and then place these defects in a programmable ROM (PRO).
M> and burned into it so that it does not indicate the location of the defective pixel and the data is permanently stored. This FROM is unique to the CCD with which it is programmed.

In the actual circuit shown in FIG. 2, PROM11 is connected to comparator 1.
Connected to 3. Pixel address counter 15 is also coupled to the same comparison PJ13. The input 17 of the pixel address counter is set each time the CCD scans to a new address.
This counter is incremented so that the actual address of the pixel being scanned is in the pixel address counter 15. The address in pixel address counter 15 is FRO
When it is the same as one address in Mll, comparator 1
3 indicates that the comparison is valid, which sends a signal to the prohibition circuit 19. The prohibition circuit is of a well-known type and compares i'! t
The signal from the TTL sample and hold trigger 2) is always allowed to pass through it, except when an inhibit pulse is received on line 23 from 13. When this inhibit pulse is received, there is no signal at the output 25 of the inhibit circuit 19.

Since the signal on line 25 is sent to a sample-and-hold circuit of the type described in the previously cited pending U.S. patent application (Assignee Receipt No. Tl-852), there is no pulse on line 25. , prohibits data transfer from this sample and hold circuit. Therefore, at this time, the data in the sample-and-hold circuit of the previously cited U.S. patent application is stored until the pixel address counter records a new address.
held within it. The net result of this is that the signal present in the sample and hold circuit is utilized for the address position of the defective pixel as well as the original address position, and the signal coming from the defective pixel is stored in the sample and hold circuit. It is lost because it cannot be done. This procedure provides an aesthetically improved display free of undesirable black and/or white dots and/or lines.

FIG. 3 shows a circuit diagram of a programmable defect compensation system according to a preferred embodiment of the present invention.

The timing signals used in this step are shown in the time diagram of FIG. The video has 242 active lines. Therefore, an 8-bit counter 31 is used as a line pointer to provide an address for a programmable fixed memory (PROM>33).

328fillJ l1Ij per video horizontal scan line
There is an element.

Although 9 bit words are required to count each pixel, 29-328=184 counts or 36% are not used. An 8-bit FROM 33 is chosen to minimize the number of chips. As a result, 3281 [!
148 of the pixels of J are double corrected.

The pixel count of 255 io or FF16 is a missing value and this is programmed into the PROM 33 for lines for which correction is not desired. , FF16 was chosen as the missing value, assuming that there is a horizontal scan line without defects, r'
This is to reduce the power consumption of the ROM 33 and wrap 35.

The PROM 33 is programmed only during the 10.5 microsecond horizontal blanking time at the end of each television horizontal scan line (once every 63.5 microseconds) and during the monitor blanking time.
At this time, the latch 35 is loaded with 8-bit data from the PROM. This represents the defective pixel count on the next valid horizontal scan line. The flip-flop latch 35 performs an O-lock operation using the horizontal drive pulse HD shown in FIG.

While scanning a valid horizontal scan line, the address of the defective pixel, or run 1~, is compared in comparator 39 with the output of 8-bit pixel counter 37. This counter is clocked by the CCD camera serial clock signal (φ,) shown in FIG. If the comparison is made in the comparator 39 (if the address of the defective pixel is the same as the count in the pixel counter 37), an inhibit pulse is generated by the comparator via the one-shot 41 to detect this defect. 11. Prevents sampling of pixels that have

The pixel counter 37 is reset to O during horizontal blanking or compound blanking (CB in Figure 4), and the value of FF16 is decoded by the decoder 43 on the output side of the pixel counter and becomes the missing value of FF16. When the comparison is made, no inhibit pulse is generated. Originally, the value of FF16 is decoded, but due to the propagation delay of the circuit, a pulse is generated when there is a missing one. This is the result with one extra inverter and two non-pixel counts.

A one shot 45 is added to the serial clock, which drives the pixel counter 37 to phase shift the output inhibit pulse relative to the serial clock (φ,).

In the actual circuit configuration, the comparison for the currently scanned pixel is made during the previous pixel count, so that the inhibit pulse can be generated at the same time as the actual sample and hold pulse is generated.

One shot 41 is provided to control the pulse width of the inhibit pulse. If two pixels must be removed in succession, the pulse can be extended from 80 nanoseconds for one pixel to 240 seconds for two pixels by adjusting variable resistor 47. This value can be set to any number of pixels, but each inhibit pulse corrects the same number of successive pixels.

As can be seen from the above description, it is possible to improve the aesthetic appearance of the CCD when read out, to make it possible to utilize CCD devices with less serious defects, and thus to increase the yield rate. It provided a simple circuit.

Although the invention has been described with respect to certain preferred embodiments,
Many modifications will occur to those skilled in the art. Therefore,
The claims are to be construed as broadly as possible in light of the prior art to encompass all such modifications.

In connection with the above description, the following sections are further disclosed.

(1) An apparatus for compensating for defects in a selected CCD, comprising sample and hold storage means and driving means for driving the storage means, the driving means representing the location of the defect in the CCD. Apparatus comprising defect indicator means, scan position means representative of the location of scanning of said CCD, and comparator means for inhibiting said drive means in response to a predetermined relationship between said defect indicator means and said scan position means. .

(2) In the device described in item (1), the defect display means is a FROM.

(3) The apparatus according to item (1), wherein the scanning position means is a pixel counter.

(4) The apparatus according to item (2), wherein the scanning position means is a pixel counter.

(5) The device according to item (1), wherein the driving means also includes inhibiting means for inhibiting driving of the storage means in response to the comparator means.

(6) The device according to item (2), wherein the driving means also includes inhibiting means for inhibiting driving of the storage means in response to the comparator means.

(7) In the apparatus described in item (3), the driving means also includes inhibiting means for inhibiting driving of the storage means in response to the comparator means. Place.

(8) The device according to paragraph (4), wherein the driving means also includes inhibiting means for inhibiting the driving of the storage means in response to the comparator means.

(9) In the device described in item (1), the device includes means for controlling the operation cycle of the inhibiting means.

(10) The apparatus described in item (2), which includes means for controlling the operation cycle of the inhibiting means.

(11) The apparatus described in item (3), which includes means for controlling the operation cycle of the inhibiting means.

(12) In the apparatus described in item (4), the apparatus includes means for controlling the operation cycle of the inhibiting means.

(13) The apparatus described in item (5), which includes means for controlling the operation cycle of the inhibiting means.

(14) The apparatus according to item (6), including means for aNI talling the operating cycle of the inhibiting means.

(15) The apparatus described in item (7), including means for controlling the operation cycle of the inhibiting means by aNI.

(1G) In the device described in item (8), the device includes means for controlling the operation cycle of the inhibiting means a, 11.

(17) An apparatus for compensating for defects in a selected CCD, comprising a sample and hold storage means, a display means responsive to an output of the storage means, and a drive means for driving the storage means. Means includes: a defect indicator representing the location of a defect in said CCD; a scan position means representing a scan position of the CCD; A device containing means for inhibiting modification.

(18) The device according to item (17), including means for controlling the operation cycle of the prohibiting means.

(19) In a method of compensating for defects in a selected CCD,
determining the location of the defect in the selected CCD; scanning the selected CCD; determining the location of the scan; comparing the location of the scan with the location of the defect; generating an inhibit signal in response to a predetermined relationship between locations of the method.

(20) The method described in item (19), further comprising the step of providing a display device and inhibiting the change of the signal to the display device in response to the prohibition signal.

[Brief explanation of drawings]

Figure 1 shows C with a defective pixel at the entered address.
Figure 2 is a schematic diagram illustrating a CD; Figure 2 is a circuit diagram of a circuit that inhibits the display at a location corresponding to a defective pixel in the CCD;
4 is a circuit diagram of a programmable defect compensation system according to a preferred embodiment of the present invention, and FIG. 4 is a time diagram showing timing signals used in the circuit of FIG. Explanation of main symbols 11: PROM 13: Comparator 15: Pixel address counter 19: Prohibited circuit allowance Hiroshi Asamura

Claims (2)

[Claims] (1) An apparatus for compensating for defects in a selected CCD, comprising a sample and hold storage means and a drive means for driving the storage means, the drive means representing the location of the defect in the CCD. Apparatus comprising defect indicator means, scan position means representative of the location of scanning of said CCD, and comparator means for inhibiting said drive means in response to a predetermined relationship between said defect indicator means and said scan position means. . (2) In a method of compensating for a defect in a selected CCD, the location of the defect in the selected CCD is determined and the selected CCD is
scanning a CD, determining the scan location, comparing the scan location to the defect location, and generating an inhibit signal in response to a predetermined relationship between the defect location and the scan location; method including.