JPS62126664A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To protect a high level potential accumulated in a capacitor constituting a memory cell from free electrons, by forming the capacitor between a region, wherein an arranged body of memory cells is formed, and a region, wherein peripheral circuits are formed, connecting one electrode of the capacitor to the ground potential, thereby capturing the free electrons in a semiconductor substrate by the capacitor. CONSTITUTION:A memory cell is constituted by an access transistor and an MIS capacitor. The arranged body of the memory cell is formed in a region. A capacitor is formed between said region and a region, wherein peripheral circuits are formed. One electrode of the capacitor is connected to the ground potential. For example, the memory cells are formed in a region defined by an isolating insulating film 4'. The peripheral circuits are formed in a region defined by an isolating insulating film 4''. An impurity region 3' is formed in a region between the films 4' and 4''. The impurity regions 3' is made to face an electrode 7' through a capacitor insulating film 10'. A capacitor is formed by the impurity regions 3', the capacitor insulating film 10' and the electrode 7'. Thus, electrons freed from the peripheral circuits into a substrate are absorbed into an inverted layer, which is generated in the substrate beneath the electrode 7' that is connected to the ground potential. The electrons do not reach the memory cells. Therefore, information stored in the memory cells are not erased by the free electrons.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device in which one electrode of a capacitor for information storage is connected to a power supply potential.

[Conventional technology]

FIG. 2 is a cross-sectional view showing a conventional example, in which an N-type impurity region 2.3 is formed in a P-type silicon substrate 1, and the impurity region 2 is used as a digital wire. The impurity regions 2 and 3 are surrounded by a thick field enhancement film 4, and the optical surface of the substrate 1 between them is covered with a thin silicon dioxide film 5. Silicon dioxide film 5 between impurity regions 2 and 3
A gate 6 of an access transistor is formed thereon 9 , while an electrode 7 faces the impurity region 3 with a silicon dioxide group 5 interposed therebetween. The gate 6 and the electrode 7 are connected to a power wiring &9 and a ground wiring 10, respectively, through contact holes formed in a thick plated film covering them.

In order to store a high level potential corresponding to a logic 1 in a memory cell having such a configuration, a high level signal is applied to the word line,
A channel is formed on the surface of the substrate 10 between impurity regions 2 and 3, and a high-level potential is sent from the digit line, that is, the impurity region 2, through the channel. therefore,
The high-level potential is accumulated in the inversion layer formed on the substrate side based on the power supply potential applied to the electrode 7 via the power supply wiring 9, and information corresponding to the high-level potential is stored. .

[Problem to be solved by the invention]

In addition to the array of memory cells, the above-mentioned memory device has various circuits integrated therein, and electrons are dissociated from the elements constituting these peripheral circuits onto the substrate 1, and move through the substrate 1 to form the memory cells. When approaching the array, mosquitoes are attracted to memory cells that store high-level potentials, causing the tube-level potential to disappear.

[Failure to solve the problem]

The present invention provides an access transistor and an MI connected to the access transistor and having one electrode supplied with a power supply potential.
In a semiconductor memory device in which a memory cell array composed of 8 capacitors and a peripheral circuit of the memory cell array are integrated on a single semiconductor substrate, an area where the memory cell array is formed. A capacitor is formed between the area where the peripheral circuit is formed, and one electrode of the capacitor is connected to a ground potential, thereby transferring free electrons in the semiconductor substrate to the capacitor connected to the ground potential. This is intended to protect the high-level potential that is captured by the body and accumulated in the cap body constituting the memory cell from the liberated electrons.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of the present invention, and in the figure,
Components that are the same as those of the conventional example are given the same reference numerals, and explanations thereof will be omitted. The above-mentioned isolation insulating film 4' and isolation insulating film 4'' are provided between the isolation insulating film 4' that defines the area where the memory cell is formed and the area where the peripheral circuit (not shown) is formed. An impurity region 3' is formed in the region defined by 9.
, the impurity region 3' is connected to the electrode 7 via the capacitive insulation lA10.
′ is opposite.

The impurity region 3', the capacitor insulating film 10', the electrode 7' and t
As a whole, it constitutes a capacitor that captures liberated electrons.

In a memory device having such a configuration, although electrons released into the semiconductor substrate 1 from the elements constituting the peripheral circuit reach the vicinity of the area where the memory cells are formed, they do not reach the area immediately below the electrode 7' connected to the ground potential. Since the free electrons are absorbed by the inversion layer formed on the surface of the substrate 1, the information stored in the memory cell as a high level potential will not be erased by the released electrons.

〔effect〕

As described above, according to the present invention, a capacitor having one electrode connected to the ground potential is formed between a region where an array of memory cells is formed and a region where a peripheral circuit is formed. Therefore, the fc electrons released from the peripheral circuit to the substrate are absorbed by the inversion layer generated in the substrate under the electrode connected to the ground potential and do not reach the memory cell. Therefore, it is possible to obtain the effect that the information stored in the memory cell is not destroyed by the liberated electrons.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 7...One electrode of a capacitor constituting a memory cell, 7'...One IT& connected to ground potential.ゝ(゛

Claims (1)

[Claims] A memory cell array including an access transistor and an MIS capacitor connected to the access transistor and having a power supply potential supplied to one electrode, and a peripheral circuit of the memory cell array are mounted on a single semiconductor substrate. In a semiconductor memory device integrated in a semiconductor memory device, a capacitor is formed between a region where the memory cell array is formed and a region where the peripheral circuit is formed, and one electrode of the capacitor is connected to a ground potential. A semiconductor memory device characterized by: