JPS62125629A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To microminiaturize an element separating zone by partly etching in depth with an etchant having selectivity in a crystal direction at groove forming time to form an oblique portion on the periphery of a bottom of the groove. CONSTITUTION:A groove of predetermined depth is selectively formed on a semiconductor substrate, a mask 22 is removed when a groove for forming an element separating zone formed by burying an insulator in the groove is formed, it is then heat treated to form an SiO2 film 27 in and on the groove 25, the surface including the groove is covered with a thick polycrystalline silicon film 28 by a CVD method to bury the groove 15, and the polycrystalline silicon film 28 is laminated thereon. Then, the film 28 on the surface is removed by etching or polishing, and the silicon film on the surface of the groove is oxidized to generate an SiO2 film 29, thereby completing an element separation zone of separating the groove. Thus, a discontinuous line of the buried insulator is eliminated to obviate a low density portion, thereby obtaining an element separating zone to be readily microminiaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] When forming an element isolation zone by trench isolation, etching is performed using an etching agent that is selective to the crystal direction to form a sloped portion around the bottom of the trench. In this way, discontinuous lines of the buried insulator will not be formed, and the element isolation bands can be miniaturized.

[Industrial Field of Application] The present invention relates to a method for manufacturing semiconductor devices such as ICs, and more particularly to a trench isolation method for isolating semiconductor elements.

In an IC, a large number of semiconductor elements are provided on a semiconductor substrate, and element isolation bands are formed to electrically isolate these semiconductor elements.

Various methods are known for forming such device isolation bands, and one of the currently widely used methods is the trench isolation method.

However, it is desirable that the element isolation band formed by this trench isolation method be given sufficient consideration so that a high-density insulator is buried inside the groove, and that the element isolation band can be easily miniaturized.

[Problems to be solved by conventional techniques and inventions] Conventionally,
The trench isolation method (trench isolation method) is also known as I OP (I
Solation with Oxide and P
This is a method in which a polycrystalline semiconductor is buried in a trench via an oxide film, and an oxide film is formed on both sides of the trench. - A method of forming a so-called V-groove separation zone, in which a V-shaped groove is formed by etching, has been adopted.

However, in recent years, with the development of the dry etching method and the demand for higher integration, a method for forming a so-called U-groove separation zone, in which a U-shaped groove is formed by dry etching, has become widely used. This is because the U-shaped groove is more suitable for miniaturization than the ■ groove.

Moreover, instead of the above-mentioned IOP method, recently, an isolation method, also called the so-called oxide film trench isolation method, has been used in which the entire trench is buried with an oxide film (silicon dioxide film; 3i02 film). This is due to advances in the deposition of 5iCh films by chemical vapor deposition (CVD).

However, as the trench width becomes narrower as a result of higher integration, it becomes difficult to sufficiently bury the trench with the insulator, and gaps are likely to form inside the buried layer.

This will be explained using a specific example. FIG. 3 (a+ to (C+) are cross-sectional views in the order of steps of a method for forming a U-groove separation band by the conventional IOP method.

First, as shown in FIG. 3(a), a p-type silicon substrate 1
A mask 2 is formed on top, and grooves 3 with a depth of 3 to 4 μm and a width of about 1 μm are formed by dry etching using chlorine gas.
is formed, and further boron ions are implanted. By implanting this boron ion, a p' type channel/node layer 4 (see FIG. 3(b)) is formed in a heat treatment in a subsequent step. still,
Mask 2 is silicon nitride (Si3
N4) film is laminated, and the top is further covered with a phosphorous silicate glass (PSG) film or a resist film with a thickness of 1 μm.
It is a covering mask of about m.

Next, as shown in FIG. A thick polycrystalline silicon film 6 is deposited on the surface including the grooves 3 to bury the grooves 3.

Next, as shown in FIG. 3 (C1), the polycrystalline silicon film 6 on the surface is removed by etching or polishing, and the polycrystalline silicon film on the groove surface is further oxidized to form a 5t02 film 7. , complete the device isolation strip of groove isolation.

However, in this formation method, when depositing the polycrystalline silicon film 6, the polycrystalline silicon film is stacked on a flat surface, so a discontinuous line of stacking of the polycrystalline silicon film occurs from the corner of the bottom surface (third
In Figures fb), (shown in dotted lines in (C)), interstitial areas with low burial density are formed. In this case, the low-density portion of the discontinuous line becomes easily penetrated by the etching or polishing liquid during the etching or polishing process (see Figure 3 (C1)), and in extreme cases, the intruding liquid is heated in the next process. They may expand and break.Furthermore, even if they do not break, cracks often appear in the discontinuous line portions after heat treatment.These problems are extremely detrimental to the yield and quality of semiconductor devices.

Therefore, in order to eliminate this discontinuous line, other forming methods have been proposed, and FIGS. 4(a) to 4(Fdl) show cross-sectional views in the order of the forming steps.

First, as shown in FIG. 4(a), a p-type silicon substrate 1
After forming a 5i02 film 12 with a thickness of 1000 to 2000 on 1, and forming a mask 13 thereon, etching is performed using an isotropic etching agent, for example, a hydrofluoric acid solution, and while controlling the amount of etching, Excessive side etching as shown. In this etching, the width of the side etching is important.

Next, as shown in Figure 4tb), sulfur hexafluoride (SF
6) Etching is performed using gas to form a groove 14 having a depth of 3 to 4 μm with tapered groove sides, and further boron ions are implanted. The reason why the groove side surfaces are tapered is due to the physical impact of the heavy sulfur contained in sulfur hexafluoride, and the tapered shape is regulated by the side etching width. Therefore, the side etching width I becomes very important. Further, boron ions are implanted into the p+ type channel cathode layer 15 (see FIG. 4(C)) in a post-process heat treatment. The mask 13 is a covering mask similar to the embodiment shown in FIG. 3 above.

Next, as shown in 41F (C+), after removing the mask 13, a heat treatment is performed to form a 5i02 film (thickness: 1000) 16 on the inside and upper surface of the groove 14, and the inside of the groove is further coated by CVD. A thick polycrystalline silicon film 17 is deposited on the surface including the groove 14 to bury the groove 14.

Next, as shown in FIG. 4(d), the polycrystalline silicon film 17 on the surface is removed by etching or polishing, and further,
The polycrystalline silicon film on the groove surface is oxidized to form a 5t02 film 18.
, and complete the device isolation zone for groove isolation.

This formation method has the advantage that discontinuous lines are not generated and the channel cut layer 15 is also formed on the side surfaces, but it is difficult to control the side etching width L (see FIG. 4 (al)), and Since the formation method is similar to that of , the width of the upper surface becomes wide, making it difficult to form finely.

Therefore, the present invention proposes a method of forming an element isolation band made of trench isolation that eliminates such drawbacks.

[Means for solving the problem] The problem is that in the method of forming an isolation band, which is formed by selectively forming a groove of a predetermined depth on the surface of a semiconductor substrate and burying an insulator inside the groove, several problems arise. This problem is solved by a semiconductor device manufacturing method that includes a step of etching only a portion of the structure to a certain depth using an etching agent that is selective to the crystal direction during the formation of the structure to form sloped portions around the bottom surfaces of several structures. be done.

[Operation] That is, in the groove separation method, the present invention etches only a partial depth using an etching agent (solution or gas) that is selective to the crystal direction to form an inclined portion around the bottom of the groove. .

This will prevent discontinuities from forming in the buried insulator.
In addition, an element isolation band that can be easily miniaturized is formed.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views in order of steps of a method for forming an isolation band according to an embodiment of the present invention.

As shown in FIG. 1(a), a mask 22 is provided on a p-type silicon substrate 21, and the exposed silicon substrate 21 is etched with a caustic potash (KOH) solution to a thickness of about 1 μm, resulting in a tapered shape as shown in the figure. A recess 23 with side surfaces is formed, and boron ions are implanted and heat treated to form a p-type leak prevention layer 24.The caustic potash solution is selective to the silicon substrate in the direction of crystallization. Since etching proceeds only in the crystal direction (111) with an etching solution having
The mask 22 is the same as the embodiment shown in FIGS. 3 and 4 above.
This is a covering mask with a film thickness of about 1 μm, which is made by laminating a SiO2M, Si3N4, PSG, or resist film.

Next, as shown in FIG.
A trench 25 with a depth of 2 to 3 μm is formed, and boron ions are further implanted. Then, by this vertical anisotropic dry etching, the above-mentioned tapered side surface is directly formed on the side surface of the bottom. In addition, by implanting boron ions, the p+ type channel cupping layer 26 can be
(See FIG. 1(C)) is formed.

Next, as shown in FIG. 1 (C1), after removing the mask 2, a 5i02 film (thickness: 1000) 27 is formed on the inside and upper surface of the groove 3 by heat treatment, and then by CVD method.
A thick polycrystalline silicon film 28 is deposited on the surface including the inside of the groove to bury the groove 25. Then, the polycrystalline silicon film 28 is stacked in the line direction as shown by the dotted line in the figure.

Next, as shown in FIG. 1+d+, the polycrystalline silicon film 6 on the surface is removed by etching or polishing, and the polycrystalline silicon film on the trench surface is further oxidized to form a 5i02 film 29, which separates the trench. Complete the device isolation band.

According to such a forming method, grooves can be formed with high precision, and discontinuous lines arising from the corners of the bottom surface are eliminated, and low-density portions are significantly reduced. The dotted line in the polycrystalline silicon film in the figure is the direction of stacking of the polycrystalline silicon film. Furthermore, since the area of the p+ type channel layer 26 is expanded, the effect of preventing channel leakage is increased, and since the leakage prevention layer 24 is formed on the surface, surface leakage and fluctuations in threshold voltage are also suppressed. . Furthermore, according to this formation method, it becomes easy to miniaturize the element isolation band.

Next, FIGS. 2(a) to tel show step-by-step cross-sectional views of another method of forming an isolation band according to the present invention.

First, as shown in Fig. 2(a), the crystal axis direction (100
), a mask 32 is formed on the silicon substrate 31, boron ions are implanted into the exposed portion of the substrate (element isolation band formation region), and a p+ type leak prevention layer 33 is formed by heat treatment.

Note that the mask 32 is the same as in FIG. 1 above, and is a SiO2 film.

It is a covering mask with a film thickness of about 1 μm, which is made by laminating a Si3N4 film, a PSG film, or a resist film.

Next, as shown in FIG. 2 (bl), the exposed silicon substrate 31 is etched by an anisotropic dry etching method using chlorine-based gas, for example, RIB using 5iC14 gas.
A groove 34 with a width of 1 μm and a depth of 2 to 3 μm is etched.
form.

Then, as shown in FIG. 2(C), the groove 34 is further
The film is etched with a caustic potash solution to a film thickness of about 100 μm to form a bottom with tapered sides as shown in the figure.
Next, boron ions are implanted. As mentioned above, since the caustic potassium solution is an etching solution that is selective to the crystal direction, etching progresses only in the crystal direction (111).
A tapered side surface as shown in the figure is formed. Further, by implanting boron ions, a p+ type channel cut layer 35 (see FIG. 2(d)) is formed in the next step of heat treatment.

Next, as shown in FIG. 2 Fdl, after removing the mask 32, heat treatment is performed to form a SiO2 film (
A thick polycrystalline silicon film 37 is formed on the surface including the inside of the trench by CVD, and the trench is buried. Then, the polycrystalline silicon film 37 is laminated in the line direction shown by the dotted line in the figure.

Next, as shown in FIG. 2(e), the polycrystalline silicon film 37 on the surface is removed by etching or polishing, and further,
The polycrystalline silicon film on the groove surface is oxidized to form a 5i02 film 38.
, and complete the device isolation band for groove isolation.

According to this forming method, similarly to the above example, discontinuous lines arising from the corners of the bottom surface are eliminated, and the area of the p + type channel cut layer 26 is expanded, the effect of preventing channel leakage is increased, and the surface The surface leakage and threshold voltage fluctuations are suppressed by the leakage 11J stopper Ji24. Furthermore, it becomes easy to miniaturize the element isolation band.

The above embodiments were explained using the IOP method, but
It goes without saying that the present invention can be similarly applied to an oxide film trench separation method in which only an oxide film is buried in the trench.

[Effects of the Invention] As is clear from the above description, according to the present invention, the discontinuous line of the buried insulator is eliminated, the low density portion is eliminated, and the area of the p4 type channel cut layer 26 is expanded. , the effect of preventing channel leakage becomes greater. Further, according to the present invention, an element isolation band that can be easily miniaturized can be obtained.

[Brief explanation of drawings]

Figures 1 (a) to (dl) and Figures 2 (al to (el) are sectional views in the order of the formation steps according to the present invention; Figures 3 (al to (C) and Figures 4 (a) to (d) are It is a sectional view in the order of conventional forming steps. In the figure, 1., 1.1.21., 31 are p-type silicon substrates, 2
, 13.22.32 is a mask, 3, 14.25.34 is a groove, 4, 1.5.24.26.33.35 is a channel cut layer, 5, 7.16.18.27.29. 36.38
indicates a 5i02 film, and 6, 17, 28, and 37 indicate a polycrystalline silicon film. Figure 1 Jukei/L shape (1) Figure 3 Jukei N type captive ■) Figure 4

Claims (3)

[Claims] (1) In a method for forming an isolation band in which a groove of a predetermined depth is selectively formed on the surface of a semiconductor substrate and an insulator is buried inside the groove, selectivity is achieved in the crystal direction when forming the groove. 1. A method of manufacturing a semiconductor device, comprising the step of etching to a partial depth using a sticky etchant to form an inclined portion around the bottom of the groove. (2) In the method for forming the device isolation band described above, in the initial stage of etching the groove, etching is performed only to a partial depth using an etchant that is selective to the crystal direction to form an inclined portion around the bottom surface. A method for manufacturing a semiconductor device according to claim 1, characterized in that: (3) In the above method for forming an isolation band, at the final stage of etching the trench, etching is performed to a partial depth using an etchant that is selective to the crystal direction to form a sloped portion around the bottom surface. A method for manufacturing a semiconductor device according to claim 1, characterized in that: