JPS62102481A - Read circuit - Google Patents

Abstract

PURPOSE:To completely eliminate the influence of excessive compensation caused by a cosine equalizer and to improve the reliability of information reading by converting the delay amount of a delay line into an optimum value corresponding to the characteristic of a read signal. CONSTITUTION:A memory circuit 16 stores information setting a delay amount suitable for the read waveform of a magnetic head whose address is designated, transmits a binary delay setting signal to a signal line 31, on/off controls analog switches 7-12 and appropriately selects the output signals of delay lines 2 and 4. When the isolation wave semi-value width of the read signal 1 is wide, the switches 7 and 10 and the remaining ones are turned on and off, respectively. An adder 6 synthesizes the signal 1 and the output signal of the switch 10, and subtracts 27 the attenuation output 26 from a buffer output 25. If the isolation wave semi-value width of the signal 1 is narrow, only the switches 8 and 11 are turned on. As a result, no undershoot occurs in any cases, and a satisfactory waveform can be obtained accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a read circuit in a magnetic storage device such as a magnetic probe disk device or a magnetic tape device.

(Prior Art) Conventionally, in readout circuits for magnetic disk devices, magnetic tape devices, etc., a configuration shown in FIG. 3 has been adopted for a cosine equalization circuit used for equalizing trench width.

The cosine equalization circuit shown in FIG. 3 inputs a delay line 2 for inputting from a read signal Y signal line 1 of a magnetic disk device, a terminating resistor 3 of the delay line 2, and an output signal of the delay line 2. a buffer circuit 13 for
A delay line 4 for inputting the output signal of the buffer circuit 13 from the signal line 20, a terminating resistor 5 of the delay line 4, and a Z-input of the output signal on the signal line 1 and the output signal of the delay line 4. Adder 6 for adding signals
, an attenuator 14 for inputting the output signal of the adder 6 and attenuating the amplitude of the signal, and a signal line 2 from the attenuator 14.
1 and the output signal from the buffer circuit 13 to the signal line 20, and a ninth subtracter 15 which takes the difference between the two signals.

FIG. 4 is a waveform diagram showing the waveforms χ of each part in FIG. In FIG. 4, the numbers represent the numbers of the signal lines shown in FIG.

Here, the polarity of the signal outputted from the attenuator 14 to the signal line 21 is reversed and is indicated by 21.

The waveform shown in FIG. 4 is a solitary wave in which adjacent magnetization reversals are far apart. In addition, τ is the delay line 2 and 4, respectively.
shows the delay time.

FIG. 4(a) shows the case where the half-width of the solitary wave on the signal line 1 is large, and FIG. 4(b) shows the case 7 where the half-width is small.

In FIG. 4(a), the waveform of the buffer output signal on the signal line 20 is delayed from the waveform of the read signal on the signal line 1 by the delay time τ of the delay line 2. In FIG. The waveform obtained by subtracting y from the buffer output signal (number -1'; zo) by the inverted output signal (number 2x) of the attenuator is the subtracter output signal (number 23).

As a result, the solitary wave half width TWIμ of the buffer output signal becomes small as shown in the solitary wave half width TWll of the subtractor output signal (number 23).

In general, waveforms with a large solitary wave half-width have large interference between adjacent waveforms due to magnetization reversal. Therefore, the amplitude of the bladder output signal changes greatly depending on the spacing of magnetization reversal, which has a big effect on the demodulation of the readout signal! give.

As mentioned above, the cosine equalization circuit shown in Figure 3 is intended to reduce the half-width of the solitary wave and reduce the amplitude change in the read signal due to interference between adjacent waveforms, so it has a large effect on the demodulation of the read signal. be.

In practical use, the circuit constants in FIG. 3, that is, the delay amount τ of the delay lines 2 and 4 and the attenuation amount of the attenuator 14, are set based on the case where the readout signal with the largest half-width of the solitary wave is input. ing. However, due to characteristic differences between the inner and outer peripheries of a magnetic disk and variations in characteristics of individual heads when a large number of magnetic heads are provided, a waveform with a very narrow half-width may occur. If input to the circuit shown in Figure 3, which is set for a waveform with a narrow half-width or a wide half-width, overcompensation will occur, so the attenuator output signal (number 23
) VC undershoot (number 24) may occur, leading to demodulation malfunction.

(Problems to be Solved by the Invention) The conventional bladder extraction circuit described above has the drawback that it is subject to restrictions on improving the waveform of the read signal due to variations in characteristics between magnetic heads and differences in characteristics between the inner and outer circumferences of the magnetic disk. was there.

41 The purpose of the present invention is to eliminate the above drawbacks and easily improve the waveform of the read signal by converting the delay amount of the delay line provided in the cosine equalizer to an optimal value corresponding to the characteristics of the read signal. An object of the present invention is to provide a readout circuit configured to enable the above-mentioned reading circuit.

(Problem! Means for Solving) The readout circuit according to the present invention includes a storage circuit, a first delay line, a first selection circuit, a buffer circuit, a second delay line, and a second selection circuit. , an adder, an attenuator, and a subtracter.

This is for storing a plurality of delay setting signals appropriately set for the recording position of the magnetic disk device in the storage circuit, and outputting the stored delay setting signal at the storage position indicated by the input address signal. be.

The first delay line is for inputting a read signal and providing different amounts of delay through a plurality of output terminals.

The first selection circuit is for selecting one of the delay amounts provided by the first delay line in response to one of the delay setting signals output from the storage circuit.

The buffer circuit is for buffering the output of the first selection circuit.

The second delay line inputs the output of the buffer circuit,
This is to provide different amounts of delay to each of the plurality of output terminals.

The second selection circuit is for selecting one of the delay amounts provided by the second delay line in response to another one of the delay setting signals output from the storage circuit.

The adder is for adding the output signals of the first and second selection circuits.

The attenuator is for attenuating the output amplitude of the adder.

The subtracter is for subtracting the output signal of the attenuator from the output signal of the buffer circuit.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a readout circuit according to the present invention.

Referring to FIG. 1, an embodiment of the invention includes a delay line 2, 4 having an output terminal 7 with a plurality of intermediate taps;
Resistors 3 and 5, adder 6, and analog switches 7 to 1
2, a buffer circuit 13, an attenuator 14, and a subtracter 15
, a memory circuit 16, and χ.

In FIG. 1, a resistor 3 is provided as a terminating resistance of the delay line 2 between the maximum delay terminal of the delay line 2 and the ground, and a resistor 3 is also provided between the maximum delay terminal of the delay line 4 and the ground. 5 is provided. Ninth, the output terminal of the delay amount τl of the delay line 2 and the signal input terminal of the analog switch 7 are connected, and the intermediate tag output terminal of the delay amount τ2 of the delay line 2 and the signal input terminal of the analog switch 8 are connected. connected, delay line 2
The intermediate tap output terminal of the delay amount τ3 of The output terminals 7 to 9 are connected to each other and further connected to the input terminal of the buffer circuit 13.The output terminal of the buffer circuit 13 is connected to the delay line 40 input terminal and the positive input terminal of the subtracter 15. Delay amount τl of delay line 4
The intermediate tap output terminal of the analog switch 10 is connected to the signal input terminal of the analog switch 10, the intermediate tap output terminal of the delay amount τ2 of the delay line 4 is connected to the signal input terminal of the analog switch 1, and the intermediate tap output terminal of the delay amount τ2 of the delay line 4 is connected to the signal input terminal of the analog switch 10. The intermediate tap output terminal is connected to the signal input terminal of the analog switch 12. The control input terminals of the analog switches 7.10 are connected to each other, the control input terminals of the analog switches 8.11 are connected to each other, and the control input terminals of the analog switches 9, 1
The two control input terminals are interconnected. The output terminals of the analog switches 10 to 12 are connected to each other and further connected to one input terminal of the adder 6. Adder 6
The other input terminal of the adder 6 is connected to the input terminal of the delay line 2, the output terminal of the adder 6 is connected to the input terminal of the attenuator 14, and the output terminal of the attenuator 14 is connected to the negative input terminal of the attenuator 15. has been done.

In FIG. 1, a selection circuit 17 for the output signal of the delay line 2 is configured by the analog switch 7-0.
Similarly, the analog switches 10 to 12 constitute a selection circuit for the output signal of the delay line 4.

The memory circuit 16 is of a non-volatile type, and stores delay amount setting information for setting a delay amount suitable for the read waveform of the magnetic head, which is designated by the input address signal on the signal line 30. From the address (memory location) specified by the input address signal input from line 30,
The stored information is output onto the signal line 31 as a delay setting signal.

In the manufacturing process of the magnetic disk device, the delay setting information is set by examining the waveform of the read signal at the main recording position of each head and determining values suitable for each. The input address signal on the signal line 30 does not have to be a signal corresponding to F versus IK for all recording positions of the magnetic disk device. For example, the entire radial recording range of the magnetic disk may be divided into several parts within a range that does not significantly affect the margin of signal detection operation, and a signal may be used to designate each part.

The delay setting signal on the signal line 31 is output in the form of a 3-pit binary signal, and is used to control on/off of the analog switches 7 to 12 and select the appropriate output signal of the delay line 2.4.

FIG. 2 is a waveform diagram showing waveforms 7 of various parts of the readout circuit shown in FIG. In FIG. 2, each number indicates the number 7 of the corresponding signal line.

Further, the number n represents the inversion of the output signal of the attenuator 14.

The waveform shown in FIG. 2 represents an isolated wave in which adjacent magnetization reversals are separated.

FIG. 2(a) is a waveform diagram illustrating the case where the solitary wave half width of the read signal is wide. In this case, the memory circuit 16 is set as described above and outputs a delay setting signal onto the next signal line 31 to turn on the analog switch 10Z and turn off the other analog switches. Therefore, delay line 2
．． It becomes 1 when the actual delay amount is 4. Buffer circuit 13
The output signal sent onto the signal line 25 is a signal delayed mainly by τl from the read signal of the magnetic disk device on the signal line 1, and has the same waveform as the read signal. The adder 6 combines the read signal 1 on the signal line 1 with the output signal of the analog switch 10, which is delayed mainly by 2.tau.l from the read signal. The waveform obtained by reducing the imaging width of the composite wave is the output signal (number core) of the attenuator 14. The waveform obtained by subtracting the attenuator output signal (number 26) by Y from the buffer output signal (number 25) is the output signal (number 27) of the subtracter 15. As a result, the solitary wave half width W3 of the buffer output signal becomes as small as the solitary wave half width TW31 of the attenuator output signal (number 27).

FIG. 2(b) is a waveform diagram illustrating a case where the half-width of a solitary wave of a read signal is narrow. In this case, the delay setting signal sent from the memory circuit 16 to the signal line 31 is transmitted to the analog switch 8.
, 117 is turned on, and the other analog switches are turned off. Therefore, the effective delay i of delay line 2.4
τ2 is smaller than μτ1. In this case too, Figure 2(a)
Similarly, the solitary wave half-width Tw4 of the buffer output signal becomes small like the solitary wave half-width TW41 of the attenuator output signal (number 27), but as shown in FIG. 4(b), undershoot due to overcompensation ( No. 24) does not occur.

The thread formed by turning on the analog switches 9 and 120 has a delay amount τ3. This thread is applied when the half-width of a solitary wave is even narrower than that shown in FIG. 2(b), and the delay amount τ3 is smaller than the delay amount τ2.

As described above, even if the solitary wave half-width of the bladder ejection signal is wide or narrow, undershoot tra does not occur and the half-width can be made narrower than the same half-width, resulting in good waveform improvement. It can be achieved.

(Effects of the Invention) As explained above, the present invention corresponds to the characteristics of the readout signal with the delay amount χ of the delay line provided in the cosine equalizer and converts it to an optimal value, thereby reducing the delay between the magnetic head and the magnetic disk. The effects of overcompensation of the cosine equalizer caused by variations in the characteristics of the magnetic disk and differences in characteristics between the inner and outer circumferences of the magnetic disk can be completely eliminated, and the reliability of information reading can be further improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment Z of a readout circuit according to the present invention. FIG. 2 is a waveform diagram showing the main signal general form Z of the readout circuit shown in FIG. FIG. 3 is a block diagram showing an example of a readout circuit according to the prior art. FIG. 4 is a waveform diagram showing main signal waveforms Y of the readout circuit shown in FIG. 2.4...Delay line 3,5...Resistor 6.
...Touguchi Calculator 7-12...Analog switch 13
...Buffer circuit 14...Attenuator 15...Subtractor 16...Storage circuit 17, 18...
selection circuit

Claims (1)

[Claims] a storage circuit for storing a plurality of delay setting signals appropriately set with respect to recording positions of the magnetic disk device and outputting the stored delay setting signals at the storage positions indicated by the input address signal; a first delay line for inputting a read signal and providing different amounts of delay through a plurality of output terminals; and a first delay line for receiving one of the delay setting signals output from the storage circuit. a first selection circuit for selecting one of the delay amounts provided by the input terminal; a buffer circuit for buffering the output of the first selection circuit; and a plurality of output terminals to which the output of the buffer circuit is input. a second delay line for providing different amounts of delay, respectively, and one of the amounts of delay provided by the second delay line in response to the other one of the delay setting signals output from the storage circuit; a second selection circuit for selection, an adder for adding the output signals of the first and second selection circuits, an attenuator for attenuating the output amplitude of the adder, and the buffer circuit. A readout circuit comprising: a subtracter for subtracting the output signal of the attenuator from the output signal of the attenuator.