JPS6210974A - Method for driving solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve the efficiency of transfer by driving a gate electrode of the side that transfers charge plural times while keeping the gate electrode of the side to which charge is transferred at high level. CONSTITUTION:One or more of charge coupled element gate electrodes 3, 4, 7, 8 are kept at low level during the period of transfer in a vertical direction, and one or more of charge coupled element gate electrodes 3, 4, 7, 8 are made to intermediate level. A moment in which the voltage of high level is applied to the gate electrodes at both sides which these electrodes are interposed is provided, and the gate electrode of the side that transfers charge is driven plural times while keeping the gate electrode of the side of which the charge is transferred at high level. Thus, the efficiency of transfer is improved even when a surface channel charge coupled element is used as the charge coupled element of vertical direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for driving a solid-state imaging device that can increase transfer efficiency without reducing the amount of charge transferred in the vertical direction.

[Conventional technology]

Recently, the resolution of solid-state imaging devices has been increasing, and their integration density has been increasing. However, as resolution increases, the area of a photoelectric conversion element per pixel decreases, resulting in a decrease in sensitivity. In order to prevent this, a charge coupled device (Charge Coupled Device) is used for signal succession.
A solid-state imaging device using an e+ (hereinafter referred to as rccDJ) (hereinafter referred to as an rccrt-type solid-state imaging device) is advantageous.

In this case, it is necessary to arrange a photoelectric conversion element and a COD within one pixel. FIG. 5 shows the layout of a general solid-state imaging device. A conventional solid-state imaging device includes, for example, photoelectric conversion elements 1 and 6 such as photodiodes, and a CCD channel 2.
, the first part of the CCD. Second. Third. Fourth gate electrode 3.4
, 7, 8, and transfer gate electrodes 5.9.

Next, the operation of the apparatus configured as described above will be explained. After accumulating charges generated by light incident on the photoelectric conversion elements 1 and 6 for a certain period of time, the transfer gate electrodes 5.
9 to the gate I electrodes 3, 4, 7.8 of the COD and read out to CCI) (not shown). Therefore, in the conventional CCD type solid-state imaging device, the charge transfer capacity of the CCD is required to transfer the amount of charge accumulated in the photoelectric conversion element 1.6, and the area occupied by the COD in one pixel increases. Usually, a vertical CCD is called a haired channel CCD (Ruried CCD, hereinafter [BCC
However, in the case of BCCD, the amount of charge transferred is generally small, and for this reason, as the number of pixels increases, the area of BCOD occupied by the pixel will reach 30 to 50%, and the photoelectric conversion element 1.6 It becomes impossible to increase the area of For this reason, in the current CCD type solid-state imaging device, the amount of transferred charge of the vertical BCCD is small and the sensitivity is low.

[Problems to be Solved by the Invention] In order to overcome the above drawbacks, a surface channel CCU (Surface CCD, hereinafter referred to as "5C") is used instead of a BCCr).
There is a method using a CDJ). However, in this case, there was a problem in that even though the amount of transferred charge increased, the transfer efficiency deteriorated and the resolution in the vertical direction deteriorated.

The present invention has been made in view of these points, and its purpose is to provide a driving method with high transfer efficiency in a solid-state imaging device in which the vertical COD is configured with 5 COD or a CCD with characteristics close to 5 COD. It's about doing.

[Means for solving problems]

In order to solve these problems, the present invention fixes at least one charge-coupled device gate electrode to a low level, sets at least one charge-coupled device gate electrode to an intermediate level, and fixes this charge-coupled device gate electrode to a low level during the vertical transfer period. There is a moment when a high level voltage is applied to the gate electrodes on both sides of the gate electrode, and multiple gate electrodes on the side to which charge is transferred are simultaneously applied while the gate electrode on the side to which charge is transferred is kept at a high level. It is designed to be driven.

[Effect]

In the present invention, the transfer efficiency is improved even when 5 CCDs are used as vertical CCDs. [Embodiment] An embodiment of a method for driving a solid-state imaging device according to the present invention will be described with reference to FIGS. 1 and 2. A solid-state imaging device having the configuration shown in FIG. 5 is used, and a 5COD is used as a vertical COD.

Figure 1 ial ~ (dl is 1st, 2nd, 3rd, .
The clock signals φVI+ φVZ+ φV3+ φV4 applied to the fourth gate electrodes 3, 4, 7.8 are shown, and FIG. 2 shows the clock signals φ9, φv, φV3+
It shows the potential of 5COD when φV4 is applied.

In FIG. 1, 10 indicates a low level, 11 indicates a high level, and 12 indicates an intermediate level.

Clock signal φVl+φ9□ shown in FIG. 2(a),
φv3 and φV4 are stages (hereinafter referred to as "n stages")
The clock signal PφV indicates the signal applied to each gate electrode 3, 4, 7.8 of the (n-1) stage, and the clock signal R
φv1 indicates a signal applied to the first electrode of the (n+1) stage. FIG. 2(b) to +11 are each timing tl, t2. t3. t4゜t5. t6. t7. t8
It shows the potential under the gate electrode due to each clock signal in . Since charge transfer in the vertical direction is normally performed during the horizontal blanking period, transfer during this period was considered here. Also, here, photoelectric conversion element 1
．． The charge transfer method from 6 to 5 CCD is not considered.

At the timing of tl shown in FIG. 2 (bl), the gate electrode 3.
4.7, the voltage of the clock signal φVI+φV□3 φV3 is applied. However, each clock signal φVI+φ
9□, the voltage of φv3 is ■φyl-Vφ9. 〉■φV□
There is a relationship between Next, timing t2 shown in FIG. 2(C)
The charge (indicated by diagonal lines in the figure) is the clock signal φ9□.

The charge flows under the gate electrodes 4 and 7 to which φV3 is supplied, and at timing t3 shown at +dl in FIG. 2, most of the charge is transferred under the gate electrode 7. Next, Fig. 2(e) to (g)
At the timing t4 to t6 shown in FIG. 1, the gate electrode 3.
When clock signal φVI+φV2 is applied to 4, 1
The charges Q left behind in the second transfer are collected under the gate again.

To transfer the charge Q of the gate electrode 7 to the first gate electrode of the next stage ((n→1) stage), a method similar to the method described above is used. The result is timing t8 shown in FIG. 2 (0), and one stage of charge is transferred between timings t1 and t8. FIG. 2 fh) shows a state corresponding to (b).

Note that in the above embodiment, the drive for collecting the remaining charge Q is performed only once, but it may be performed multiple times. In addition, in FIG. 1, the clock signal level is set to only two values to simplify the explanation, but for example, if the clock signal level is set so that the reverse flow of charge from the gate electrode 7 to the gate electrode 3 does not occur, , it doesn't matter what clock signal level you use. Furthermore, as a second embodiment, a lock signal φVI+ is used as shown in FIG.
Similar effects can be obtained at the timings of φ9□ and φV3+φv4.

Further, in FIGS. 1 and 3, the clock signal φV□.

φv4 is set to move multiple times during one stage of transfer, but as a third embodiment, Fig. 4 1bl, (di
As shown in the figure, the same effect can be achieved even if the transfer is performed only once. Note that the clock signal φ shown in FIG. 4 (al, (01)
9. ．． φv3 is the same as the clock signal shown in FIG. 3 (al, (C1).

Further, in this embodiment, an example having two 5 COD gate electrode structures per pixel has been described, but the same operation can be performed if there are two or more gate electrodes.

〔Effect of the invention〕

As explained above, in the present invention, during the vertical transfer period,
At least one charge-coupled device gate electrode is fixed at a low level, at least one charge-coupled device gate electrode is set at an intermediate level, and there is a moment when a high-level voltage is applied to gate electrodes on both sides of the gate electrode. By driving the gate electrode on the charge transfer side multiple times while keeping the charge transfer side gate electrode at a high level,
Using surface channel charge-coupled devices as vertical charge-coupled devices also improves transfer efficiency, and the large charge-transfer capacity of surface-channel charge-coupled devices allows for smaller width charge-coupled devices, making it easier for photoelectric conversion devices. This has the effect of increasing the area and increasing sensitivity.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing a clock signal used in an embodiment of the method for driving a solid-state imaging device according to the present invention, FIG. 2 is a state diagram showing the potential under the gate electrode, and FIG. 3 is a waveform diagram showing the potential under the gate electrode. FIG. 4 is a state diagram for explaining the third embodiment, and FIG. 5 is a configuration diagram showing the general configuration of the solid-state imaging device. 1.6...Photoelectric conversion element, 2...CCD channel, 3,4,7.8...Gate electrode, 5.9...
・Transfer gate electrode.

Claims (1)

[Claims] A plurality of photoelectric conversion elements arranged two-dimensionally on a semiconductor substrate, surface channel charge-coupled devices formed vertically to read out signals from the photoelectric conversion elements, and charge-coupled devices formed horizontally. In a method for driving a solid-state imaging device having a device, during a vertical transfer period, at least one charge-coupled device gate electrode is fixed at a low level, at least one charge-coupled device gate electrode is set to an intermediate level, and the gate There is a moment when a high level voltage is applied to the gate electrodes on both sides of the electrode, and the gate electrode on the side where charge is transferred is driven multiple times while the gate electrode on the side where charge is transferred is kept at a high level. A method for driving a solid-state imaging device, characterized in that: