JPS619898A - Josephson memory element - Google Patents

Abstract

PURPOSE:To simplify constitution and to lighten considerably a burden imposed to a peripheral circuit by making a digital information memory superconduction closed loop for adopting an AC superconduction quantum interference element (rf-SQUID) constitution to a geometrically complete closed loop. CONSTITUTION:An rf-SQUID closed loop 10 involved in a memory function is a complete closed loop physically and geometrically. When write command currents Ix and Iy flow in the same direction in write only W/Y control lines 12 and 13 jointed magnetically to the closed loop 10, a ring current is produced on the superconduction closed loop 10. When a magnitude of the ring current exceeds a DC Josephson critical current value of a Josephson element 11, a flux quantum is caught in the superconduction loop 10, and a permanent current IL is generated, thereby storing a logic ''1''. When X and Y coordinates read command currents Ix' and Iy' flow in control lines 12' and 13', a sensor gate 15 is brought into the detection possible condition. Then a magnetic field induced by the permanent current IL is added, and the logic ''1'' is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Josephson memory element for storing and reading digital signals by utilizing the Josephson effect, which is one of cryogenic phenomena, and particularly relates to a Josephson memory element of persistent current memory type. This invention relates to improvements in memory elements.

There are several types of Josephson memory elements, but a persistent current memory type that selectively generates a persistent current in a closed loop in response to the digital information to be stored is '1' or '0'. The device has the advantage that it is easy to realize relatively high-speed operation.

Typical examples of the basic configuration of such conventional persistent current memory type Josephson memory elements are those shown in FIGS. 1 and 2.

The one shown in the first diagram includes a pair of terminals 2 and 3 for connecting a circuit current line or a gate current line 4 to a superconducting loop 1;
having a gate 5 generally consisting of three Josephson junctions;
Write control lines 6 and 7 are magnetically coupled to this gate 5, as shown surrounded by imaginary lines.

In principle, the writing control lines 6 and 7 may be made of one piece of wood, but
Generally, when such memory elements are integrated into an X, Y two-dimensional plane array, in order to address a specific memory element,
It is composed of two addressing lines 6 for the X coordinate and an addressing line 7 for the Y coordinate.

In addition, in order to read out whether the persistent current IL is flowing in the superconducting loop 1, that is, whether the stored information in the superconducting loop 1 is 1' or 0', this is also generally done. A DC superconducting quantum interference device consisting of a superconducting loop including two Josephson junctions, that is, a dc-3QUID, is used as the sense gate 9, and the main superconducting loop l is shown surrounded by a phantom line in the figure. are magnetically coupled to each other.

On the other hand, in the conventional Josephson memory element shown in FIG. However, other parts are basically the same as the case shown in the first figure. Therefore, the other components are given the same reference numerals as the corresponding components in FIG. 1, and the explanation thereof will be omitted.

In the conventional example shown in FIG. 1.2, writing of the input information logic "1" is carried out through the writing control lines 6 and 7 (generally serving as addressing lines for the X and Y coordinates). Writing of logical value "O" or erasing of memory contents is performed only when the command currents Iz, Iy and the loop control current or gate current 1g flowing through the loop control line 4 all rise above a predetermined threshold. This is performed by not flowing the gate radio wave Ig to the superconducting closed loop in the write mode.

Thus, as in writing the logical value "l°',
It is extremely difficult to align the three types of current as described above in a fraction of a second, especially in a circuit in which such memory elements are integrated, since the propagation paths of each signal are different.

Therefore, as a next best measure, in order to ensure circuit operation,
In order to create a moment when each type of signal current reliably coincides in time, it is necessary to deliberately consider overlapping, but even in such cases, with conventional memory elements such as this, it is sufficient to simply overlap each signal current. Rather, the important issue is the input order of each signal, that is, the timing sequence.

This is because malfunctions may even occur if each signal current is input in an order different from the predetermined sequence.

In fact, in conventional prototype circuits, it is extremely difficult to design a circuit to maintain this timing sequence as specified, and the negative phase applied to the peripheral circuits is also quite large.

In addition, when it comes to reading information, sense K]・9
In addition to the sense current or read command current Is via the line 8 to the line 8, a gate I-current rg must also be applied, as was also required during the writing described above.

In other words, the gate current of 1 g must be used in both the write circuit system and the read circuit system, which imposes quite severe restrictions on the current value range and makes the peripheral drive circuit system very complicated.

As a result, the fundamental drawback of such a conventional configuration is that in addition to the two types of write command current and read command current, a circuit current or gate current Ig given to the superconducting closed loop I itself is required. , at least three types of separate and independent signal current systems are required. From a structural standpoint, the superconducting closed loop 1 is geometrically structurally independent because it requires external circuit connection terminals to supply current from the external circuit system into the closed loop. The reason is that it is not a closed loop.

The present invention has been made in view of these facts, and not only provides a storage element with an easy configuration, but also reduces the types of input signal currents required, and further improves the timing sequence between each signal current. The object of the present invention is to provide a persistent current memory type Josephson memory element which is not very sensitive and therefore can simplify the configuration of the peripheral circuit system and increase the degree of freedom in design.

In order to achieve this object, in the present invention, first of all, a superconducting closed loop for digital information storage that adopts an AC superconducting quantum interference device (RF-5QUID) configuration is made into a completely closed loop in terms of geometric structure. That is, it has a completely closed structure without any connection terminals to the outside.

Then, the write control line in the write mode is magnetically coupled to the superconducting closed loop, and the read control line in the read mode is similarly magnetically coupled to this superconducting closed loop via the sense gate. so that it is combined with

In this way, the timing sequence between signal currents in different systems as in the past, for example, the timing sequence between the circuit current 1g system and the write command room mix, Iy system, or the same circuit current 1g system. There is no need to pay careful consideration to timing and sequence with respect to the read command current Ig system, and not only the peripheral circuit system is significantly simplified, but also the reliability of the circuit operation can be improved.

Generally, the write command current and the read command current are composed of two current components 1x, y; lx', Iy' for X and Y addressing, respectively. In the memory element having the configuration described above, a write operation and a read operation can be performed simultaneously with the address specification.

Furthermore, since the erase mode can be isometrically considered to be a logical write of 0°, this book also considers the erase mode to be included in the write mode.

A basic embodiment of a memory element 10 constructed in accordance with the idea of the present invention is shown in FIG.

To capture magnetic flux quanta for storing digital information, the RF-3 QUID type closed loop 10 composed of the Josephson element 11 and the superconducting line is used as described above.

One feature of the present invention, as mentioned above, is that the main closed loop 10 involved in this storage function is a completely closed loop both physically and geometrically. That is,
Gate current line 4 as seen in the conventional example shown in Figure 1.2
There are no lead-out terminals 2, 3, etc. for connecting to external circuits.

In order to selectively induce a persistent current in the superconducting closed loop 10 depending on the logical value of the input digital information to be stored, an X, Y address designation and write control line dedicated to the write mode is provided. 12.
13 is magnetically coupled to the sparrow, as shown surrounded by a phantom line frame 14.

Of course, the Josephson element 11 in the closed loop 10 is similar to the known RF-3QLIIO, and has a high speed when capturing magnetic flux.
Work as Sochi.

On the other hand, among the X and Y address designation and readout control lines 12' and 13' dedicated to the read mode, in this case, the Y coordinate address designation and control line 13' has a sense gate connected in series with the line. The sense gate 15 connects to the main closed loop IO via the virtual wire magnetic coupling part 19.
is combined with

On the other hand, the X-coordinate addressing and control line 12' magnetically connects the sense gate 15 at a different position from the magnetic coupling section 18 with the closed loop 10, as shown by the magnetic coupling section 20 in phantom. It is arranged to be connected to.

Furthermore, in this embodiment, the sense gate 15 employs a known three-junction asymmetric dc-5QIJrD using three Josephson junction elements 18, 17, and 18, improving read sensitivity and read current gain. This is the intended damping resistance.

However, the structure of the sense game 15 itself does not need to be understood, and may be of any known or existing structure as long as it is magnetically coupled to the superconducting closed loop IO.

The writing operation of the logical value "l" of this memory element is as follows.

Write-only X and Y address designation and control lines 12.1
3, address designation and write command electronic pulse lx,
When Iy flows in the same direction, as the current value increases in the transient state of the pulse, a ring current is generated in the superconducting closed loop lO in a direction that cancels out the magnetic field induced by both current components. occurs, and when the magnitude of this ring current exceeds the DC Josephson critical current value of the Josephson element 11 in the rf-9 QUI[l, magnetic flux quanta are captured in the superconducting loop lo through the element 11. , a persistent current IL occurs. That is, there is a persistent current I in the superconducting loop 10.
If the time when L is flowing corresponds to logic "1", then the logic "1" will be stored.

Of course, once ° "1" is stored, even if the input current pulses lx and Iy fall, the persistent current IL continues to flow in the superconducting closed loop 10 without attenuation, and the stored state can be maintained. can.

On the other hand, writing (or erasing) the information logic "o" can be done by simultaneously changing the direction of the write command current pulses Ix and Iy to the direction opposite to that when writing the logic "°1" as before. .

However, if only one of them is not flowing, or if they are flowing in opposite directions, the writing of information "O'" and "I'" should not occur at the same time.

This is the magnitude of each current, the critical current value of the superconducting closed loop,
This can be realized by considering the degree of magnetic coupling, etc. in the design, but in this way, when the memory elements of this embodiment are assembled into a general X, Y two-dimensional plane array to form an integrated circuit, the logic " Whether it's the writing of ``l'' or the logic of ``o,'' regardless of which direction the currents I and Iy are flowing, they both flow in the same direction (positive or negative) and have the same magnitude, which is both addressing and control. Since there can be only one element located at the intersection of the lines 12.13, write ° "0'" only to the addressed only element, depending on the sign of both currents lx and Iy at that time. or write "1'".

Next, reading of stored information from this memory element will be explained.

In the read mode, the control lines 12 and 13 used during writing are not used at all, but dedicated addressing and reading control lines 12' and +3' are used.

When the X-coordinate addressing/reading command current Ix' and the Y-coordinate addressing/reading command current HyI are passed through both lines +2' and 13', the sense gate 15 is in a detectable state, that is, the voltage still remains as it is. It does not switch to the state, but when additional magnetic energy is applied from the outside, it detects this and becomes an enable state that can easily transition to the voltage state.

Therefore, when a logic "1" is stored in the superconducting closed loop 10 and a persistent current IL is flowing, the magnetic field induced by this is added, and the sense gate 15 changes to a voltage state, which causes a logic "1" to flow. 1” is read.

Of course, as is clear from the above, if the logic "0" is stored in the superconducting closed loop 10, that is, if the persistent current IL is not flowing or is wavering in the opposite direction, the sense Gate I.15 remains in a zero voltage state, thereby resulting in a logic "0'" reading.

Although the present invention has been described with reference to one illustrated embodiment, as can be understood from this mechanism, it is not intended to be used as a memory element to be integrated, but as a memory element used alone, such as a latch circuit. When using a bit element, there is naturally no need to specify an address, so the two sets of write control lines 12 and 13, one for the X coordinate and one for the Y coordinate in the illustrated embodiment, can be combined into one. Furthermore, each of the readout control lines 12' and 13' for the X and Y coordinates can also be reduced to only one line connected to the sense gate 15.

In any case, according to the present invention, it is possible to eliminate the need for the supply current of the superconducting closed loop and its terminals, simplifying the configuration itself, and significantly reducing the burden on peripheral circuits. Since it is possible to use completely separate dedicated circuit systems for the write mode and the read mode, the degree of freedom in circuit design is greatly increased and a sufficient operating margin can be provided.

In fact, the fact that there is no need to take any special consideration, especially regarding the timing sequence, is an extremely large effect, and it also allows for a large degree of freedom in the layout and configuration of the physical circuit board L. This will be a major stepping stone to the realization of integrated circuits using this type of memory element, as it will make it easier to create an optimal design for miniaturization.

[Brief explanation of the drawing]

1 and 2 are two typical basic configuration diagrams of a conventional persistent current memory type Josephson memory element, and FIG. 3 is a schematic diagram of an embodiment of the Josephson memory element of the present invention. It is. In the figure, 10 is a superconducting closed loop consisting of an AC superconducting quantum interference device configuration, 11 is a Josephson junction element, 12 and 13 are control lines for writing, 12' and 13' are control lines for reading, and 15 is a sense gate. , 14, 15.20 is a magnetic coupling part.

Claims (1)

[Scope of Claims] 1) A superconducting closed loop for digital information storage, which is composed of an AC superconducting quantum interference element configuration and is formed as a completely closed loop having no connection terminal to the outside; A Josephson memory device comprising: a write control line magnetically coupled to the superconducting closed loop; and a read control line magnetically coupled to the superconducting closed loop via a sense gate. 2) The write control line and the read control line are each
The Josephson memory element according to claim 1, characterized in that the Josephson memory element comprises a set of two wires, one for the X coordinate and one for the Y coordinate, for addressing.