JPS6180858A - Power mosfet - Google Patents
Power mosfetInfo
- Publication number
- JPS6180858A JPS6180858A JP59201761A JP20176184A JPS6180858A JP S6180858 A JPS6180858 A JP S6180858A JP 59201761 A JP59201761 A JP 59201761A JP 20176184 A JP20176184 A JP 20176184A JP S6180858 A JPS6180858 A JP S6180858A
- Authority
- JP
- Japan
- Prior art keywords
- type layer
- power mosfet
- power
- type
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003071 parasitic effect Effects 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000001172 regenerating effect Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明＆ｔパワーＭＯ８ＦＥＴにおける寄生バイポーラ
トランジスタ防止技術に関する、〔背景技術〕
パワーＭＯＳ ｌ” Ｅ Ｔには横形オフセットゲート
構造と縦形Ｄ Ｓ Ａ （Ｄｉｆｆｕｓｉｏｎ ５ｅｌ
ｆ Ａｌ ｉｇｎｍｅｎｔ ）構造とがあり、このうち
後者は多数のセルを縦横等間隔に並べることにより高耐
圧化と大電流化が図られ、高電圧スイ・ノチ／グ用とし
て使用されることが知られている。（工業調査会発行電
子材料１９８１年９月Ｐ２２−２８）
この縦形ＤＳＡ構造のパワーＭＯ３ＦＥＴ＋７）各セル
は第３図に示すように底部にＫ 濃Ｋｎ＋型層２を有す
るｎ−型シリコン基板ｌをドレインとして、その表面の
一部上に絶縁膜４を介して形成したゲート（ポリＳｉゲ
ート）５をマスクに２ＪｔＫ拡散してｐ型層３とソース
ｎ＋型Ｎ６を形成したもので、ゲートへの電圧印加によ
ってゲート下σ）ｐ型層（チャネル部）を通るソース争
ドレイン電流を制御するようにＭＯ３ＦＥＴ動作するも
のである。[Detailed Description of the Invention] [Technical Field] Related to the present invention & parasitic bipolar transistor prevention technology in a power MO8FET [Background Art] A power MOS l”ET has a horizontal offset gate structure and a vertical DSA (Diffusion 5el).
The latter has a structure in which a large number of cells are arranged at equal intervals vertically and horizontally to achieve high withstand voltage and large current, and is known to be used for high-voltage switching. It is being (Electronic Materials Published by Kogyo Kenkyukai, September 1981, P22-28) Each cell of this vertical DSA structure power MO3FET+7 consists of an n-type silicon substrate l having a K-rich Kn+ type layer 2 on the bottom as shown in Figure 3. As a drain, a p-type layer 3 and a source n+ type N6 are formed by 2JtK diffusion using a gate (poly-Si gate) 5 formed on a part of the surface of the drain via an insulating film 4 as a mask. The MO3FET operates so as to control the source-drain current passing through the p-type layer (channel portion) under the gate by applying a voltage.
この縦形ＤＳＡ構造のパワーＭＯ８ＦＥＴはオン抵抗Ｒ
０Ｎが小さく、ゲート幅Ｗとゲート長りの比Ｗ／Ｌが太
き（得られ、増幅率ｇｍが大きくとれる、また、ゲート
・ドレイン間帰還容量Ｇｒ５３ が大きく、一方、入力
容量ｃｉｓｓ が大きいことからスイッチングレギュ
レータ、モータ制御などの電力スイッチング用として適
合している。This power MO8FET with vertical DSA structure has on-resistance R
0N is small, the ratio W/L of gate width W to gate length is large (obtained, the amplification factor gm can be large), the feedback capacitance Gr53 between the gate and drain is large, and the input capacitance ciss is large. It is suitable for power switching applications such as switching regulators and motor control.
このパワーＭＯ８ＦＥＴに内蔵されているダイオード（
ｐ！ｕ７６３とｎ−型基体１との間の接合ダイオード）
をフライホイールダイオードＦＲＤとして使用するＤＣ
／ＡＣインバーターブリッジ回路（第５図）においては
、対偶のＭＯ８ＦＥＴＱ、、Ｑ、 とＱ３．Ｑ３ とが
交互にスイッチング動作するが、その場合に次の問題が
生じる、すなわち、Ｑ、 、 Ｑ−がオン（Ｑ２− Ｑ
ｓがオフ）した状態からＱ、、Ｑ、を切ると、内蔵ダイ
オードＤ２−Ｄ３を通る回生電流ＩＤＲが急激に流れ、
Ｑ、をオンしり、が回復する間は導通状態にある。（第
４図参照）
このＩＤＲが流れこんだとき、チャネル部に近い部分で
寄生バイポーラトランジスタに、、Ｋ。The diode built into this power MO8FET (
p! Junction diode between u763 and n-type substrate 1)
DC using as flywheel diode FRD
/AC inverter bridge circuit (Fig. 5), paired MO8FETQ, ,Q, and Q3. Q3 and Q3 alternately switch, but in that case the following problem arises: Q, , Q- are on (Q2- Q
When Q, , Q are turned off from the state where s is off), the regenerative current IDR flows rapidly through the built-in diodes D2-D3,
When Q is turned on, it remains conductive while Q recovers. (See Figure 4) When this IDR flows into the parasitic bipolar transistor near the channel part, K.
（第３図）かオンし、ソースｎ＋型領（１セル）ｒ過剰
電流が流れて素子を破壊する。(FIG. 3) turns on, and excessive current flows through the source n+ type region (1 cell), destroying the device.
〔発明Ｑ〕目的〕
本発明は上記の問題を克服するためになされたものであ
り、その目的とするところをエパワーＭＯ８ＦＥＴにお
ける寄生バイポーラトランジスタによる電流集中を防ぎ
、耐圧を高めることにある。[Invention Q] Purpose The present invention was made to overcome the above problems, and its purpose is to prevent current concentration due to the parasitic bipolar transistor in the Epower MO8FET and to increase the withstand voltage.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである、すなわち、パ
ワーＭＯ８ＦＥＴにおいて、ノース領域にポリシリコン
等のバラスト抵抗を捜入することで寄生バイポーラトラ
ンジスタの動作を抑制し耐圧を向上し前記発明の目的を
達成できる。A brief overview of the typical inventions disclosed in this application is as follows. That is, in a power MO8FET, a parasitic bipolar transistor is eliminated by inserting a ballast resistor such as polysilicon into the north region. The object of the invention can be achieved by suppressing the operation and improving the withstand voltage.
第１図は本発明の一実施例を示すものであって、縦形Ｄ
ＳＡ構造パワーＭＯ３ＦＥＴにおける１セルの縦断面図
である。FIG. 1 shows an embodiment of the present invention, in which a vertical type D
It is a longitudinal cross-sectional view of one cell in the SA structure power MO3FET.
１はドレイン領域となるｎ型シリコン基板で底？ｆｉｉ
＆ＩＣＡａ度° 型層２′介ゝ”’（）”Ｌ／（７電極
膜”゛ １設けられる、
３はｐ型層でその表面上に絶縁膜４を介してポＩＪ Ｓ
ｉ等からなるゲート５が形成され、このゲートをマス
クとしてｐ型層３の表面の一部にソースとなるｎ 型拡
散）會６か形成されている。７はソースに接続されたバ
ラスト抵抗で例えばポリＳｉからなり、ゲートの上Ｋ
犯、”、１漠（Ｓ ＋ Ｏｔ膜）介して延設されている
。９はＣＶＤ（気相化学堆積）法によるＳｉｎ、膜、１
０はＡｌ（アルミニウム）よりなるソース電極（配線）
で一部はｐ型層表面に接続され、他の一部はＣＶＤ−８
ｉＯ３膜９のヌル・−ホールを介してバラスト抵抗７に
接続されている、
第２図Ｇ工上記Ｑ）催形ＤＳＡ袷造パワーＭＯ３ＦＥＴ
の平面Ｍであって、そのＡ−Ａ’ 切断面図が第１図に
対応する。1 is the n-type silicon substrate that becomes the drain region and is the bottom? fii
&ICAa degree ° type layer 2'``'()''L/(7 electrode film'' 1 is provided, 3 is a p-type layer and a po IJ S is provided on its surface via an insulating film 4.
A gate 5 made of a material such as i is formed, and using this gate as a mask, an n-type diffusion layer 6 which becomes a source is formed on a part of the surface of the p-type layer 3. 7 is a ballast resistor connected to the source, made of poly-Si, for example, and K above the gate.
9 is a Sin film by CVD (vapor phase chemical deposition) method.
0 is a source electrode (wiring) made of Al (aluminum)
A part is connected to the p-type layer surface, and the other part is connected to the CVD-8
Q) Formed DSA woven power MO3FET connected to the ballast resistor 7 through the null-hole of the iO3 film 9.
1, and its AA' cross-sectional view corresponds to FIG.
同図において、３ａは基板のｐ型層３の露出するコンタ
クト穴、７ａはバラスト抵抗７が露出するコンタクト穴
である６、
上記バラスト抵抗７はゲートｉｈ極を形成する不純物ド
ープド−ポリＳｉと同じものを使用することができる。In the figure, 3a is a contact hole through which the p-type layer 3 of the substrate is exposed, and 7a is a contact hole through which a ballast resistor 7 is exposed.6 The ballast resistor 7 is the same as the impurity-doped poly-Si that forms the gate IH electrode. things can be used.
このバラスト抵抗はポリＳ１平面形状（たとえば第２図
に示す、に、５な放射状形状）ＪＰ不純物のドーピング
量で決定され、その抵抗値はたとえば１セル当り２Ｏ２
以上とする。This ballast resistance is determined by the doping amount of the JP impurity in the poly S1 planar shape (for example, the radial shape shown in FIG. 2), and its resistance value is, for example, 2O2 per cell.
The above shall apply.
以上実施例で述べた本発明によれば、下記の理由により
発明の効果が得られる。According to the present invention described in the embodiments above, the effects of the invention can be obtained for the following reasons.
第６図は第３図に示したバラスト抵抗を入れないこれま
でのパワーＭＯ３ＦＥＴの等価回路図である。この場合
、寄生トランジスタ（Ｋｌ、に２）を通して回生電流Ｉ
ＤＲが流れソース近傍に′電流集中する。第８図はバラ
スト抵抗を入れない場合のパワーＭＯ８ＦＥＴチップの
全体平面図であって、ソース・ポンディングパッドＳ近
傍で電流集中による破壊（×印）が多くみられる。FIG. 6 is an equivalent circuit diagram of the conventional power MO3FET shown in FIG. 3, which does not include a ballast resistor. In this case, the regenerative current I through the parasitic transistor (Kl, 2)
DR flows and current concentrates near the source. FIG. 8 is an overall plan view of a power MO8FET chip without a ballast resistor, in which many breakdowns (x marks) due to current concentration are seen near the source/ponding pad S.
第７図はバラスト抵抗Ｒ８を入れた本発明によるパワー
ＭＯ８ＦＥＴの等価回路図である、この場合、Ｒｓを挿
入することにより寄生バイポーラトランジスタへの回生
電流Ｉ。Ｒが分散し集中は回避できる、
第９図はバラスト抵抗を入れたパワーＭＯ８ＦＥＴチッ
プの全体平面図であって、ソース・ポンディングパッド
Ｓ近傍での破壊はみられなかった。FIG. 7 is an equivalent circuit diagram of a power MO8FET according to the present invention including a ballast resistor R8. In this case, by inserting Rs, a regenerative current I to a parasitic bipolar transistor is generated. R can be dispersed and concentration can be avoided. Figure 9 is an overall plan view of a power MO8FET chip including a ballast resistor, and no damage was observed near the source/ponding pad S.
このように本発明によれば、バラスト効果により、ソー
ス・ポンディングパッドＳ周辺のセルの寄生バイポーラ
トランジスタ動作が抑止され、破壊耐量が１０〜２０倍
に向上１−だ。すなわち、バラスト抵抗Ｒ８を入れない
従来例では破壊耐量が０１〜０．２Ａであるのに対し、
バラスト抵抗Ｒ８を入れた本発明の例では耐量は１．５
Ａ〜５Ａに向上することができた、
〔利用分野〕
本発明は特にモータ制御等のＤＣ／ＡＣインバータブリ
ッジ回路図に使用されるパワーＭ ＯＳ ＦＥＴに適用
して有効である。As described above, according to the present invention, the parasitic bipolar transistor operation of the cells around the source/ponding pad S is suppressed due to the ballast effect, and the breakdown resistance is improved by 10 to 20 times. That is, in contrast to the conventional example that does not include the ballast resistor R8, the breakdown resistance is 01 to 0.2 A.
In the example of the present invention including a ballast resistor R8, the withstand capacity is 1.5
[Field of Application] The present invention is particularly effective when applied to power MOS FETs used in DC/AC inverter bridge circuit diagrams for motor control and the like.
第１図は本発明の一実施例を示す縦形ＤＮＡ構造のパワ
ーＭＯ３ＦＥＴの一セル部分の縦断面図である。
第２図は第１図に示されるパワーＭＯ８ＦＥＴの平面図
である、
第３図はこれまでの縦形のＤＮＡ構造パワーＭＯ３ＦＥ
Ｔの縦断面図である。
第４図はパワーＭＯ８ＦＥＴの順方向′電流ＩＦが切れ
た後の回生電流ＩＤＨの形態を示す曲線図である。
第５図はＤ Ｃ／Ａ Ｃインバータブ９７９回路の例を
示す回路図である。
第６因、第７図はパワーＭＯ３ＦＥＴの等価回路図であ
る、
第８図、第９図はパワーＭＯ３ＦＥＴチ、プの全体平面
図であって電流集中の状態を示すものである。
１・・・ｎ−型Ｓｉ基体（ドレイン）、２・・・ｎ＋型
層、３・・・ｐ型層、４・・・絶縁膜、５・・・ゲート
（ポリＳｉ）、６・・・ｎ＋型型数散層ソース）、７・
・・バラスト抵抗（ポＩＪ Ｓ ｉ ）、８．９・・・
絶縁膜、１０・・・アルミニウム電極。
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５ 図
第 ６ 図
第 ７ 図
第 ８ 図
第 ９ 図FIG. 1 is a longitudinal sectional view of one cell portion of a power MO3FET having a vertical DNA structure, showing an embodiment of the present invention. Figure 2 is a plan view of the power MO8FET shown in Figure 1. Figure 3 is the conventional vertical DNA structure power MO3FE.
It is a longitudinal cross-sectional view of T. FIG. 4 is a curve diagram showing the form of the regenerative current IDH after the forward current IF of the power MO8FET is cut off. FIG. 5 is a circuit diagram showing an example of a DC/AC inverter tab 979 circuit. The sixth factor, FIG. 7, is an equivalent circuit diagram of the power MO3FET. FIGS. 8 and 9 are overall plan views of the power MO3FET chip, showing the state of current concentration. DESCRIPTION OF SYMBOLS 1...n-type Si base (drain), 2...n+ type layer, 3...p-type layer, 4...insulating film, 5...gate (poly-Si), 6... n+ type scattered layer source), 7.
...Ballast resistance (Po IJ S i ), 8.9...
Insulating film, 10...aluminum electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9
Claims (1)
ランジスタの動作を抑制するようにソース領域にバラス
ト抵抗が挿入されていることを特徴とするパワーＭＯＳ
ＦＥＴ。 ２、上記バラスト抵抗はゲート電極形成材料であるポリ
シリコンにより形成されている特許請求の範囲第１項に
記載のパワーＭＯＳＦＥＴ。 ３、上記パワーＭＯＳＦＥＴは縦形ＤＳＡ構造ＭＯＳＦ
ＥＴである特許請求の範囲第１項又は第２項に記載のパ
ワーＭＯＳＦＥＴ。[Claims] 1. A power MOS characterized in that a ballast resistor is inserted in the source region so as to suppress the operation of a parasitic bipolar transistor in the power MOSFET.
FET. 2. The power MOSFET according to claim 1, wherein the ballast resistor is made of polysilicon, which is a gate electrode forming material. 3. The above power MOSFET is a vertical DSA structure MOSF
The power MOSFET according to claim 1 or 2, which is an ET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201761A JPS6180858A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201761A JPS6180858A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6180858A true JPS6180858A (en) | 1986-04-24 |
Family
ID=16446494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59201761A Pending JPS6180858A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6180858A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6380572A (en) * | 1986-09-24 | 1988-04-11 | Fuji Electric Co Ltd | Conductivity modulation vertical mos-fet |
| JPH01248564A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Power transistor |
| EP0656661A1 (en) * | 1993-11-12 | 1995-06-07 | Nippondenso Co., Ltd. | DMOSFET with a resistance for improving the reverse bias conduction |
| EP0657947A1 (en) * | 1993-12-07 | 1995-06-14 | Nippondenso Co., Ltd. | Power converter |
| US5608616A (en) * | 1993-12-07 | 1997-03-04 | Nippondenso Co., Ltd. | Power converter |
| US5694311A (en) * | 1995-03-31 | 1997-12-02 | Nippondenso Co., Ltd. | Power supply system |
| US5780953A (en) * | 1993-12-07 | 1998-07-14 | Nippondenso Co., Ltd. | Alternator |
| EP0936677A1 (en) * | 1998-02-16 | 1999-08-18 | Asea Brown Boveri AG | Power semiconducteur device with an isolated gate electrode and its method of fabrication |
| JP2003234200A (en) * | 2001-11-07 | 2003-08-22 | Applied Films Gmbh & Co Kg | Plasma impedance adjustment device |
| JP2014003051A (en) * | 2012-06-15 | 2014-01-09 | Rohm Co Ltd | Switching device |
-
1984
- 1984-09-28 JP JP59201761A patent/JPS6180858A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6380572A (en) * | 1986-09-24 | 1988-04-11 | Fuji Electric Co Ltd | Conductivity modulation vertical mos-fet |
| JPH01248564A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Power transistor |
| EP0656661A1 (en) * | 1993-11-12 | 1995-06-07 | Nippondenso Co., Ltd. | DMOSFET with a resistance for improving the reverse bias conduction |
| US5696396A (en) * | 1993-11-12 | 1997-12-09 | Nippondenso Co., Ltd. | Semiconductor device including vertical MOSFET structure with suppressed parasitic diode operation |
| EP0657947A1 (en) * | 1993-12-07 | 1995-06-14 | Nippondenso Co., Ltd. | Power converter |
| US5608616A (en) * | 1993-12-07 | 1997-03-04 | Nippondenso Co., Ltd. | Power converter |
| US5780953A (en) * | 1993-12-07 | 1998-07-14 | Nippondenso Co., Ltd. | Alternator |
| US5694311A (en) * | 1995-03-31 | 1997-12-02 | Nippondenso Co., Ltd. | Power supply system |
| EP0936677A1 (en) * | 1998-02-16 | 1999-08-18 | Asea Brown Boveri AG | Power semiconducteur device with an isolated gate electrode and its method of fabrication |
| JP2003234200A (en) * | 2001-11-07 | 2003-08-22 | Applied Films Gmbh & Co Kg | Plasma impedance adjustment device |
| JP2014003051A (en) * | 2012-06-15 | 2014-01-09 | Rohm Co Ltd | Switching device |
| US9866143B2 (en) | 2012-06-15 | 2018-01-09 | Rohm Co., Ltd. | Switching device |
| US10630199B2 (en) | 2012-06-15 | 2020-04-21 | Rohm Co., Ltd. | Switching device |
| US11005387B2 (en) | 2012-06-15 | 2021-05-11 | Rohm Co., Ltd. | Switching device |
| US11509240B2 (en) | 2012-06-15 | 2022-11-22 | Rohm Co., Ltd. | Switching device |
| US11784580B2 (en) | 2012-06-15 | 2023-10-10 | Rohm Co., Ltd. | Switching device |
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