JPS617637A - Semiconductor - Google Patents
SemiconductorInfo
- Publication number
- JPS617637A JPS617637A JP59128907A JP12890784A JPS617637A JP S617637 A JPS617637 A JP S617637A JP 59128907 A JP59128907 A JP 59128907A JP 12890784 A JP12890784 A JP 12890784A JP S617637 A JPS617637 A JP S617637A
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- electrode
- semiconductor
- external lead
- composite material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体に関づるもので、特に発熱量の大きいパ
ワーＩＣやトランジスター等の熱歪に基づく障害を解消
したものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductors, and in particular solves problems caused by thermal distortion in power ICs, transistors, etc. that generate a large amount of heat.
一般に半導体は、電極又は基板（以下電極等と略記）上
に、半導体素子（以下素子と略記）を搭載し、該素子に
外部リードを接続した後、これをレジンモールド等によ
り封止したもので、電極等には伝熱性や導電性に優れた
Ｃｕ又はＣｕ合金が用いられている。しかしながら素子
とＣｕ又はＣｕ合金では熱膨張率が大ぎく異なるため、
素子を搭載するダイボンディング時の高温からの冷却や
使用（動作）時の発熱において、熱膨張差による過大な
応力が素子に作用し、該素子の性能低下や素子にクラッ
クを発生りる欠点がある。In general, a semiconductor is a device in which a semiconductor element (hereinafter abbreviated as an element) is mounted on an electrode or a substrate (hereinafter abbreviated as an electrode, etc.), external leads are connected to the element, and then this is sealed with a resin mold or the like. , Cu or Cu alloy, which has excellent heat conductivity and electrical conductivity, is used for electrodes and the like. However, since the coefficient of thermal expansion is very different between the element and Cu or Cu alloy,
Excessive stress due to the difference in thermal expansion acts on the element during cooling from high temperatures during die bonding to mount the element, and during heat generation during use (operation), resulting in deterioration of the performance of the element and generation of cracks in the element. be.
これを改善するため、従来は第３図に示すように、電極
等（１）の上に素子（２）をダイボンドにより搭載する
高Ｐｂ半田層（３）内に、ＷやＭＯからなる緩衝材（９
）を設けるか、又は電極等（１）をコバールやＮｉ−Ｆ
ｅ合金で形成している。面図において、（４）は素子（
２）のエミッターやベースを外部リード（５）（６）と
接続するＡ（−１％３ｉ合金線、（７）は素子（２）の
コレクターを電極等（１）を通して接続する外部リード
を示す。To improve this, conventionally, as shown in Figure 3, a buffer material made of W or MO was added to the high Pb solder layer (3) on which the element (2) is mounted on the electrode (1) by die bonding. (9
), or electrodes (1) are made of Kovar or Ni-F.
It is made of e-alloy. In the top view, (4) is the element (
A (-1% 3i alloy wire) connects the emitter and base of 2) with external leads (5) and (6), (7) indicates the external lead that connects the collector of element (2) through electrode etc. (1) .
Ｗ、’ＭＯ、’：］バール、Ｆｅ−Ｎｉ合金等は何れも
高価な金属で、伝熱性も劣るため、これを電極等に用い
ると半導体の熱抵抗を大きくし、これが設計上の障害と
なっており、このような障害は素子の大型化においても
重大な問題となっている。W, 'MO,': ] Var, Fe-Ni alloy, etc. are all expensive metals and have poor heat conductivity, so if they are used for electrodes, etc., they will increase the thermal resistance of the semiconductor, which can be a design obstacle. Therefore, such obstacles become a serious problem even when devices are made larger.
これを解決するため、電極等や緩衝材をＣｕとカーボン
繊維の複合材で形成することが試みられている。しかる
にＣｕとカーボン１Ｊｌｆｔを強固に界面接合させるた
めには、特殊な処理が必要となり、更に電極等や緩衝材
の成型を高温で行なうため、カーボンｍＨの損傷をまね
き易く、性能的にも、コスト的にも不都合なものとなる
。In order to solve this problem, attempts have been made to form electrodes and cushioning materials from a composite material of Cu and carbon fiber. However, in order to form a strong interfacial bond between Cu and carbon 1Jlft, special treatment is required, and electrodes and cushioning materials are molded at high temperatures, which can easily damage the carbon mH and increase performance and cost. It will also be inconvenient.
本発明はこれに鑑み、種々検討の結果、高性能で小型、
軽量化にも貢献できる経済的な半導体を開発したもので
、電極等の上に素子を搭載し、該素子に外部リードを接
続した後、これをレジンモールドにより封止した半導体
において、電極等を５ｉＣＩＩ維とＡア又はＡ（合金か
らなる複合材で形成したことを特徴とするものである。In view of this, and as a result of various studies, the present invention is a high-performance, compact,
We have developed an economical semiconductor that can also contribute to weight reduction. After mounting an element on an electrode, connecting an external lead to the element, and sealing it with a resin mold, the electrode, etc. It is characterized by being made of a composite material consisting of 5iCII fiber and A or A (alloy).
即ち本発明半導体は、第１図に示すように、電極等（１
）をＳｉＣ繊維とＡ（又はＡλ金合金複合材で形成し、
該電極等（１）の上に高ｐｂ半田を用いて素子（２）を
ダイボンディングにより搭載し、該素子（２）の１ミツ
ターを外部リード（５）と、ベースを外部リード（６）
と、それぞれＡＪ！−１％８１合金線（４）により接続
し、素子（２）のコレクターを電極等（１）を通じて外
部リード（７）に接続し、しかる後第２図に示すように
、レジンモールド（８）を施して封止したものである。That is, the semiconductor of the present invention, as shown in FIG.
) is formed from SiC fiber and A (or Aλ gold alloy composite material),
The element (2) is mounted on the electrode etc. (1) by die bonding using high pb solder, one portion of the element (2) is connected to the external lead (5), and the base is connected to the external lead (6).
and AJ respectively! -1% 81 alloy wire (4), the collector of the element (2) is connected to the external lead (7) through the electrode etc. (1), and then the resin mold (8) is connected as shown in Fig. 2. It is sealed by applying
ＳｉＣｍＮとしては、有機珪素化合物ポリマーを紡糸し
た先駆体を焼成して直径５〜５０μ程度の繊維とするか
、又はカーボン繊維を芯線としてその表面に、例えば化
学気相反応（ＣＶＤ）を応用して、ジクロルメチルシラ
ン蒸気とＨ２ガスの混合気流中、約１２００℃でＳｉＣ
を析出させた繊維を用いる。また複合材としＣは、上記
繊維を束ねて所望形状とし、これにＡ（又はｌｅ合金溶
湯を含浸させるか、あるいは繊維を束ねてシート状とし
、これとＡ（又はＡ（合金箔を積層するか、又はこれに
Ａ（又はへア合金粉をスラリー状として充填し、これを
ホットプレスにより所望形状に成型して複合化させると
共に電極等を形成する。SiCmN can be produced by firing a precursor obtained by spinning an organosilicon compound polymer into fibers with a diameter of about 5 to 50 μm, or by applying a chemical vapor phase reaction (CVD) to the surface using carbon fiber as a core wire. , SiC at about 1200°C in a mixed flow of dichloromethylsilane vapor and H2 gas.
The fibers that have been precipitated are used. Composite material C can be obtained by bundling the above fibers into a desired shape and impregnating them with A (or le alloy molten metal), or by bundling the fibers into a sheet shape and laminating this with A (or A (alloy foil)). Alternatively, this is filled with A (or hair alloy powder) in the form of a slurry, and then molded into a desired shape by hot pressing to form a composite, and electrodes and the like are formed.
このようにして形成した電極等に直接素子をダイボンデ
ィングにより搭載するか、又は電極等にＮｉ、Ｃｏ又は
これ等の合金、例えばＮ１−Ｃｏ 、Ｎ１−Ｂ、Ｎｉ
−Ｃｏ−Ｐ、Ｎｉ −８ｎ 、Ｃｏ−８ｎ等の合金を電
気メッキや蒸着等により被覆し、その上に素子を搭載づ
゛るか、更にはその上にＣｕ 、Ａｇ、Ａｕ １Ｓｎ
、５ｎ−Ｐｂ合金等を被覆して、その上に素子を搭載す
る。Either the element is directly mounted on the electrode etc. formed in this way by die bonding, or the electrode etc. is coated with Ni, Co or an alloy thereof, such as N1-Co, N1-B, Ni.
-Co-P, Ni-8n, Co-8n, etc. alloys are coated by electroplating, vapor deposition, etc., and the element is mounted on it, or Cu, Ag, Au 1Sn is coated on top of it.
, 5n-Pb alloy, etc., and the element is mounted thereon.
上記繊維とＡ（又はＡＪ２合金の複合材は、繊維の特性
、配列、配合量にもよるが、ＳｉＣ単独の！！紐を用い
た場合で熱膨張率を約５〜１０×１０−８／’Ｃの範囲
とすることが実用的であり、これよりＳｉＣを過剰にす
ると複合材全体の強度低下をきたす。この熱膨張率は素
子の３．１×１０’／’Ｃより大きいが、ＭＯｌＷ、４
２％Ｎｉ −Ｆｅ合金の熱膨張率に近・く、ダイボンデ
ィング時や使用時における素子の特性低下やクラック発
生を有効に防止することができる。更に低熱膨張率化し
たい場合にはカーボン繊維上にＳｉＣを析出させたｍ維
を用いる。カーボン繊維はＳｉＣよりも低熱膨張率であ
るが、ＡＪ２との濡れ性が悪く、Ａ（との間にＡｆ＋
０３等の反応生成物を発生し易いため、そのままでは使
用できないが、表面にＳｉＣを析出させて被覆すること
により、上記欠陥は解消し、熱膨張率も３〜８ｘ１０’
／’Ｃ程度とすることができる。The composite material of the above fibers and A (or AJ2 alloy) has a thermal expansion coefficient of about 5 to 10 x 10-8 / It is practical to keep the SiC in the range of , 4
It has a coefficient of thermal expansion close to that of 2% Ni-Fe alloy, and can effectively prevent deterioration of device characteristics and generation of cracks during die bonding and use. If it is desired to further reduce the coefficient of thermal expansion, m-fibers in which SiC is precipitated on carbon fibers are used. Although carbon fiber has a lower coefficient of thermal expansion than SiC, it has poor wettability with AJ2, and there is a gap between Af+
However, by precipitating and coating the surface with SiC, the above defects are eliminated and the thermal expansion coefficient is 3 to 8 x 10'.
/'C.
しかしてＳｉＣ析出被覆厚さはＡｊ！どの濡れ性の面か
ら０．１μ以上、実用上０．１〜１．０μとすることが
望ましい。However, the thickness of the SiC deposited coating is Aj! In terms of wettability, it is preferably 0.1 μ or more, and practically 0.1 to 1.0 μ.
本発明半導体は上記複合材からなる電極等の上に素子を
搭載したものであるが、Ａ柔酸化皮膜の発生により、素
子のダイボンディングの障害となる場合には、電極等の
上にＮｉ、Ｃｏ又はこれ等の合金を被覆するとよい。こ
れ等の被覆は電極等の耐食性を向上するばかりか、／’
１とろう材の拡散反応による接合劣化を防止することも
できる。しかしてその厚さは１０μ以下とする必要があ
り、皮膜厚さが１０μを越えると熱歪が再発する恐れが
ある。更にまたＣＵ 、Ａ（１。The semiconductor of the present invention has an element mounted on an electrode etc. made of the above-mentioned composite material, but if the generation of A soft oxide film becomes an obstacle to die bonding of the element, Ni, Ni, etc. are placed on the electrode etc. It is preferable to coat with Co or an alloy thereof. These coatings not only improve the corrosion resistance of electrodes, etc.
It is also possible to prevent joint deterioration due to diffusion reaction between No. 1 and the brazing filler metal. However, the thickness must be 10 μm or less, and if the film thickness exceeds 10 μm, there is a risk that thermal distortion will occur again. Furthermore, CU, A(1.
ＡＵ 、、Ｓｎ 、５ｎ−ｐｂ金合金を被ｉ ｔ ｈ
’Ｌ；ｆ、素子の搭載接合作業を容易にし、半導体とし
ての特性を長時間安定させることかできる。AU,,Sn,coated with 5n-pb gold alloy
'L;f, It is possible to facilitate the mounting and bonding work of elements and to stabilize the characteristics of the semiconductor for a long time.
〔実施例）
有機珪素化合物ポリマーを紡糸した先駆体を焼成して線
径１２μのＳｉＣ繊維を作成し、これを平面上で直角に
交差ざゼて配置し、これに純ＡＪ２溶湯を含浸させてＳ
ｉＣ量６０ ｖｏ１％、厚さ１．２＃、巾１８麿、長さ
ｉｏｍのコレクターを兼ねた電極を作成し、その表面に
厚さ３．５μのＮｉメッキを施した後、第１図に示づよ
うに電極上に高Ｐｂ半田を用いで３ｉ素子をダイボンデ
ィングにより搭載した。次に素子のエミッター及びベー
スをそれぞれ線径３５μのＡＪ！−１％３ｉ合金線によ
り外部リードと接続し・、コレクターを電極を介して外
部リードと接続した。外部リードには高導電性のＣｕ
−０，１５％ｓｎ合金条（厚さ０．３５Ｉｌｌｆｆ）を
プレス打抜きにより成形し、表面にＡｇメッキを施した
。次に第２図に示すように素子をゲル状絶縁物Ｃ処理し
てからレジンモールドを施して本発明半導体を製造した
。[Example] SiC fibers with a wire diameter of 12 μm were created by firing a precursor obtained by spinning an organosilicon compound polymer, and the fibers were arranged so as to intersect at right angles on a flat surface, and were impregnated with pure AJ2 molten metal. S
An electrode with an iC content of 60 VO1%, a thickness of 1.2 #, a width of 18 mm, and a length of iom was made to serve as a collector, and the surface was plated with Ni to a thickness of 3.5 μm, as shown in Figure 1. As shown, a 3i element was mounted on the electrode by die bonding using high Pb solder. Next, connect the emitter and base of the device to each AJ! with a wire diameter of 35μ. The collector was connected to the external lead through an electrode. Highly conductive Cu for external leads
A -0.15% sn alloy strip (thickness: 0.35 Illff) was formed by press punching, and the surface was plated with Ag. Next, as shown in FIG. 2, the device was treated with a gel-like insulator C and then resin molded to produce a semiconductor of the present invention.
この本発明半導体について、重量及び熱抵抗を測定した
。これを高導電性の無酸素銅条（厚さ０．８５ ｔｔｔ
ｍ、中１８舖、長さ１０＃）からなる電極を用い、第３
図に示すように高半田ｐｂ層中にＭＯ板を緩衝材として
用いて素子を搭載した従来の半導体と比較ターると、本
発明半導体は重量で約半分、熱抵抗で０．０２℃／Ｗと
従来半導体の０．０３℃／Ｗより約３５％低くなった。The weight and thermal resistance of the semiconductor of the present invention were measured. This was made into a highly conductive oxygen-free copper strip (thickness 0.85 ttt
Using an electrode consisting of 18 mm (medium) and 10 # length, the third
As shown in the figure, when compared with a conventional semiconductor in which an element is mounted in a high solder PB layer using an MO board as a buffer material, the semiconductor of the present invention has a weight of about half, and a thermal resistance of 0.02°C/W. This is about 35% lower than the 0.03°C/W of conventional semiconductors.
以上はトランジスターの例について説明したが、これに
限るものではなく、ＩＣその他の半導体についても同様
の効果を得ることができるものである。Although the above description has been made using an example of a transistor, the present invention is not limited to this, and similar effects can be obtained with ICs and other semiconductors.
このように本発明によれば、特に大電流半導体や大径素
子を用いた半導体において、最大の問題である熱歪を解
消することができるもので、工業上顕著な効果を秦する
ものである。As described above, according to the present invention, it is possible to eliminate thermal distortion, which is the biggest problem especially in large current semiconductors and semiconductors using large diameter elements, and it has a significant industrial effect. .
第１図は本発明半導体の素子搭載状態の一例を示す平面
図、第２図は本発明半導体の一例を示す断面図、第３図
は従来半導体の一例を示す断面図である。
１・・・電極等
２・・・素子
３・・・高ｐｂ合金半田
４・・・Ａぶ−１％Ｓ１合金線
５．６．７・・・外部リード
８・・・レジンモールド
９・・・緩衝材FIG. 1 is a plan view showing an example of a semiconductor device according to the present invention in which elements are mounted, FIG. 2 is a cross-sectional view showing an example of the semiconductor device according to the present invention, and FIG. 3 is a cross-sectional view showing an example of a conventional semiconductor. 1... Electrode, etc. 2... Element 3... High pb alloy solder 4... Ab-1% S1 alloy wire 5.6.7... External lead 8... Resin mold 9...・Cushioning material
Claims (2)
外部リードを接続した後、これをレジンモールドにより
封止した半導体において、電極又は基板をＳｉＣ繊維と
Ａｌ又はＡｌ合金からなる複合材で形成したことを特徴
とする半導体である。(1) In a semiconductor in which a semiconductor element is mounted on an electrode or substrate, external leads are connected to the element, and then sealed with a resin mold, the electrode or substrate is made of a composite material made of SiC fiber and Al or Al alloy. This is a semiconductor characterized by being formed of.
た電極又は基板上に、Ｎｉ、Ｃｏ又はこれ等の合金を被
覆して半導体素子を搭載する特許請求の範囲第１項記載
の半導体。(2) The semiconductor according to claim 1, wherein a semiconductor element is mounted on an electrode or substrate made of a composite material of SiC fibers and Al or an Al alloy, coated with Ni, Co, or an alloy thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59128907A JPS617637A (en) | 1984-06-22 | 1984-06-22 | Semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59128907A JPS617637A (en) | 1984-06-22 | 1984-06-22 | Semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS617637A true JPS617637A (en) | 1986-01-14 |
Family
ID=14996307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59128907A Pending JPS617637A (en) | 1984-06-22 | 1984-06-22 | Semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS617637A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0363286A2 (en) * | 1988-09-13 | 1990-04-11 | PECHINEY RECHERCHE (Groupement d'Intérêt Economique régi par l'ordonnance du 23 Septembre 1967) | Material for electronic components and process for preparing the components |
| EP0725433A2 (en) * | 1995-02-01 | 1996-08-07 | Motorola, Inc. | leadframe and method of fabrication |
| EP1195810A1 (en) * | 2000-03-15 | 2002-04-10 | Sumitomo Electric Industries, Ltd. | Aluminum-silicon carbide semiconductor substrate and method for producing the same |
-
1984
- 1984-06-22 JP JP59128907A patent/JPS617637A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0363286A2 (en) * | 1988-09-13 | 1990-04-11 | PECHINEY RECHERCHE (Groupement d'Intérêt Economique régi par l'ordonnance du 23 Septembre 1967) | Material for electronic components and process for preparing the components |
| EP0725433A2 (en) * | 1995-02-01 | 1996-08-07 | Motorola, Inc. | leadframe and method of fabrication |
| EP0725433A3 (en) * | 1995-02-01 | 1998-03-04 | Motorola, Inc. | leadframe and method of fabrication |
| EP1195810A1 (en) * | 2000-03-15 | 2002-04-10 | Sumitomo Electric Industries, Ltd. | Aluminum-silicon carbide semiconductor substrate and method for producing the same |
| EP1195810A4 (en) * | 2000-03-15 | 2007-10-10 | Sumitomo Electric Industries | Aluminum-silicon carbide semiconductor substrate and method for producing the same |
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