JPS6175553A - Electronic part - Google Patents
Electronic partInfo
- Publication number
- JPS6175553A JPS6175553A JP59196709A JP19670984A JPS6175553A JP S6175553 A JPS6175553 A JP S6175553A JP 59196709 A JP59196709 A JP 59196709A JP 19670984 A JP19670984 A JP 19670984A JP S6175553 A JPS6175553 A JP S6175553A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead
- tip
- mounting
- fixing portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置等の面実装型の電子部品、特にリー
ドの半田濡れ性が良好な電子部品に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to surface-mounted electronic components such as semiconductor devices, and particularly to electronic components whose leads have good solder wettability.
電子機器は、機能面から高密度実装化が、実装面から軽
量化、小型化、薄型化が要請されている。Electronic devices are required to be more densely packaged from a functional standpoint, and to be lighter, smaller, and thinner from a packaging standpoint.
このため、電子機器に組み込まれる電子部品の多くは、
面実装が可能な構造に移行してきている。For this reason, many of the electronic components incorporated into electronic devices are
There is a shift towards structures that allow surface mounting.
また、電子部品の製造コスト低減のために、パッケージ
形態は＋７１料が安くかつ生産性が良好なレジンパッケ
ージが多用されている。Furthermore, in order to reduce the manufacturing cost of electronic components, resin packages are often used because they are inexpensive and have good productivity.
このような電子部品（半導体装置）の一つとして、超小
型の半導体装置、いわゆるミニモールド部品（たとえば
、ミニモールドトランジスタ）が知られている。As one such electronic component (semiconductor device), an ultra-small semiconductor device, a so-called mini-mold component (for example, a mini-mold transistor) is known.
一方、電子機器の製造コスト低減等の目的から、電子部
品の実装（搭載）の自動化が図られている。On the other hand, for the purpose of reducing manufacturing costs of electronic devices, efforts are being made to automate the mounting (mounting) of electronic components.
また、前記ミニモールドトランジスタ等の電子部品の固
定は、半田ペーストが印刷された基板上に電子部品を仮
付け（半田ペーストの表面張力によってリードの半田ペ
ーストとの接触部分が仮付けされる。）した後、半田を
リフローすることによって行われている。（なお、自動
実装技術を詳しく述べである文献の例として、工業調査
会発行［電子材料Ｊ １９７９年３月号、昭和５４年３
月１日発行、Ｐ５４〜Ｐ５８がある）。Furthermore, to fix electronic components such as the mini-mold transistors, the electronic components are temporarily attached onto a board on which solder paste is printed (the surface tension of the solder paste causes the parts of the leads that are in contact with the solder paste to be temporarily attached). This is then done by reflowing the solder. (Incidentally, as an example of a document that describes automatic mounting technology in detail, there is
Published on the 1st of the month, pages 54-58).
ところで、前記ミニモールドトランジスタは、パッケー
ジの寸法は縦、横、高さが１〜３ｍｍ程度と極めて小さ
く、パッケージの一側面から２本。By the way, the mini-mold transistor has extremely small package dimensions of about 1 to 3 mm in length, width, and height, and there are two wires from one side of the package.
他側面から１本とそれぞれ突出したリードをも含む製品
幅も３ｍｍにも満たない。また、突出したリードの幅も
狭いことから、ミニモールドトランジスタを基板に取付
ける取付は面積も小さくならざるを得ない。The product width, including one lead protruding from the other side, is less than 3 mm. In addition, since the width of the protruding leads is narrow, the installation area for attaching the mini-molded transistor to the board must also be small.
したがって、ミニモールドトランジスタの半田によるよ
り確実な固定が望まれる。Therefore, it is desired that mini-mold transistors be more securely fixed by soldering.
本発明の目的は半田の濡れ性が良好な面実装型の電子部
品を提供することにある。An object of the present invention is to provide a surface-mounted electronic component with good solder wettability.
本発明の他の目的は実装歩留りが高くできる面実装型の
電子部品を提供することにある。Another object of the present invention is to provide a surface-mounted electronic component that can achieve a high mounting yield.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明のミニモールドトランジスタは、基板
の半田ペース！司二に載置されるリード部分を先端に向
かうに従って徐々に薄＜シて先端を薄くシ、この先端の
−Ｌ面に半田ペーストが接触し易いようにすることによ
り、半田の濡れ性および表面張力作用を利用して溶融し
た半田をリード先端部に這い」−がるようにしているこ
とから、リードはノん仮に確実に固定され、ミニモール
ドトランジスタの実装の信頬度向上が達成できる。In other words, the mini-mold transistor of the present invention uses only solder paste on the board! The lead portion placed on the wire is gradually thinned toward the tip so that the solder paste can easily come into contact with the -L side of the tip, thereby improving the wettability of the solder and the surface. Since the molten solder is caused to creep onto the tip of the lead using tension, the lead is securely fixed without any temporary effect, and the reliability of mounting the mini-mold transistor can be improved.
第１図は本発明の一実施例によるミニモールドトランジ
スタの反転状態の斜視図、第２図は同じく実装状態を示
す斜視図、第３図は同じく実装された状態を示す斜視図
である。FIG. 1 is a perspective view of a mini-mold transistor according to an embodiment of the present invention in an inverted state, FIG. 2 is a perspective view of the same mounted state, and FIG. 3 is a perspective view of the same mounted state.
この実施例のミニモールドトランジスタ１は、第１図に
示されるように、プラスチック（たとえば、エポキシ樹
脂）のパッケージ２の両側から合計３本のリード３を突
出させた構造となっている。As shown in FIG. 1, the mini-mold transistor 1 of this embodiment has a structure in which a total of three leads 3 protrude from both sides of a plastic (for example, epoxy resin) package 2.
同図は、トランジスタ１の実装面４が上となるように裏
返しにした状態を示す図である。前記パッケージ２は、
縦が１．５ｍｍ、横が２．９ｍｍ。This figure shows a state in which the transistor 1 is turned over so that the mounting surface 4 faces upward. The package 2 includes:
The length is 1.5mm and the width is 2.9mm.
高さが１．１ｍｍとなっている。また、前記リード３は
パッケージ２の付は根近傍で実装面４側に折れ曲がると
ともに、その先端部分は再び外方に折れ曲がり、先端に
固定部５を形成している。リード３は幅がＱ、４ｍｍ、
厚さが０．１６ｍｍ。The height is 1.1 mm. Further, the lead 3 is bent toward the mounting surface 4 near the root of the package 2, and its tip portion is bent outward again to form a fixing portion 5 at the tip. Lead 3 has a width of Q, 4mm.
Thickness is 0.16mm.
パッケージ２の側面からの突出長さが０．５ｍｍとなっ
ている。この固定部５は実装面４と同一面となっていて
、実験時配線基板等の導体層に半田等によって接続され
る。前記固定部５のリード３部分はその先端に向かって
徐々に薄くなり濡れ促進部を形成している。すなわち、
固定部５のリード３部分ではり一部３の主面が先端に向
かうに従って徐々にその高さが低くなり、先端部分では
その厚さが、たとえば、Ｑ、１ｍｍとなり、先鋭となっ
ている。これは、実装時、溶けた半田が固定部５の先端
の主面（−Ｊ−面）に接触し、半田の濡れ性と表面張力
によって、半田１１が固定部５の上面全域にｊＨい上が
ることを期待して形成されている。なお、前記固定部５
の薄形化はリード３の切断成型時にプレスすることによ
って同時に行われる。The protrusion length from the side surface of the package 2 is 0.5 mm. This fixing part 5 is flush with the mounting surface 4, and is connected to a conductor layer of a wiring board or the like by solder or the like during an experiment. The lead 3 portion of the fixing portion 5 gradually becomes thinner toward its tip to form a wetting promoting portion. That is,
In the lead 3 portion of the fixing portion 5, the height of the main surface of the beam portion 3 gradually decreases toward the tip, and the thickness at the tip portion is, for example, Q, 1 mm, and is sharp. This is because during mounting, the melted solder comes into contact with the main surface (-J- surface) of the tip of the fixed part 5, and the solder 11 rises over the entire upper surface of the fixed part 5 due to the wettability and surface tension of the solder. It is formed with the expectation that Note that the fixing part 5
The thinning of the lead 3 is simultaneously performed by pressing when cutting and molding the lead 3.
一方、パッケージ２内に延在するリード３の内端ばそれ
ぞれ幅広となっている。そして、中央のリード３の内端
には半導体素子（チップ）６が固定されている。また、
両側のリード３の内端と前記チップ６の電極とはワイヤ
７によって接続されている。On the other hand, the inner ends of the leads 3 extending inside the package 2 are each wide. A semiconductor element (chip) 6 is fixed to the inner end of the central lead 3. Also,
The inner ends of the leads 3 on both sides and the electrodes of the chip 6 are connected by wires 7.
つぎに、このようなトランジスタ１の実装構造、特に半
田リフローによる実装について説明する。Next, the mounting structure of such a transistor 1, particularly the mounting by solder reflow, will be explained.
第２図で示されるように、最初に基板（配線基板）８が
用意される。この基板８はセラミック等の絶縁体によっ
て形成されているとともに、表面（主面）には導電体か
らなる配線層９が設けられている。また、この基板８の
配線層９の所定部分には、半田ペースト１０がスクリー
ン印刷等によって印刷されている。As shown in FIG. 2, a substrate (wiring board) 8 is first prepared. This substrate 8 is formed of an insulator such as ceramic, and a wiring layer 9 made of a conductor is provided on the front surface (principal surface). Further, a solder paste 10 is printed on a predetermined portion of the wiring layer 9 of the substrate 8 by screen printing or the like.
そこで、ミニモールドトランジスタ１は自動搭載装置等
によって基板８の所定位置に載置される（第２図参照）
。この際、リード３の固定部５は半田ペースト１０上に
載ることから、半田ペースト１０の表面張力によって仮
り固定される。 つぎに、基板８に印刷された半田ペー
スト１０はリフローによって一時的に溶かされる。この
際、固定部５の先端は薄くかつ半田ペースト１０に直接
接触していることから、半田ペースト１０が熔けると、
固定部５はミニモールドトランジスタ１の自重で半田１
１中に埋まるようになり、半田１１は固定部５の上面に
接触する。また、半田１１はその濡れ性と表面張力によ
って固定部５の略全域に這い」−がる。この結果、第３
図で示されるように、ミニモールドトランジスタ１のリ
ード３の固定部５部分は半田１１に被われるようにして
配線層９に確実に固定される。この半田の濡れ性の再現
性は高く、実装の歩留りは高い。Therefore, the mini-mold transistor 1 is placed at a predetermined position on the substrate 8 by an automatic mounting device or the like (see Fig. 2).
. At this time, since the fixing part 5 of the lead 3 is placed on the solder paste 10, it is temporarily fixed by the surface tension of the solder paste 10. Next, the solder paste 10 printed on the substrate 8 is temporarily melted by reflow. At this time, since the tip of the fixing part 5 is thin and in direct contact with the solder paste 10, when the solder paste 10 melts,
The fixing part 5 is soldered 1 by the weight of the mini mold transistor 1.
1, and the solder 11 comes into contact with the upper surface of the fixing part 5. Moreover, the solder 11 creeps over substantially the entire area of the fixing portion 5 due to its wettability and surface tension. As a result, the third
As shown in the figure, the fixing portion 5 of the lead 3 of the mini-mold transistor 1 is covered with solder 11 and is securely fixed to the wiring layer 9. The reproducibility of this solder's wettability is high, and the mounting yield is high.
（１）本発明によれば、リード３の先端の固定部５には
濡れ促進部が形成されていることから、半田の濡れ性が
良好となり、半田１１を介して固定部５を配線層９に強
固にかつ再現性良く接合することができるという効果が
得られる。(1) According to the present invention, since the wetting promoting part is formed in the fixed part 5 at the tip of the lead 3, the wettability of the solder is good, and the fixed part 5 is connected to the wiring layer 9 through the solder 11. The effect is that it can be joined firmly and with good reproducibility.
（２＋ １記（ｌｌから、本発明によれば半田ペースト
１０がリード３の厚さと同じ程度と薄くなっても、リー
ド３の固定部５は確実に配線層９に固定できるという効
果が得られる。(2+ From 1), according to the present invention, even if the solder paste 10 becomes as thin as the thickness of the leads 3, the fixing portion 5 of the lead 3 can be reliably fixed to the wiring layer 9. .
（３）上記（２）から実装において半田ペースト１０を
薄くできることから、電子部品の実装密度を高めても、
隣り合う電子部品における半田接合部分間の半田による
連結現象（ブリッジ）も発生し難くなり、実装密度向上
が達成できるという効果が得られる。(3) From (2) above, since the solder paste 10 can be made thinner during mounting, even if the mounting density of electronic components is increased,
The solder connection phenomenon (bridging) between solder joint portions of adjacent electronic components is also less likely to occur, resulting in the effect that an improvement in packaging density can be achieved.
（４）上記ｆ１）〜（３）により、本発明によれば、実
装歩留りの向上、使用半田量の軽減、高密度実装化によ
って、電子部品の実装コストの低減が達成できるという
相乗効果が得られる。(4) According to f1) to (3) above, according to the present invention, a synergistic effect can be achieved in that it is possible to reduce the mounting cost of electronic components by improving the mounting yield, reducing the amount of solder used, and achieving high-density mounting. It will be done.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない、たとえば、第４図で示さ
れるように、濡れ促進部はり−ド３の固定部５を先端に
向かうに従って徐々に細くして先端を鋭利とし、この鋭
利部１２が溶けた半田１１中に埋まり易いことを利用し
て固定部５の上面全域に半田１１が這い上がるようにし
ても、前記実施例同様な効果が得られる。なお、この実
施例は、パッケージ２の四辺からそれぞれリード３を突
出させる構造の半導体装置１３に本発明を適用した例で
ある。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, as shown in FIG. 4, the fixing part 5 of the wetting promoting part beam 3 is made gradually thinner toward the tip so that the tip is sharp, and this sharp part 12 is formed in the melted solder 11. Even if the solder 11 is made to creep up over the entire upper surface of the fixing part 5 by taking advantage of the fact that the solder 11 is easily buried in the solder, the same effect as in the above embodiment can be obtained. Note that this embodiment is an example in which the present invention is applied to a semiconductor device 13 having a structure in which leads 3 protrude from each of the four sides of a package 2.
また、濡れ促進部としての構造は、表面張力現象と接触
角現象による毛管現象（毛細管現象）を利用した構造が
考えられる。すなわち、第５図は固定部５に溝状の切り
欠き１４を設けた例であり、第６図は固定部５にスリッ
ト（スリット孔）１５を設Ｌ３た例であり、第７図は固
定部５に円形の孔１６を３個設けた例である。これら切
り欠き１４．スリット１５．孔１６はいずれも毛管現象
によって半田１１を固定部５の−に面に吸い上げること
ができるような寸法となっている。また、第５図〜第７
図で示す矢印は半田１１の吸い上がり状態を示すもので
ある。Further, the structure of the wetting promoting portion may be a structure that utilizes capillary phenomenon due to surface tension phenomenon and contact angle phenomenon. That is, FIG. 5 shows an example in which a groove-shaped notch 14 is provided in the fixed part 5, FIG. 6 shows an example in which a slit (slit hole) 15 is provided in the fixed part 5, and FIG. This is an example in which three circular holes 16 are provided in the portion 5. These notches14. Slit 15. Each of the holes 16 has a size that allows the solder 11 to be sucked up to the negative surface of the fixing portion 5 by capillary action. Also, Figures 5 to 7
The arrows shown in the figure indicate the state in which the solder 11 is sucked up.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるトランジスタおよび
ＩＣ０面実装技術に適用した場合について説明したが、
それに限定されるものではなく、他の構造の面実装型の
電子部品に適用できる。In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the field of application which is the background of the invention, which is the transistor and IC0 surface mounting technology.
The present invention is not limited thereto, and can be applied to surface-mounted electronic components having other structures.
本発明は少なくとも面実装構造の物品の固定技術には通
用できる。The present invention is applicable at least to techniques for fixing articles of surface mount structure.
第１図は本発明の一実施例によるミニモールドトランジ
スタの反転状態の斜視図、
第２図は同じく実装状態を示す斜視図、第３図は同じく
実装された状態を示す斜視図、第４図は本発明の他の実
施例による半導体装置の斜視図、
第５図は本発明の他の実施例によるリードの先端部分を
示す斜視図、
第６図は本発明の他の実施例によるリードの先端部分を
示す斜視図、
第７図は本発明の他の実施例によるリードの先端部分を
示す斜視図である。
１・・・ミニモールドトランジスタ、２・・・パッケー
ジ、３・・・リード、４・・・実装面、５・・・固定部
、６・・・チップ、７・・・ワイヤ、８・・・基板、９
・・・配線層、１０・・・半田ペースト、１１・・・半
田、１２・・・鋭利部、１３・・・半導体装置、１４・
・・切り欠き、１５・・・スリット、１６・・・孔。
第 ６ 図
第 ７ 図FIG. 1 is a perspective view of a mini-mold transistor according to an embodiment of the present invention in an inverted state, FIG. 2 is a perspective view of the same mounted state, FIG. 3 is a perspective view of the same mounted state, and FIG. 5 is a perspective view of a semiconductor device according to another embodiment of the present invention, FIG. 5 is a perspective view showing the tip end of a lead according to another embodiment of the present invention, and FIG. 6 is a perspective view of a lead according to another embodiment of the present invention. FIG. 7 is a perspective view showing the tip end of a lead according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Mini mold transistor, 2... Package, 3... Lead, 4... Mounting surface, 5... Fixing part, 6... Chip, 7... Wire, 8... board, 9
... Wiring layer, 10... Solder paste, 11... Solder, 12... Sharp part, 13... Semiconductor device, 14...
...notch, 15...slit, 16...hole. Figure 6 Figure 7
Claims (1)
リードと、からなる面実装型の電子部品であって、前記
リードの先端部分には半田の濡れ性の良い濡れ促進部を
有していることを特徴とする電子部品。 ２、前記濡れ促進部はリード先端部分が先端に向かうに
従って徐々に薄くなる構造によって形成されていること
を特徴とする特許請求の範囲第１項記載の電子部品。 ３、前記濡れ促進部はリード先端部分が先端に向かうに
従って徐々に細くなる構造によって形成されていること
を特徴とする特許請求の範囲第１項記載の電子部品。 ４、前記濡れ促進部は毛管現象による半田吸い上げが可
能なスリット、切り欠き、孔によって形成されているこ
とを特徴とする特許請求の範囲第１項記載の電子部品。[Scope of Claims] 1. A surface-mounted electronic component consisting of a package and a lead protruding from the circumferential surface of the package, the lead having a wetting promoting part with good solder wettability at the tip end of the lead. An electronic component characterized by having the following. 2. The electronic component according to claim 1, wherein the wetting promoting portion is formed with a structure in which the tip portion of the lead becomes gradually thinner toward the tip. 3. The electronic component according to claim 1, wherein the wetting promoting portion is formed with a structure in which the tip portion of the lead gradually becomes thinner toward the tip. 4. The electronic component according to claim 1, wherein the wetting promoting portion is formed by a slit, notch, or hole that allows solder to be sucked up by capillary action.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59196709A JPS6175553A (en) | 1984-09-21 | 1984-09-21 | Electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59196709A JPS6175553A (en) | 1984-09-21 | 1984-09-21 | Electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6175553A true JPS6175553A (en) | 1986-04-17 |
Family
ID=16362280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59196709A Pending JPS6175553A (en) | 1984-09-21 | 1984-09-21 | Electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6175553A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4920074A (en) * | 1987-02-25 | 1990-04-24 | Hitachi, Ltd. | Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof |
| JPH02152243A (en) * | 1988-12-02 | 1990-06-12 | Rohm Co Ltd | Semiconductor device |
| EP0794560A3 (en) * | 1996-03-08 | 1998-03-18 | Nec Corporation | Production method for insulated semiconductor device |
| WO2015141114A1 (en) * | 2014-03-19 | 2015-09-24 | パナソニックＩｐマネジメント株式会社 | Electronic component |
| JP2016167480A (en) * | 2015-03-09 | 2016-09-15 | 三菱電機株式会社 | Power semiconductor device |
| US11735509B2 (en) * | 2019-03-22 | 2023-08-22 | Mitsubishi Electric Corporation | Power semiconductor device and manufacturing method thereof |
-
1984
- 1984-09-21 JP JP59196709A patent/JPS6175553A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4920074A (en) * | 1987-02-25 | 1990-04-24 | Hitachi, Ltd. | Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof |
| JPH02152243A (en) * | 1988-12-02 | 1990-06-12 | Rohm Co Ltd | Semiconductor device |
| EP0794560A3 (en) * | 1996-03-08 | 1998-03-18 | Nec Corporation | Production method for insulated semiconductor device |
| KR100246694B1 (en) * | 1996-03-08 | 2000-03-15 | 가네꼬 히사시 | Production method for insulated semiconductor device |
| WO2015141114A1 (en) * | 2014-03-19 | 2015-09-24 | パナソニックＩｐマネジメント株式会社 | Electronic component |
| JP2016167480A (en) * | 2015-03-09 | 2016-09-15 | 三菱電機株式会社 | Power semiconductor device |
| US11735509B2 (en) * | 2019-03-22 | 2023-08-22 | Mitsubishi Electric Corporation | Power semiconductor device and manufacturing method thereof |
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