JPS6155186B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock information writing device for a rotary storage device such as a magnetic disk storage device or a magnetic drum storage device, and more particularly to a clock control circuit that adjusts the number of clocks applied to the writing device. .

The above-described rotary storage device includes a recording medium that is a rotating body such as a magnetic disk or a magnetic drum.
For example, when writing a servo track on a magnetic disk, a predetermined number of reference clock information is written on the disk surface in advance. Then, based on the signals read out, servo information such as dipulse and tripulse is created and written on the servo surface. In order to write a predetermined number of reference clock information on the magnetic disk at equal intervals, and to maintain the same clock interval at the boundary between the start and end of writing, that is, to make the phase step at the junction sufficiently small. Various efforts have been made in the past.

The present invention relates to a circuit provided upstream of a writing device that writes clock information to a recording medium such as a magnetic disk for each input clock, and the present invention relates to a circuit provided in a preceding stage of a writing device that writes clock information to a recording medium such as a magnetic disk for each input clock. so that the writing device can write a predetermined number of clock information per rotation of the recording medium at equal intervals on one concentric circle determined by the relative rotational movement. The invention relates to a clock control circuit that adjusts the number of clocks input to the writing device to the predetermined number. The following will explain the conventional servo track writer clock control circuit shown in FIG.

While the magnetic disk, which is the recording medium, makes one revolution,
A voltage controlled oscillator (hereinafter referred to as VCO) that oscillates at a high frequency to create a phase matching window.
The output of 101 is counted down by a counter 102 and sent to the writing device side as a reference clock. The output of the counter 102 is further
The oscillation frequency of the VCO 101 is changed by one reference clock when a predetermined number is found to be either too much or too little as a result of the comparison made by the comparator 109. By repeating the above steps, the reference clock number approaches a predetermined number. After the number of reference clocks matches a predetermined number, a window is provided before and after the end of the last clock to reduce the phase step between the start and end of writing, and the index signal at the end of writing is placed outside the window. When the index signal rises, it is assumed that the phases do not match, and the same operation is repeated, and when the index signal rises within the window, it is assumed that the phases match, and a signal is sent to the writing device to stop writing, thereby completing the writing. In the figure, 104 and 1
07 is an AND gate, 105 is a delay element, 108
is a D-type flip-flop, 111 is an up-down counter, and 112 is a DA converter. The detection window is the output of VCO101 and the counter 10.
A signal generated by passing the output of 2 through the delay element 105 and a match signal from the comparator 109 are generated through the AND gate 107. A D-type flip-flop 108, which uses this window signal as a D input and uses the rising edge of the INDEX2 signal as a clock input, determines whether the phases match.

However, this conventional clock control circuit has the following drawbacks. First, since the oscillation frequency is changed by one reference clock, it takes a considerable amount of time to reach the target predetermined number. Second, when the rotational jitter on the disk surface is large, even if the number of counters deviates slightly from the predetermined number, if the frequency of the VCO is changed, an oscillation state occurs and it becomes difficult to match the predetermined number.
Thirdly, in a configuration in which a window is provided to perform phase matching, it is difficult to achieve highly accurate phase matching.

A first object of the present invention is to provide a clock control circuit suitable for shortening the time required to adjust the number of clocks input to the writing device to the predetermined number.

A second object of the present invention is to provide a clock which does not cause an oscillation state and makes it easier for the number of output clocks to match the predetermined number when the number of output clocks of the voltage controlled oscillator deviates slightly from the predetermined number. The purpose is to provide a control circuit.

A third object of the present invention is to provide a clock control circuit having a configuration capable of performing highly accurate phase matching.

In the present invention, when the number of output clocks of the voltage controlled oscillator approaches a predetermined number, if the difference between the number of output clocks of the voltage controlled oscillator and the predetermined number is greater than or equal to a predetermined first threshold value, the voltage controlled oscillator The oscillation frequency correction width is made large, and the oscillation frequency correction width is made small when the oscillation frequency correction width is less than the first threshold value and greater than or equal to the second threshold value (which is smaller than the first threshold value). The present invention has achieved the object of shortening the time required to adjust the number of output clocks of the voltage controlled oscillator to the predetermined number.

Further, the present invention achieves the second object by not correcting the oscillation frequency of the voltage controlled oscillator to prevent an oscillation state from occurring when the difference is less than the second threshold, and This makes it easier for the number to match the predetermined number.

Furthermore, the present invention generates a sawtooth wave synchronized with a signal having a period that is a natural number multiple of the period of the output clock of the voltage controlled oscillator and a natural number fraction of the time required for the recording medium to complete one revolution. The above-mentioned highly accurate phase matching is achieved by comparing the sawtooth wave levels at the start and end points. By comparing analog signals with sawtooth wave levels in this way, quantum errors that always accompany phase matching control using digital circuits in conventional clock control circuits can be eliminated.
Highly accurate phase matching is possible.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention. In the following explanation, a magnetic disk will be used as an example of a recording medium.
It can be similarly applied to magnetic drums and the like. First, write only one pulse around the disk surface,
The data is read out and each control signal as shown in FIG. 3 is generated. In FIG. 2, 201 is a voltage controlled oscillator (VCO), and 204 is a gate (AND gate) that opens when INDEX2 is at the "1" level.
The output of the VCO 201 is sent to a write amplifier in the writing device through a signal line 205 as a reference clock a, while being entered into a counter 207 and counted. When the disk surface makes one revolution, the difference between the counted number of clocks and a predetermined number appears in the output of the counter 207. A threshold circuit 208 determines whether the output of 207 is greater than or equal to a first threshold, from less than the first threshold to greater than or equal to a second threshold, or less than the second threshold. If it is above the first threshold, the threshold pulse generation circuit 211 generates pulses by the number of the first threshold according to the signal given to 209 at the rising edge of INDEX3', and if the counted number of clocks is too large, is the output of the UP DOWN counter 213 through the signal line 227 and the OR gate 231.
When connecting to the DOWN terminal, signal line 226
and is sent to the UP terminal through the OR gate 230. The difference between the number of clocks and a predetermined number is a first threshold (e.g.
16) and above a second threshold (for example, 4), the monostable multivibrator 212 generates one pulse by the signal given to 210 at the rising edge of INDEX3' which delayed INDEX3, If the number of clocks is too large, connect signal line 229 and
UP DOWN counter 2 through OR gate 231
If it is too small, send it to the UP terminal through the signal line 228 and OR gate 230. If the difference between the counted number of clocks and the predetermined number is less than a second threshold, no pulses are generated. When a pulse arrives at the DOWN terminal of the counter 213, the content of the UP DOWN counter 213 decreases, the output voltage of the DA converter 214 also decreases, and the oscillation frequency of the VCO 201 is lowered. Similarly, when a pulse comes to the UP terminal of counter 213,
The contents of the UP DOWN counter 213 increase and the DA
The output voltage of converter 214 also increases, and VCO2
Increase the oscillation frequency of 01. At first, when the difference between the clock number and the predetermined number is very large, it approaches the predetermined number by the number of the first threshold value, and at the next INDEX0, the counter 20
7 is cleared, counting starts again at INDEX2, and the same operation is repeated to get closer to the target. After the difference between the number of clocks and the predetermined number becomes less than the first threshold, the VCO is set so that the counter approaches the predetermined value one by one.
The oscillation frequency of 201 is modified. When the difference between the number of clocks and the predetermined number becomes less than the second threshold
Since the influence of the INDEX signal and VCO jitter becomes large, the VCO 201 is not controlled and the clock number and phase coincide by chance. In this way, the number of output clocks of the VCO is adjusted according to the number of pulses output by the pulse generator including the threshold pulse generator 211 and the monostable multivibrator 212.

In this way, in this embodiment, the difference between the counted number of reference clocks and the target value (predetermined number) is the first.
By changing the oscillation frequency of the VCO so that the number of clocks approaches the target value by the number of first threshold values only when the threshold value of This achieved a reduction in time. Also, the second drawback mentioned above is eliminated by not modifying the VCO when the difference is less than a second threshold;
This makes it easier for the number of clocks to match the target value.

The reference clock a enters the frequency dividing circuit 216 from the signal line 205. A sawtooth wave (b in FIG. 4) synchronized with the output signal of the frequency dividing circuit 216 is generated by the sawtooth wave generation circuit 217. OR gate 2
A pulse is input to the input terminal 219 of 21 at the rising edge of INDEX2, the level of the sawtooth wave at that time is sampled and held by the sample and hold circuit 218, converted into a digital signal by the AD converter 222, and the pulse is inputted at the rising edge of INDEX2'. register 223
is memorized. After the disk surface has rotated once, that is, when INDEX3 rises, the input terminal 22
A pulse enters 0, and the level of the sawtooth wave at that time is sampled and held, converted into a digital signal by the AD converter 222, and stored in the register 224 at the rise of INDEX3'. If the contents of the register 223 and register 224 are different, the comparator 225 compares them again at the next INDEX2 and INDEX3.
If the contents of the registers 223 and 224 are equal, the comparator 225 determines that the phases match, and outputs a stop signal that closes the write gate in the writing device, thereby completing the reference clock writing.

Figure 4 shows the positional relationship between reference clock a, sawtooth wave b, INDEX2 and INDEX3. In FIG. 4, the period of the sawtooth wave b is shown to be two periods of the reference clock for simplicity, but it can be made larger depending on the number of stages of the frequency dividing circuit 216. In this way, the sample-and-hold time is near the center of the sawtooth wave, so linearity is good and highly accurate phase matching can be performed. In other words, by performing phase alignment control using an analog signal having a sawtooth wave level, the quantum error that always occurs in digital circuit control in the conventional clock control circuit shown in FIG. 1 is eliminated, and highly accurate phase alignment is achieved. becomes possible.
In any case, the sawtooth wave generation circuit 217
The sawtooth wave b appearing at the output of the VCO 201 must be synchronized with a signal having a period that is a natural number multiple of the period of the output clock of the VCO 201 and a period that is a natural number fraction of the time required for one round. Also, by storing the information of the AD converter 222 in the registers 223 and 224, the levels of the two sawtooth waves can be compared after a sufficient period of time has passed since the information entered the AD converter 222. The response time of H.222 is not a problem, and a high-precision AD converter can be selected.

In this way, this embodiment regarding phase matching is performed using VCO
A sawtooth wave generator (specifically, a sawtooth wave generator) generates a sawtooth wave that is synchronized with a signal that is a natural number multiple of the period of the output clock of the disk and has a period that is one natural number of the time required for one rotation of the disk surface. (includes a frequency circuit 216 and a sawtooth wave generation circuit 217) and compares the reference clock sawtooth wave level at the start of writing with that at the end, and if they match, outputs a stop signal to end the writing. A write stop signal sending unit (specifically, this includes the sample and hold circuit 218, OR gate 221, AD converter 22)
2, registers 223, 224, and comparator 22
Contains 5. ), it is possible to eliminate the third drawback mentioned above and write a reference clock with a small phase step.

Although one embodiment of the present invention has been described above, it goes without saying that the present invention is not limited thereto and includes various modifications and changes based on the idea of the present invention.

As explained above, the present invention is configured to change the frequency correction range of the VCO in multiple stages and to compare the level of the sawtooth wave synchronized with the reference clock at the beginning and end of one cycle to perform phase matching. This has the effect of shortening the writing time and enabling highly accurate phase alignment.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional reference clock control circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a timing chart of control signals supplied to Fig. 2. 4 are diagrams showing timing charts for explaining the state of phase matching according to the present invention. 201...Voltage controlled oscillator, 204...AND
Gate, 207... Counter, 208... Threshold circuit, 211... Threshold pulse generation circuit, 212...
Monostable multivibrator, 213...Up-down counter, 214...DA converter, 21
6... Frequency dividing circuit, 217... Sawtooth wave generation circuit,
218... Sample hold circuit, 219...
Signal that becomes “1” when INDEX2 rises, 220
...Signal that becomes "1" when INDEX3 rises, 2
21...OR gate, 222...AD converter, 22
3 and 224... register, 225... comparator, 230 and 231... OR gate.

Claims (1)

[Scope of Claims] 1. The recording medium is provided upstream of a writing device that writes clock information on a recording medium for each input clock, and is determined by the rotational movement of the recording medium relative to the writing device. The number of clocks input to the writing device per rotation of the rotational movement is set as above so that the writing device can write a predetermined number of clock information at equal intervals on one concentric circle per rotation of the rotational movement. A voltage controlled oscillator that outputs the clock in a clock control circuit that adjusts the clock to a predetermined number;
The difference between the number of output clocks of the voltage controlled oscillator per rotation of the rotational motion and the predetermined number is input, and the difference is set as the first and second thresholds (however, the first threshold is the second threshold). a threshold circuit that determines the magnitude relationship with respect to the threshold value (greater than a threshold value); and when the determination result of the threshold circuit indicates a first threshold value or more, more correction is made than when the judgment result indicates a second threshold value or more and less than the first threshold value. a pulse generator that generates a pulse and does not generate a correction pulse when the pulse is less than a second threshold; and a pulse generator that is connected to the pulse generator and the voltage controlled oscillator and outputs the number of correction pulses that the pulse generator outputs. Accordingly, when the number of correction pulses is large, the oscillation frequency of the voltage controlled oscillator is corrected more than when it is small, and when the pulse generator does not output correction pulses, the oscillation frequency is 1. A clock control circuit comprising: a circuit for preventing correction from being performed. 2. Provided at the front stage of a writing device that writes clock information on a recording medium for each input clock, and arranged on one concentric circle of the recording medium determined by the relative rotational movement of the recording medium with respect to the writing device. A clock that adjusts the number of clocks input to the writing device per rotation of the rotational movement to the predetermined number so that the writing device can write a predetermined number of clock information at equal intervals per rotation of the rotational movement. In the control circuit, a voltage controlled oscillator outputting the clock;
The difference between the number of output clocks of the voltage controlled oscillator per rotation of the rotational motion and the predetermined number is input, and the difference is set as the first and second thresholds (however, the first threshold is the second threshold). a threshold circuit that determines the magnitude relationship with respect to the threshold value (greater than a threshold value); and when the determination result of the threshold circuit indicates a first threshold value or more, more correction is made than when the judgment result indicates a second threshold value or more and less than the first threshold value. a pulse generator that generates a pulse and does not generate a correction pulse when the pulse is less than a second threshold; When the number of correction pulses is large, the oscillation frequency of the voltage controlled oscillator is corrected more than when the number of correction pulses is small, and when the pulse generator does not output correction pulses, the oscillation frequency is corrected. a clock control circuit having a period that is a natural number multiple of the period of the output clock of the voltage controlled oscillator and a natural number fraction of the time required for one rotation of the rotational motion. A sawtooth wave generation section that generates a sawtooth wave in synchronization with the signal is compared with the level of the sawtooth wave at the start and end of one revolution of the rotational movement, and when both levels match, the writing device 1. A clock control circuit comprising: a write stop signal sending unit that sends a stop signal to stop a write operation.