JPS61502995A - Control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Control device This invention decodes a coded input signal and corresponds to a predetermined code. to a control device that controls the operation of a connected device according to an encoded input signal that It is related to Furthermore, the present invention decodes the telephone ring signal and A control device that electrically controls the operation of the equipment according to a coded group of sequences. It's about location.

The present invention can be applied to lighting systems, heating and cooling appliances, audible and/or visual alarm system equipment. It has found particular application in controlling the operation of various household appliances such as appliances, etc. Here, by using a telephone ring in the electrical network, the operation of such a device is Remotely enabled or disabled.

Remote control of various household appliances according to the ring of the telephone has long been known However, prior to the previous control device used to interface between the appliance and the telephone receiver, The major disadvantage of this technology's devices is that they include cumbersome and expensive control equipment, which self and others in response to input signals derived from unintended sources that attempt to activate control of the device. An example of this is J.E. Bard sales or false information. Sensitive to rigging. Previous devices such as this were designed to accept input ring signals from telephone receivers Parasitic phone rings or unintended device control shall have appropriate arrangements in place to sufficiently avoid possible false triggering of the instrument by the call. The lines are not broken.

An example of previous technology in this field is E. A. Kol. No. 3,360,777 by Represents one of the earliest attempts to provide remote control of appliances through the use of a road network. . This patent uses a series of relays and timers to transfer input signals to the output of the device. A control device for use is disclosed. Especially both the relays and timers used there. Due to the complex and cumbersome nature of it is obvious.

Additionally, this device has different relays and ties that must be used depending on each input signal. We need a combination of materials. In this way, this device realizes a decoding system. It is impractical to do so, and this device must , requires a predetermined number of inputs of a defined number of groups of continuous input signals. The essential requirements of the essential and remote control device are accepted for false triggering. It is to have a certain degree of resistance.

U.S. Pat. It is stated by No. 4. This device was described in Comb's patent as expensive and cumbersome. The traditional analog circuit elements are abandoned in favor of digital electronics, in which , the counter is controlled to count the incoming telephone ring signals in response to the occurrence of the control signal. and the output means includes an indication of the number of rings counted.

The disadvantage of this device is that it is not possible to determine the operation of the counter as stated in the Byrd patent. This results from the use of special control signals such as The start of counting is activated by the ring signal only when the control signal is not present. There is.” This feature, in addition to the true nature of the control signals, Greater use of counters and control signals in situations requiring group decoding is given a limit. The interaction between the counter and the control signal in this device is Convenient for generating an output signal indicating the number of rings counted, especially for relatively complex Preferred for generating an output signal in response to a coarsely encoded ring signal. like this In the latter application, the control means for generating the control signal is a human head.The other device is also It is based on a remote control device that uses the telephone network. This device is available in two series This is in turn counted to count the second series of ringing signals. a second series of ringing equal to a predetermined number. The instrument is activated in response to the signal. The disadvantage with this device is that the complex encoded The problem lies in the inability to decode the input ringing signal. I mean lingin The first series of coding signals is not needed to match any particular code. It is from. Furthermore, the device can recover a series of different groups of input ring sequences. are not prepared for encoding and cannot be efficiently applied to adapt as such. .

Another example is U.S. Pat. No. 430 to Gretczko I. No. 4967, which is the subject of a counter that counts countable input signals and It is directed to a device having a timer that controls the counting of the above input signals, and , after the counter reaches a predetermined number of counted signals, The connected instrument will be activated. The drawback with this device is false triggers Exists in lack of decoding to avoid ringing and activates immediately for distortion . Moreover, it is useful for controlling the decoding of input signals that are more complexly encoded. No preparations have been made yet.

Alternative devices have been proposed, but they are substantial modifications of the above quotation and their Some or all exhibit the same drawbacks as previously mentioned.

The object of the invention is here to provide a control device of the type specified, which is more efficient and economical to implement than the device described in the previous quote. .

It is a further object of the present invention to obtain relatively complexly encoded inputs of the type defined herein. To provide a control device that is easily modified or adapted to decode signals. It is.

Another object of the present invention is to provide a simple method for improving its resistance to false triggering. It is simply a matter of providing a control device that can be modified or adapted.

Another object of the invention is to provide independent control of one or more devices connected to it. The object of the present invention is to provide a control device that can be easily modified or adapted for use.

In one form, typically consists of a series of generally regularly spaced input signals. A control that executes a control connected to it in response to an encoded input signal The present invention, which pertains to an apparatus, includes the following items.

That is, (a) counting the receipt of said input signals and the magnitude of the number of said input signals counted; counting means for generating a counting signal representing the (1) after a predetermined time interval of ml has elapsed from the reception of the input signal. a timing means for generating a first time borrowing; and (C) Input of a counting signal corresponding to a predetermined magnitude and the above first time borrowing symbol. output means for controlling the operation of the above device according to the force; Here, the above first time signature is the last input signal if the subsequent input signal is received. is not received within a first time interval from then only.

According to a preferred feature of the invention, the timing means, upon receiving said input signal, reset to initial state.

According to another preferred feature of the invention, the output means include one or more logic means. one or more of the counting signals generated according to a specified code. sequentially decoding the plurality of sets and the first time signal, and implementing the control of the above device. generates an output control signal regarding the current state;

According to another advantageous characteristic of the invention, the control device is arranged such that after the occurrence of said first time borrowing At any given time, the reset means outputs the reset signal as described above. Apply to several means.

According to another preferred feature of the invention, the logic means and gate hands corresponding to different signal sets. and control means for controlling the operation of said gate means, thereby controlling said gate means. The control means sequentially decodes said set of signals and combines with said control means for output control. Achieve control signal generation.

According to another preferred feature of the invention, the gate means has a predetermined size. a series of gates each receiving an input corresponding to the above counting signal and a first time signature; and the signals gated by it according to the specified code above. the first gate corresponds to the first set of signals in the code. The subsequent gates have a counting signal of The gated signal of the final gate has a corresponding count signal and the gated signal of the final gate is the source of the output control signal. achieve life.

According to another preferred feature of the invention, the logic means are configured to control the selected operation of said first gate. Corresponding to the operation, it has an initial operating state, in which the above control means have been previously selected. Depending on the output of the gate the selected motion of the subsequent gate is determined by a second predetermined A second time signature occurs after the time interval has elapsed since the reception of the input signal, and the second the predetermined time interval is relatively longer than the first time interval, and the second time interval The interval is the time interval in which subsequent input signals are within a second time interval from the last received input signal. Occurs only if it is not received, so that the above logic means the above second time receives an input corresponding to the second time borrow, where the logical means Upon occurrence, it is reset to the initial state described above.

According to another preferred feature of the invention, the arbitrary time is the time of occurrence of said second time borrowing. It hasn't grown any further than that.

According to another preferred feature of the invention, the control device is adapted to control a defined sequence of input signals. The above coded input has a pulse generating means for generating a pulse in response to the input of the coded input. input means for receiving a force signal, wherein said pulse is applied to said input. Counting means and timing to facilitate signal counting and timing operations, respectively. applied to the means. In another form, the invention provides a defined sequence of input signals. belongs to a pulse generating means that generates an output pulse according to The above sequences corresponding to one or more input signals are delayed and sampled. ring means, wherein the delay means is configured to provide a time delay from receipt of the input signal. Later, an activation signal is output to the above-mentioned sampling means, and the above-mentioned sampling means is the presence of the input signal and the activation signal above, the time approximating the fixed period above ゛Generates the above output pulse only in response to the delay.

The invention will be better understood with reference to the following description of some embodiments. child The description has been made with reference to the accompanying drawings. here, FIG. 1 is a circuit diagram of the remote control device described in the first embodiment.

FIG. 2 is a circuit diagram of the remote control device described in the second embodiment.

FIG. 3 is a block diagram of a remote control circuitry according to a third embodiment.

FIG. 4 is a block diagram of a remote control circuitry according to a fourth embodiment.

FIG. 5 is a circuit diagram of the input stage of the remote control device described in the first embodiment. Ru.

Embodiments of the invention are directed to a remote control device operable in response to a telephone ring. ing. The functions of the device can be connected to it according to the user's requirements, one or more Electrical control of the operation of further equipment; communicates with this device via the network.

The operation of the device depends on the correct input of a defined number of groups of ring sequences. and each group is a predetermined number of ring sequences, followed by Groups are separated in time by periods that fall within a defined range.

A ring sequence is defined as a set of one or more rings, in which Then, the set is the basic ring ring of a telephone receiver as specified by the telephone network used. It forms the tone. The invention has been adopted by the Australian telephone network. This is explained by referring to the ring sequence, which has a relatively long pause period. It comprises two successive rings in relatively quick succession. However, the scope of the invention has been adopted by other telephone networks, including but not limited to those in the United States or the United Kingdom. It should be appreciated that this applies equally to ring sequences.

Now, specifically describing the first embodiment of the present invention shown in FIG. Backup 11 is connected to telephone 15 or located near it. Li The signal pickup is a magnetic pickup connected directly to the receiver circuit of the telephone. This may be an acoustic microphone placed near the telephone. ring signal The big ass 11 sends a signal to its output in response to the ringing sound of the telephone 15. to generate. The output of the ring signal pickup is connected to an amplifier and filter network 12. which in turn is connected to the input of the pulse generator logic circuit 40. Pal The pulse generator logic circuit comprises a ring pulse generator 13 and an input logic gate 14. . Ring pulse generator 13 generates each ring sequence generated by telephone 15. It is designed to generate a single ring pulse at its output for a given signal. pulse The output of generator 13 is connected to one input of logic gate 14, which logic gate It is shaped like an and gate. Feedback line 21 passes through switch 36 Output 34C of output flip-flop 33 (this will be explained later) , thereby causing logic gate 1.4 to follow the state of feedback line 21. can block or pass the ring pulse through it.

The output of gate 14 is connected directly to the reset bin of timer 18 and is also connected to the RC delay circuit. It is connected to the clock input pin of the counter 16 via a network 39 .

Timer 18 can easily generate relatively long time delays (e.g. 5 hours). , a multi-bit binary counter with a clock frequency set by the RC circuit 19. Preferably, it is a bit (for example, 14 bits). This timer counts continuously while the control device is activated by the oscillator. , three taimi The ringing output 20 is the continuation from the last set pulse received by the timer. is equal to the specified period.

The first timing output 20a is the first timing output 20a from the time of the last reset pulse received. Selected to assert the expiration of one period TI (approximately 10 seconds) . The second timing output 20b is from the time of the last reset pulse received. is selected to claim the expiration of the second period T2 (approximately 1 minute), which is greater than period TI. It's getting louder. Finally, from the time of the top pulse, the third period T3 (approximately 5 hours) The first and second periods T1 and T2 are selected to claim expiration. Each is substantially larger than the other. These periods are chosen as follows: There is. That is, T1 is the regular time interval between successive sets of ring sequences. However, the caller ends the telephone call to telephone 15, and then the number of telephone 15 is returned. less than some nominal minimum time to redial a number. T2 is the latter minimum time Long, but at least some nominal maximum amount of time a caller can redial the phone one more time. shorter. and T3 is some maximum time greater than both TI and T2; Here, the state of the output of the control device automatically returns to its original state after the initial selection of the control function. It will be reset dynamically.

The latter is defined as the timing output of the present control device. The counter 16 is preferably It is a sequential decimal counter, which depends on the received ring pulse. The sequential counter output 25 is asserted continuously.

The counter is reset at bin 24, which is connected to the second timing output 20b, output Output 31a of logic gate 31 (more on this later), and intermediate flip Connect the line connected from the output of flop 22 (which will also be discussed later) to have. The first preselected counter 25a is the first intermediate logic gate 1 7 and the second preselected counter output 25C is connected to the second It is connected to the input pin of intermediate logic gate 26.

The first timing output ZOa is connected to the other input pins of both intermediate gates 17.26 Both of these gates are in the form of an AND gate. First Araka The previously selected counter output 25a, when asserted, is counted by the counter 16. is selected according to the first number of received ring pulses received, and the second predetermined number The selected counter output 25C also corresponds to the second number of received ring pulses. are doing. In this way, the output lines from each of the intermediate logic groups) and 17.26 The assertion of either 17a or 26a is the first timing Simultaneous mastering of each input derived from counter outputs 25a, 25c with output 20a It depends on Zhang.

Intermediate flip-flop 220 set input 23 in the form of a flip-flop connected to a. The second timing output 20b and the output of the output logic gate 31 Both forces 31a are connected to the reset bin 23b of the intermediate flip-flop 22. There is. In this way, the flip-flop 22 has a first intermediate gate output 17a. Set when asserted, i.e. output 23c is asserted and the second timing output 20b or output logic gate output 31a is asserted. , that is, its output 23c is negated. Output 2 of intermediate flip-flop 22 3c is connected as one input to the output logic gate 31, and further includes an RC delay circuit. It is fed back to the reset bin 24 of the counter 16 via the network 27. subordinate Therefore, counter 16 resets immediately after the initial assertion of flip-flop output 23c. It will be cut. The output logic gate 31 in the form of an AND gate is connected to the second intermediate Its other input is obtained from logic gate output 26a. Therefore, the flip-flop output At the simultaneous assertion of power 23c and logic gate output 26a, the output logic gate flip Feedback is provided to both the drop reset bin 23b and the counter reset bin 24. Output flip 70 tube 33 which is checked and in the form of toggling mode. Toggle input 34a: Phase connected. Third tie of timer 18 along output flip It is obtained from a timing output of 200°. As referenced earlier, output flip... The flop output 34c is connected to the input logic gate 14 via the feedback line 21. connected to the power pin. double pole double throw: DPDT) Integrated switch 35a, 351 of switch array 36 ) along feedback line 21 and reset line 28, respectively. Connected to provide selective operation of the control in either mode or toggling mode. has been done.

In timing mode, switches 35a, 35b switch wires 21°28 to output Connect directly to the output of the flip-flop 34c and the reset bin 34b, respectively. It is located in

In the toggling mode, switches 35a, 35b are switched to other positions. , where line 21 is connected directly to the voltage supply line Vcc and line 28 is connected directly to the oven circuit. (The reset manual power 34b is grounded).

To facilitate manual timing of the output flip-flop 33, the voltage supply line Bush connected between Vcc and output flip-flop torque input 34a A button switch 38 is provided.

The output flip-flop output 34c forms the output control line of the control device and is connected to various It will be used in any way. In this embodiment, the slip-flop output 34c is an optical It is connected to a device controller 29 comprising a plug 30 and a triac 32.

A flip-flop output 34c is connected to the input of the optical coupler 30. Absolutely The output 30a of the optical coupler 3o placed at a distance from the It is connected to the gate conductor of the IAC 32. Triac 32 is connected to this control device. Therefore, it is connected in series to the AC power supply line of the device 27 being controlled.

Now, as shown in FIG. 5, the ring pulse generator 13 of this control device is explained in more detail. To explain, the pickup is represented by 101, and the amplifier and filter are connected at point B. 102 . A filter comprising a capacitor and a diode Rectifier stage 103 is connected to the output of network 102 and receives the output from stage 103. Included to convert the AC output signal to DC. The converted DC signal is Flip-flop 104 is clipped to J-, which is set to monostable mode where it cannot trigger. Applied following the lock input. That is, the J-pin is grounded and the K-bin is connected to the power supply. Connected to supply line. The output of flip-flop 104 to J- is connected to resistor 10 A voltage divider comprising 5a, 105b connects Q and R across the Q and reset bins. The output capacitor 106 is connected to both the voltage divider and the reset bin R. They are formed to be connected in series. Output logic in the form of an AND gate Gate 107 receives one input from the output of voltage divider 105, which is a DC signal. I have received it from The output Δ of the output logic gate 107 is the output of the ring pulse generator 13. A force is formed and applied to the input logic gate 14, as previously mentioned, and then To explain the operation of the ringing pulse generator, a direct current corresponding to the ring signal of the telephone 15 is generated. A signal is applied to the clock input of flip-flop 104 at J-.

These signals are generated in pairs, the total signal has a period of approximately 0.75 seconds, and the signal The pair has a period of about 3 seconds and the first signal of the above pair triggers the monostable/constant circuit. However, high logic (logic high) is determined by the time constant caused by the output capacitor 106 and the resistor. is the output at Q with a duration determined by That is, capacitor 1 06, the voltage generated at the reset bin R connects the flip-flop 104 to J-. Charges up in response to high logic at Q until it is sufficient to reset. That will happen. The time constant of the capacitor is such that the duration of high logic at Q flips. ・The cycle is set to be slightly longer than the period of the above-mentioned overall signal applied to the flop 104. has been established.

Therefore, the output of the gutter divider 105 is output just before the reset of Q and above the signal. at the output logic gate 1070 input during the presence of the second signal of the input pair described above. The high divider is connected to the flip-flop 104 up to the output A of the output logic gate. Let's strobe the value of the input signal. Thus, the monostable circuit is triggered at the first time. A ring pulse is generated at A only when triggered, and from the first time approximately Within 0.75 seconds the monostable input is activated.

A notable advantage of this type of ring pulse generator is the This control device can be used without modifying either side of the communication line network. Furthermore, phosphorus The triggering pulse generator has a relatively short sampling period depending on the initial triggering signal. The initial triggering signal respond to noise or stray voltage spikes at a predetermined time after erroneous generation of ring pulses is largely avoided.

In an alternative arrangement, the output of flip-flop 104 to J- is connected to an RC delay circuit. is connected across Q and the reset bin of the flip-flop, and the flip-flop ・The Q output of the flop is connected to the input of the output logic gate 107 through a differentiating network. It is formed in such a way that it can be The other inputs of the output logic gate are the same as the previous device. The power is directed to flip-flop 104. The operation of this device is similar to that of the previous device. substantially similar, here the incoming signal triggers the monostable circuit and the input signal The sampling is performed after about 0.75 seconds, and the state of the input at this point is the output theory. is strobed through a physical gate.

However, in this device, the Q output is a differentiating circuit to sample the input signal. It is used to generate strobing pulses. To be more specific, believe The first incoming signal of the signal pair triggers the monostable circuit such that the Q output is high and the Q output is low. do. The capacitor of the RC delay network charges up to about 0 from the time of the triggering signal. ．． Eventually asserts reset bin R of flip-flop 104 after 75 seconds. . A reset of the flip 70 tube returns the Q output to a high level, thereby shortening the differentiator. output a high pulse, which then outputs the input signal through the output logic gate 107. Strobe in sequence. If the input pair of signals has a period of about 0.75 seconds , the second signal of the pair is detected such that the output logic gate outputs a ring pulse. do.

Now, to explain the operation of the first embodiment of the present invention, the ringing signal from the telephone 15 is The signal is picked up by the ring signal pickup 11 and the extra noise is removed. Amplification and filtering is provided by amplifier and filter network 12 to achieve this. Li The signal corresponding to the pulse generation is input to a pulse generator logic circuit 40, where the pulse generation The input device 13 generates one ring pulse for each set of two rings, which is , depending on the state of the feedback line 21, the ring pulse is blocked or pass.

As each ring pulse passes through gate 14 it resets timer 18, which A state close to each of its binary timing outputs 20 is subsequently generated. Furthermore, the above Like the clock pulse, the ring pulse is converted to decimal through an RC delay network 39. It is input to the counter 16. In this way, as each ring pulse occurs, the timer 18 is reset repeatedly and the counter 16 counts the number of subsequent ring pulses. Ru. When a predetermined number of ring pulses are input to the counter 16, the The first counting output 25a is asserted and the number of received ring pulses is Remains active for a period corresponding to a determined number.

In addition, timer 18 receives a first timing period from the last reset ring pulse received. When the interval TI (e.g. 10 seconds) is reached, no subsequent ring pulses occur within this period. is not generated, the first timing output 20a will be asserted. . In this way, the first counting output 25a and the first timing output 20a are simultaneously activated. , the output 17a of the first intermediate logic gate 17 is asserted, thereby causing the intermediate produces an output pulse to set flip-flop 22 so that the first set of rings If the value is correctly received, the flip-flop output 23c is output to the counter 16. counter 16 is used again for further counting of ring pulses. enable you to be This process of setting up flip-flop 22 takes a few steps. At least the first period Tl (10 seconds), but from the second period T2 (for example, 1 minute) Occurs only if, for a short period of time, the phone ringing stops at the correct number of rings. let's.

If telephone 15 rings regardless of the specified number of rings, The counter 16 eventually stops counting after the final counter output is asserted, and if the If no further rings are received within one period Tl, a second timing from timer 18 output 20b is asserted and via reset power 23b intermediate flip Reset flop 22 and reset counter 16 via reset bin 24. reset, thereby initializing the device for reception of a new set of rings. socialize). In this way, the device implements a response to an invalid pair of rings. It will be qualitatively resistant.

After the first group of rings correctly activates the intermediate flip-flop 22, the call The person can redial the number on telephone 15 and receive a second group of ringing signals. This in turn passes through the ring signal pickup 11 to the pulse generator. 13 will be informed. The ring pulse generated by the pulse generator is connected to the input logic gate. is applied to counter 16 and timer 18 via port 14. As explained before Then, the ring pulse continuously resets timer 18 and increments counter 16.

The second group of rings has a predetermined number (which is different from the first group) when the second counter output 25c of the counter 16 reaches the main It is stretched. Therefore, if the ring is longer than the period TI (10 seconds) and the second counter outputs If it stops at the correct number corresponding to the force 25c, then and only then the second intermediate logic gate 26 The output 26a of will be asserted. If this output 26a is asserted, the output theory The output 31a of the logic gate 31 will therefore be asserted. Output logic gate output 31a Upon assertion, output 34c of output flip-flop 33 changes state and Additionally, counter 16 and intermediate flip-flop 22 are both reset and The controller is thus initialized for receipt of a new set of rings.

By triggering or switching off the triac 32, the output 34c therefore controls the operation of external device 37. In this way, the caller's telephone 150 Dialing numbers and preparing the correct combination of ring sequences for the control unit and the occurrence of the second ring sequence within the period T2 of the first Linda sequence. The control device can either switch on or switch off the device. I can shine.

If the second series of rings is within the second period T2 (1 minute) but is an incorrect number Then, the second intermediate logic gate output 26a is not asserted and the output logic gate output 31 a will not be subsequently asserted. Therefore, timer 18 has a second timing output. 20a increases until asserted (after period T2), which counter 16 and intermediate resets flip-flop 22, thereby making it ready for reception of a new set of rings. to initialize the device.

within the telephone network due to possible variations in the number of rings received compared to the number of rings). In order to compensate for inherent errors, the first and second counter outputs 25a, 25c, etc. The adjacent counter outputs 25a and 25d are connected to the counter via diodes. In addition to the printer outputs 25b and 25c, it is connected to each input of the intermediate logic gate 17゜26. Let's go. Thereby, the first and second counter outputs are OR gated together with the adjacent outputs. form a function. Thus within a group of rings only a defined number of rings can be used. receiving a number that probably corresponds to one more or one less than the specified number. Preparations will be made for. This type of tolerance is made easier by It should be noted that there are

As previously mentioned, this control device can be operated in either taming mode or toggling mode. It can be selectively switched for either operation. set to timing mode In switch 36, input logic gate 14 outputs flip-flop output 34c. controlled by the state of For example, the device controller 29 turns off the device 37. The output flip-flop 33 is in its initial state as arranged to maintain In some cases, feedback line 21 is asserted, thereby causing input logic gate 14 transmits the ring pulse to timer 18 and counter 16. Ringpa Upon receipt of the correct combination of signals, output flip-flop 33 switches its output 34c will be toggled to change state. This change in state is caused by the device controller to switch the device 37 and further to the feedback line 21. is fed back to the input gate 14 along the line, disabling the gate as shown below. cormorant.

Therefore, input logic gate 14 blocks further ring pulse input thereto; thereby allowing timer 18 to eventually tick during its first period Tl. , and then its third timing output 20c will be asserted.

The third timing output 20c is the reset bin 34 of the output flip-flop 33. 1], the output flips, thus automatically switching the device 37. off, allowing the input logic gate 14 to transmit the ring pulse again. Ru. With this controller in timing mode, the correct combination of rings By calling the telephone 15, the user of the device can call the device 3 connected to it. 7 can be switched off remotely, after which the device enters the third period T remains on for a specified period determined by the length of 3 and after its expiry, the will be automatically switched off. While the device remains on, the control setting automatically disables itself from receiving any further ring pulses. to With switch 36 set in Gering mode, input logic gate 14 is always is enabled along the feedback line 21 and therefore applied thereto. All ring pulses occurring will be communicated to timer 18 and counter 16. this mode, the third timing output 20c of the output flip-flop 33 It can also be seen that it has no effect on the condition. Thus the output flip-flop The phone 33 continuously performs a toggling function and receives links received by the telephone 15. It changes its state with each correctly encoded group of signals.

A second embodiment of the invention is substantially similar to the first embodiment, and is now described in ringtones. The input step of the controller receives the ringing signal and generates a ring pulse for it. The page is the same. Referring to Figure 2, the generated ring pulse is input from A. A is input to the logic gate 51, and A corresponds to the output of the pulse generator as in the first embodiment. I am responding. The input logic gate 51 is connected as in the previous embodiment, here The other input 52 is connected to the output of the output flip-flop 70 via a switch 72. It is led from cuff 1c. Similarly, the input gate 51 changes to the state of its other input 52. It either blocks or passes the incoming ring pulse accordingly. input game The output of gate 51 is likewise connected to reset pin 53 of timer 54 and R It is connected to a clock input 58 of a counter 59 via a C delay network 57.

As in the previous embodiment, timer 54 is a multi-bit decimal counter that does not oscillate. the frequency is determined by the RC circuit 56. determined. Again, the three timing outputs 55a, 55b, 55c are timer 5 4, which corresponds to each of the three periods explained in the first example. I am responding.

Counter 59 again has a sequential counter output 60. It is a decimal counter. corresponds to a specified number of counted input ring pulses One counter output is connected to an intermediate logic gate 63.

As shown in FIG. 2, the counter output 60a indicates that the input gate is The counter output 60b is connected to the input of the gate 63b, and as follows, the counter output 60b is connected to the input of the gate 63b. followed by.

The second input of the intermediate logic gate 63 is all the first timing output 55a of the timer 54. It is obtained from. Furthermore, the timing output 55a is clocked by another RC delay network. The reset pin 62 of the counter 59 is connected to the reset pin 62 of the counter 59 . 3rd to intermediate logic gate 63 The human power is derived from an intermediate counter 67, which will now be explained.

Intermediate counter 67 is the same as counter 59, which is a sequential decimal counter. It is. However, the intermediate counter can receive its clock from any intermediate logic gate output 64. The clock input is received at the clock input bin 68. Furthermore, the subsequent counter output 69a, 69b are the respective subsequent intermediate logical groups) 63a.

63b and the last selected output following the counter output 69b. Counter output 63c is directly connected to toggle input cuff 1a of output flip-flop 70. It is continued.

The counter 59 outputs the second timing output 55b1 of the timer 54 and the intermediate logic gate. timing output 64, or alternatively the first timing output 55a (described above). It has a line from the offset to its reset pin 62, thus the counter is reset to 0 on assertion of any line in or after some delay time. .

In addition to supplying the intermediate counter by connecting to the reset input 66, A reset pulse is also supplied to the controller 67.

Output flip-flop 70 takes a form similar to that for the first embodiment. , here it is connected to the third timing output 55c of timer 54. has a reset input cuff 1b, and its output cuff 1c is connected to the device controller B. This in turn drives the triac or relay (not shown). Therefore, the operation of the external device is controlled. Furthermore, a DPDT switch 72 of a similar form is , in the previously mentioned timing mode or toggling mode. Enables selection of location behavior. Similarly, the button switch 73 is To facilitate manual operation of the output circuit of this device, the power supply Vcc and output flip It is included between the flop cuffs 1a. Now, let us explain the operation of the second embodiment. , according to the first embodiment, the ring pulse is received by the input logic gate 51 at A and is blocked or passed depending on the state of input 52. input 52 is asserted (this may be due to the device being set to toggling mode or depending on the initialized stage of the timing mode), the ring pulse is input to the reset input of timer 54, as well as the male side with a small delay. 54 will be reset upon receipt of each ring pulse generated. Thus, When a series of ring pulses is received, timer 54 determines when the ring pulse is There is a period T1 . There is T2 Otherwise, it will be reset continuously until it stops at T3.

Counter 59 indicates that the assertion of the counter output is for counter 59 during that period. One counter at a time during the sequence corresponds to the ordinal number of the ring pulse input. Asserts the printer output 60. In both embodiments described so far, the decimal counter has been used for ring pulse counting means that require a pulse count. Therefore, up to 10 input It is possible to count only the counting pulses, but a counter with a suitable decoding circuit It is possible to cascade additional decimal counters so that any number of ring Lux can also be counted.

Upon counting the first series of ring pulses, the first counter output 60a would be asserted if the corresponding number of pulses were input to counter 59. If received Within the first period TI (for example, 10 seconds) from the time of the last ring pulse If consecutive ring pulses are not received, the first timing output 55a is asserted. It will be done. Intermediate counter 67 responds to the O clock input received at clock input 68. Accordingly, its first counter output 69a is initialized to be asserted. Seake Since it is a digital decimal counter, all other counter outputs 69 are negated. Good morning. Therefore, denying reception of the first series of ring pulses, the first intermediate gate 6 Prepare 3a again. During the event, the first intermediate logic game) 63a is the intermediate counter If the last ring pulse received is selected by the output 69a, the first counter If output 60a is asserted, then only then gate output 64a will be output at the first timing. upon receipt of a strobing pulse from output 55a. write and the first intermediate gate output 64a is the same as the first intermediate gate output 64a. It may be asserted only if it is sometimes active.

The delay circuit network 65 is configured such that the first intermediate logic game (63a) is activated by the first timing output. It is asserted by the counter reset manual 62 until after it has been strobed. The second timing output 55a functions to delay the reception of the first timing output 55a.

Subsequently, the counter 59 receives the delayed first timing output 55a or the intermediate timing output 55a. will be reset to 0 by the action of boot output 64a. Furthermore, the first intermediate gate The assertion of force 64a clocks intermediate counter 67 by clock input 68, which The subsequent second counter output 69b is asserted, thereby causing the second intermediate logic Prepare the gate 63b.

Now, before the second period T2 expires, a ring pulse is requested, otherwise When the second timing output 55b is asserted, it thus sets the intermediate counter 67 to zero. The second counter output 69b is reset to return the first and second implementations. It should be evaluated in both cases that the second series of ring pulses is within the second period T2. , the timer is reset again and a second series of ring pulses It is counted by a counter 59. If the second series of input ring pulses If it stops at the number corresponding to the assertion of the counter output 60b, then the second intermediate game)-63b is strobed after the first period ゛r1 by assertion of the first timing output 55a. Let's go. The second intermediate gate output 64b is therefore asserted and thus the intermediate counter clock to assert its next counter output 69c. Furthermore, the first tab The timing output 55a or the second intermediate gate output 64b is asserted by the counter 59. is reset to return to 0.

In this embodiment, at the assertion of the third counter output 69c, the output flip-flop 70 is toggled, thereby generating a control signal to the flip 70 protrusion cuff 1c. However, this may be utilized in the manner described in the previous embodiment.

It is clear from this example and the previous example that the incorrect number of ring pulses is arbitrary. is to be counted by a counter at the stage of , and thus the intermediate counter will not be clocked. Therefore, the first 2 timing output 55b asserts that this entire device is activated after the second period T2 has expired. Let's reset it eventually.

is the ring sequence requested to be entered by the user of this control. The number of groups of instances is two. However, this number increases the number of intermediate circuit stages on each side. It may be easily extended in both circuits by increasing the miscellaneousness. In the first embodiment, this The trigger signal is clocked continuously according to the group of ring sequences. By simply adding more intermediate logic gates and intermediate flip-flops to Therefore, it can be done.

This increase in device size can be overcome in the second embodiment, where the final count is An intermediate logic gate is further connected such that the output of the output flip-flop is connected to the output flip-flop input cuff 1a. All that is required is to introduce the counter output 63 and connect the subsequent intermediate counter output 69. is necessary. Easily count groups of input ring sequences larger than 10 To achieve this, an additional intermediate counter may be cascaded to the primary intermediate counter. but, Appropriate decoding circuitry would be required to complete this device.

A third embodiment of the invention is directed to a remote control network, each for its remote control. each has its own code and each has its own code and each has the type of control described in any of the previous embodiments. It is possible to control the operation of a large number of external devices connected to the output of the device .

With particular reference to FIG. 3, the input stage of the controller is as described in the first and second embodiments. 81 as explained above. The input stage 81 includes the previously mentioned link ring signal pickup and condition circuit, ring pulse generator and logic circuit, and timer and a Callan circuit.

The intermediate stage of the control device is designated 82 and is similar to the related embodiment previously described. Therefore, it includes intermediate logic circuits and intermediate flip-flops or counters. .

A series of intermediate stages are provided, each with a corresponding output flip-flop. 83 and a device controller 84.

Each intermediate stage 82 receives a separately encoded input ring sequence from a device controller. A corresponding intermediate stage 8 via a troller 84 and an output flip-flop 83 from input stage 81 to operate or toggle separate devices connected to designed to independently decode a group of derived input ring sequences. There is.

To explain the operation of this embodiment in more detail, input stage 81 is connected to a telephone (not shown). receive a ring signal from (not) and respond accordingly as described in the previous example Start the timer and counter circuits. Receiving a series of separately encoded input codes In this case, one or more correspondingly encoded intermediate stages 82 Decode the input code and output flip-flop 83 connected to it in this way. The input stage 81 is connected to the input stage 81 so as to be toggled to the input stage 81. Output slip 70 pieces The controllers 83 sequentially apply the modified output signals to the corresponding device controllers 84. , which continues the operation of the corresponding device connected to it as described in the previous embodiment. Let's change it.

As in each of the previous embodiments, after the expiration of the second period T2, the motion spikes. - When a mode is selected, the entire network is reset, thus ensuring that the caller is not encoded. This allows us to initialize a series of rounds of the ring sequence, which is Change a previously selected device back to its primitive state or select a specified code. Let's similarly change the behavior of other devices depending on our choices. Similarly, various devices The encoded input signal is controlled by the controller operating in the the corresponding control device of the previously selected device until the third timing period T3 expires. It will be blocked by the position.

The fourth embodiment is directed towards improved remote control circuitry as described in the third embodiment. This depends on the number of intermediate stages installed and the clarity connected to them. As above, the remote control circuitry connects the corresponding output flip-flops 93a, 9 3b, 93c with three different intermediate stages 92a, 92b, 92c It has an input stage 91 connected to.

The output of each output flip-flop 93 is the input signal of decoder/demultiplexer 95. It is connected to the data selection bin 96a. In this example, the decoder/demultiplexer The plexer is a 3-wire to 8-wire type, where the three data selection bins 96a are eight output lines 96c, each of which is decoded to select one of the output lines 96c of the associated device controller. It is connected to the troller 94 and external equipment (not shown).

A fourth timing period 97 is taken from a timer within input stage 91, which 4 asserted by the expiration of timing period T4, and timing period T4 is received. is arbitrarily selected to correspond to a period of about 5 minutes from the last input ring pulse. child The timing output 97 of is decoded only if the fourth timing output 97 is asserted. The decoder/demultiplexer can decode the selected bin 96a of input data. It is connected to the enable bin 96b of the device/demultiplexer 95.

Thus, in operation the output of output flip-flop 93 is The multiplexer 95 forms a defined code for decoding and therefore selects link to a particular flip-flop so that the operation of device 94 is changed. By entering the correct combination of groups in the grouping sequence, the caller can It is required to set the output of flip-flop 93.

After the last flip-flop is set to the desired state, the timer starts the timing period. After the expiration of interval T4, the fourth timing output 97 is eventually asserted, thereby causing the decoder/ Enables demultiplexer 95 and thus selects device controller 9 4 may be activated to change the operation of the device connected to it.

Actually, it is connected to the output line corresponding to the input data selection of the output flip-flop. The device controller and associated devices that have been (no output flip-flops are set before this) Note that it is not desired to be in its initialized state, which is e.g. 000. Should. Because the timer still claims its fourth timing output, This is because the decoder/demultiplexer is activated in this way. Thus, revenge ZN- It would be possible to control devices associated with one device controller.

According to a fifth embodiment of the invention, the remote control device is responsive to receiving the correct set of rings. It is integrated with a means for giving a confirmation signal at the same time. Such measures must be decided in advance. for a period of time (e.g., 5 minutes) when the called telephone has the option to lift the telephone handset. ° that allows for greater communication during the time of solenoid activation. Enables the called telephone to generate a promised tone signal for the talker. Ru.

Now, discussing the advantages of the present invention, first of all, it activates the device connected to it. False or erroneous triggering of this control device to the extent that it stops triggering separately within specified times to control the operation of such equipment connected to this Multiple groups of numbered ring sequences should be entered This is extremely difficult due to the demands. Therefore, if the device is remotely controlled If so, it is essential to know the correct combination of ring sequences.

The present invention is directed to a group that performs control of devices with greater safety in this manner. easily adapted to cover any number of input groups and input ring sequences within It is used. Furthermore, the ring generated by the telephone receiver at the location of the control device the number of ring tones heard by the caller in relation to the number n of the sequence; Two or more differences within a group to account for possible errors in numbers. This device is easy to operate in the network of external devices connected to it. Each has its own group of ring signals for its control. Requesting a combination.

In this way, device control is controlled by a ring sequence that corresponds only to that particular device. are activated independently by ringing a group's own code ( or not triggered).

To facilitate the selection or control of a large number of external devices connected to a single control device. It is possible to use various decoding techniques on the output of the device for this purpose.

An important feature of the invention is a variable long delay timer that automatically turns off the device. A single integrated circuit that performs all of the timer's timing functions with high precision, including It is recruitment.

Other important features are the 10-ring design, which provides easy adaptation of multiple ring sequences. A single circuit combined with intermediate stages of circuitry to decode multiple ring sequences up to This is the adoption of integrated circuits.

In this way, complex control networks with single timer and counter circuits can be operated. It is possible.

As explained above, either the timing mode or the toggling mode The selection operation of the present control device is prepared in either of these cases.

In addition, push button switches can be used without the need to apply a ringing signal to the unit. Equipped with a function to manually change the state of the controller's output using a switch. Ru.

It is understood that the scope of the invention need not be limited to the specific embodiments described herein. should be evaluated.

In particular, the intermediate flip-flop described here is Any convenient method that can recognize the input assertion need not be limited to It may also include storage or memory elements and The output is kept active in the above recognition. For example, an intermediate memory element would be a capacitor with a time constant long enough to receive its charging input, and The charge is applied at least for a time corresponding to the second period T2 described in this embodiment. Let's keep it.

Similarly, the output flip-flop can be any suitable memory that facilitates the generation of the output signal. It will contain a latching element. In fact, in the very simple device of the invention, In accordance with the suitable embodiments described herein, the output signal is a second width flip-flop. could be obtained directly from the top or intermediate counter.

The present invention does not have a timing mode as described here, but a ring sequence. One specified code of the device always activates the device connected to the device and - Another specified code of the sequence always includes an embodiment that does not activate the device. It should also be appreciated that the invention can be arranged without departing from the scope of the present invention. It is. In this way, you can optionally check whether the device is activated or not. allows the caller to repeatedly generate a specified code a number of times.

Again, without departing from the scope of the invention, books located remotely from the telephone receiver may be used. It is possible to have a control device, where the ring signal is e.g. Any method such as an AC mains connection, a radio or microwave link, or an optical coupling means. It may be carried to the device by any suitable transmission medium.

Furthermore, the present invention is suitable for applications where activation of the device is provided only by the telephone network. It should be appreciated that it is not limited to specific uses. For example, this control device Any type of communication whose activation is performed only on the input of a defined encoded signal. It may also be used in communication systems. Thus, the clock speed of the timer is Enables equipment operation in high frequency environments for lane decoding and sequential signal applications. It will be easily adjusted to make it easier.

Furthermore, the scope of the invention is limited to the particular types of counters and timers described herein. Although not specified here, e.g. separate independent timers can be used for the various types described here. It should be appreciated that the generation of the time signal will be controlled.

Tokuga Showa 61-502995 (15) summons international search report ANNEX To THE INTERNATIONAL 5EARCHREP ORT　0NPant　Document US 4006316 IIs 3936617 LIS 4001708 U S 4081130

Claims (1)

[Claims] 1. 11. A control device for effecting control of a device connected thereto in response to an encoded input signal, which usually consists of a series of substantially regularly spaced input signals, the control device comprising: (a) said input signals; (b) a first predetermined time interval elapses since receipt of the input signal; (c) timing means for generating a first time signal after said first time signal; and (c) inputting a count signal having a predetermined magnitude and corresponding to said first time signal. output means for controlling the operation of said device in response to said first time signal, said first time signal being the last input signal received if a subsequent input signal is received; A control device that is generated only if the power signal is not received within a first time interval from the power signal. 2. 2. A control device according to claim 1, wherein said timing means is reset to an initial state upon receiving said input signal. 3. The output means includes one or more logic means which output one or more sets of the generated count signal and the first time signal according to a defined code. 3. A control device according to claim 1 or 2, wherein the control device continuously decodes the signals and generates output control signals in connection therewith for carrying out the control of said device. 4. Said controller controls said meter at any time after the occurrence of said first time signal. including a reset means for resetting several means, where the above reset means A control device according to any one of the preceding claims, which applies a counter signal to the counting means. Place. 5. the logic means having defined codes corresponding to at least two of said sets of signals, and comprising gating means corresponding to different sets of signals and control means for controlling the operation of said gating means; According to claims 3 and 4, said gating means successively decode said set of signals and in combination with said control means effectuate the generation of an output control signal. A control device according to any of the scopes. Said gating means comprises a series of gates each receiving an input corresponding to said count signal of a predetermined magnitude and said first time signal, whereby said gated signal has a predetermined code. is generated at the output of the gate according to a gate has a count signal corresponding to a first set of signals in the code, and a subsequent gate has a count signal corresponding to a successive set or set of sets of signals in the code; The generated signal is within the scope of the claim that performs the generation of the output control signal. 5. The control device according to item 5. 7. The above logic means is in an initial operating state in response to the selected operation of the first gate. , where the control means described above continues depending on the output of the previously selected gate. 7. The control device according to claim 6, wherein the control device continuously provides the selected operation of the gate. 8. The above timing means is arranged such that the second predetermined time interval is the reception of the input signal. generating a second time signal after an elapse of time since the input, said second predetermined time interval being relatively longer than said first time interval, and said second time signal If and only if a signal is not received within the second time interval from the last input signal received, then and only then the second time signal is generated, thereby satisfying the above argument. 8. The control device of claim 7, wherein the control means receives an input corresponding to said second time signal, wherein said logic means is reset to said initial state upon occurrence of said second time signal. 9. Any time mentioned above does not extend beyond the time of occurrence of the second time signal mentioned above. 9. The control device according to items 4 and 8. 10. 4. The control device according to claim 4, wherein said reset signal is generated in response to generation of said first time signal. 11. 10. The control device according to claim 9, wherein said reset signal is generated in response to generation of said second time signal. 12. The control means described above includes an intermediate counting means, the gate output providing a clock input to it, in which subsequent gates provide a gated signal to the selected gate. In this case, claims 6 and 7 are selected successively by the output of said intermediate means. and a control device according to any of the preceding claims. 13. 13. A control device according to claim 12, wherein said gated signal of the final gate clocks said intermediate counting means, said intermediate counting means continuously carrying out the generation of said output control signal. 14. The above control means includes storage means, whereby the gate of the selected gate is Claims 6 and 7, wherein the signal is accumulated by said accumulation means for a predetermined accumulation time, and the subsequent gate is selected for the duration of said accumulation time. and the control device according to any one of paragraphs 2 and 7 to 11. 15. Said accumulation time corresponds to said second predetermined time interval. The control device according to claim 8 and 14. 16. 16. A control device according to claim 14 or 15, wherein said storage means is a flip-flop. 17. 16. The control device according to claim 14 or 15, wherein the storage means is a capacitor. 18. Said timing means generates a further time signal after a predetermined further time interval has elapsed from receipt of the input signal, said predetermined further time interval being substantially less than said first time interval. longer, and even more time sensitive than above. The signal is generated only if a subsequent input signal is not received within said further time interval from the last input signal received, where said further time signal is for altering the control of said device. The control device according to any one of the preceding claims, wherein a voltage is applied to the output means. 19. 19. A control device according to claims 8 and 18, wherein said further time interval is relatively longer than said second time interval. 20. The above output means includes switching means for generating the above output signal. A control device according to claim 3 or any one of the preceding claims. 21. Said switching means receives an input corresponding to said further time signal, wherein said switching means receives said control signal in said further time signal generation. The control device according to claims 3, 18 and 19, which is switched to change the number. 22. 22. A control device according to claim 20 or 21, wherein said switching means is a flip-flop. 23. The control device according to any of the preceding claims, wherein the control device includes device control means for controlling the device. 24. 24. The control device according to claim 3, wherein the device control means executes control of the device according to an output control signal. 25. The device control means as described above includes a decoding means having an input corresponding to one or more of the output control signals, whereby the series of the device controls according to the encoded input defined by the output control signal. Controlled Claims Paragraph 3 and and the control device according to item 23 or 24. 26. The timing means described above generates a strobing time signal after a predetermined strobing time interval has elapsed from receipt of the input signal; The traversing time interval is relatively substantially longer than the first time interval, and Claim 25, wherein said strobing time signal is generated conditional on the generation of said first time signal, wherein said strobing time signal is strobed in response to said strobing time signal to perform said decoding means and its operations. Control device as described. 27. 27. A control device according to any of claims 23 and 24 to 26, wherein said device control means comprises remote control of said device. 28. The said control device includes input means for receiving said encoded input signal having pulse generating means for generating pulses in response to input of a defined sequence of input signals, wherein said pulses are Counting operation and timing of the above input signals A control device according to any of the preceding claims, wherein the control device is applied to the counting means and the timing means to facilitate each of the counting operations. 29. 29. The control device of claim 28, wherein said defined sequence corresponds to receipt of one or more input signals within a fixed period of time. 30. Said control device is tied to said counting means for receiving said input signal. including input gating means for effectively impeding operation of the The input gating means described above is controlled according to one or more parameters. A control device according to any of the claims below. 31. Control device according to claims 3 and 30, wherein one parameter corresponds to the state of said output control signal. 32. A control device according to any of the preceding claims, wherein said encoded input signal is derived from a telephone network. 33. The control device according to any of the preceding claims, wherein the control device includes signal confirmation means for generating a confirmation signal when control of the device is executed. 34. Said pulse generating means comprises delay means and sampling means, whereby said delay means operates said sampling wander means after a time delay from receipt of the input signal. outputting an activation signal to the stage, and said sampling means outputs an activation signal to said input signal and said activation signal. 30. A control device according to claim 29, wherein said pulse is generated only in response to the presence of a sexualization signal, a time delay approximating said fixed period. 35. The delay means comprises a charging means including a triggerable monostable multivibrator and a capacitor in response to a received input signal; Activated by constant multivibrator triggering, the monostable multivibrator charges the capacitor at least to a threshold voltage, which causes the monostable multivibrator to reset and charge. 35. The control device according to claim 34, wherein the voltage means generates the activation signal at or near the time when the capacitor reaches the threshold voltage. 36. 36. A control device according to claim 35, wherein said charging means includes an integrating circuit for integrating the non-inverting output of said monostable multivibrator in order to carry out generation of said activation signal. 37. The above charging means includes a voltage divider in series with the above capacitor; 37. A control device according to claim 36, whereby said activation signal is generated at the output of a voltage divider. 38. Claim 35, wherein said charging means includes a differentiating circuit for differentiating the inverted output of said monostable multivibrator in order to carry out generation of said activation signal. On-board control device. 39. Said sampling means comprises a logic gate having one input corresponding to said input signal and another input corresponding to said activation signal, such that said pulse is generated between said input signal and said activation signal. 39. The control device according to any one of claims 34 to 38, which is generated in response to simultaneous presence. 40. Claims 4 and 5 where the above-mentioned resetting means is timing means. and the control device according to any of the other claims accordingly. 41. A control device according to any of the preceding claims, wherein said timing means is a single integrated counter. 42. 42. A control device according to claim 41, wherein said counter is a binary counter. 43. Said counting means includes decoding means for providing an output count signal in response to said generated count signal corresponding to a number of predetermined discrete magnitudes. A control device according to any of the requirements. 44. A control device according to any of the preceding claims, wherein said counting means is a single integrated counter. 45. Any of the preceding claims wherein said counting means is a decimal counter. A control device according to any of the above. 46. A pulse generator that generates output pulses in response to a defined sequence of input signals. wherein the above-mentioned sequence comprises delay means and sampling means, wherein the above-mentioned sequence corresponds to receiving one or more input signals within a fixed period of time; The delay means outputs the activation signal to the sampling means after a time delay from receipt of the input signal, and the sampling means outputs the activation signal to the sampling means after a time delay from receipt of the input signal, and the sampling means outputs the activation signal between the input signal and the activation signal for a fixed period of time. Approximate above only by the presence of a time delay Pulse generating means for generating the output pulses described below. 47. The delay means comprises a charging means including a triggerable monostable multivibrator and a capacitor in response to a received input signal; It is activated by the triggering of a constant multivibrator, which causes a monostable The multivibrator charges the above capacitor to at least the threshold voltage and The above threshold voltage resets the monostable multivibrator, and the charging means rises at or near the same time as the capacitor reaches the above threshold voltage. 47. The pulse generating means according to claim 46, which generates the activation signal as described above. 48. 48. The pulse generating means according to claim 47, wherein said charging means includes an integrating circuit that integrates a non-inverting output of said monostable multivibrator that performs generation of said activation signal. 49. The above charging means includes a voltage divider in series with the above capacitor; 49. The pulse generating means of claim 48, whereby said activation signal is generated at the output of the voltage divider. 50. Claim 47, wherein said charging means includes a differentiating circuit for differentiating the inverted output of said monostable multivibrator in order to carry out generation of said activation signal. Pulse generation means included. 51. Said sampling means comprises a logic gate having one input corresponding to said input signal and another input corresponding to said activation signal, such that said output pulse is a coexistence of said input signal and said activation signal. The pulse generating means according to any one of claims 46 to 50, which is generated in accordance with the above.