JPS6150471A - Television receiver - Google Patents

Abstract

PURPOSE:To attain ease of confirmation of the content of all channels with simple constitution by using a single tuner to display plural pictures in one screen at the same time. CONSTITUTION:In case of picture display of plural channels (ch), channel selection of the Ach is commanded at first from a control signal output section 24 to a channel selection section 11, the video signal is stored in a memory 15 through a buffer memory control section 14 via a video amplifier section 3, a video signal processing section 4, an MPX12 and an A/D converter 13. Then when one field's share is stored in a memory 15, a signal line of the memory 15 is connected to a bus of a CPU20 to attain the transfer from the memory 15 ot the display memory 18. On the other hand, a control signal output section 24 controls switching sections 6, 7 by the command of the CPU20 to switch the CRT10 to a memory 18. Thus, the video signal transmitted from the memory 15 to the memory 17 is displayed on the CRT10. This is applied to the next Ch.

Description

[Detailed description of the invention] Technical fields> The present invention relates to a television receiver.

<Prior art> Currently, in the state of television broadcasting in Japan, there are at most 9 channels of broadcasting stations that can be received in a region. Therefore, if images from about 9 channels can be displayed simultaneously on one screen, the viewers can It is convenient because you can check the broadcast contents of all broadcast channels in the area at a glance, and there is no need to repeatedly switch channels to select the channel you want to watch.

In response to this, television receivers have been proposed in which images of two channels, main and sub, are displayed simultaneously on one screen of a CRT (for example, Japanese Patent Laid-Open No. 49-2
No. 419 Publication), some of which have been put into practical use).

However, the above-mentioned television receiver can only display two channels of images on one screen, and if you want to display more images, you have to install an additional tuner for the number of images. There is a drawback that it is practically impossible to simultaneously display images of all broadcast channels in one area on one screen using the conventional method.

<Objective of the Invention> The present invention has been made in view of the above-mentioned problems, and is capable of simultaneously displaying a plurality of images on one screen using a single tuner. Without complicating or increasing the size of the receiver configuration, you can easily check the contents of all broadcast channels in the area, eliminate the hassle of channel selection, and display the desired channel on the screen as necessary. An object of the present invention is to display an image as a still image to facilitate confirmation of a changing image.

A tuning section for switching reception channels of the tuner, a buffer memory for storing one image of the video signal of one of the selected channels, and one part of each video signal of one or more selected channels. a display memory that stores images; a buffer memory control unit that controls writing to the buffer 7 memory based on a synchronization signal in received radio waves;
a display memory control section that generates a television synchronization signal based on clock pulses and controls reading and writing to the display memory in synchronization with the television synchronization signal; a video signal switching section and a synchronization signal switching section that switch the inputs to the two sections to the display memory side, a central control section that controls each section, and an operation that is operated to select the display mode of the CRT. When displaying images of multiple channels on one screen, the central control unit stores the video signal for one image in a buffer memory during the display scanning period of the synchronization signal of the channel, and then During the vertical retrace period of the television synchronization signal, the contents of the buffer 7 memory are transferred to the display memory, and the stored contents are read out and sent to the CRT during the display scanning period of the television synchronization signal, and are also read out during the display scanning period of the television synchronization signal. When displaying a still image of one channel, one image of the video signal is directly stored in the display memory based on the synchronization signal of the received radio wave during the display scanning period of the synchronization signal of the channel, and the stored contents are It is configured so that it is read out and sent to the CRT during the display scanning period of the television synchronization signal.

In addition, when displaying images from multiple channels on one screen, it is necessary to determine the presence or absence of audio multiplex broadcasting for each channel and its type, that is, the audio mode of stereo broadcasting, bilingual broadcasting, or monaural broadcasting. The type of audio mode is displayed simultaneously on the image of each channel.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a block diagram of the entire television receiver of the present invention, which consists of a main circuit section A and an image processing circuit section B. As shown in FIG.

The main body circuit portion A includes an antenna 1, a single tuner 2, a video amplification section 3, a video signal processing section 4, a synchronization signal processing section 5, a video output section 8, a deflection output section 9, and a C 'RT
10 and a deflection coil 10a. A synchronization signal switching section 7 is interposed in each of the two.

The image processing circuit section B also includes a tuning section 11 that switches the reception channel of the tuner 2, a multiplexer 12 that introduces the video signal from the video signal processing section 4, and a converter that converts the analog signal from the multiplexer 12 into a digital signal. An A/D converter 13, a buffer memory 15 that temporarily stores one field of a video signal, a buffer memory control unit 14 that controls writing to the buffer memory 15 based on a synchronization signal of received radio waves, and a clock. A reference oscillation circuit 16 that generates pulses and multiple channels (9 channels in this embodiment) to be displayed on the CRTlo.
1 field of each video signal, or 1
a display memory 18 that stores one frame of a video signal of a channel; and a display memory control that generates a television synchronization signal from the clock pulse and controls reading and writing to the display memory 18 using the television synchronization signal. 17, and a D/A that converts the digital video signal read from the display memory 18 into an analog quantity.
A converter 19, a central control unit (CPU) 20 that controls the buffer memory control unit 14, display memory control unit 17, video signal processing unit 6, synchronization signal switching unit 7, etc., and a program for the central control unit 20. A program ROM 21 that stores , a work RAM 22, and a CRTIO (7)
an operation unit 23 operated to select a display mode;
A control signal output section 24 that operates the channel selection section 11, the video signal switching section 6, and the synchronization signal switching section 7 based on a signal from the central control section 20.
There is.

Furthermore, in order to display the type of audio multiplex broadcast on each channel screen when multiple channels are displayed on one screen, an audio IF detection section 39 and an audio multiplex decoder 40 are provided. .

In the above configuration, by operating the operation unit 23 and selecting the display mode, the desired one channel image is displayed on the CRTIO screen like a normal television receiver, and also on the CRT10 screen. Images of multiple channels (in this embodiment, images of 9 channels) may be displayed simultaneously, or an image of one channel may be displayed as a still image on the CRTIO screen. The operation in each mode will be explained while explaining the more detailed configuration of the display memory control section 17.

(b) Normal display mode The television radio waves of the channel received by the antenna l and selected by the tuner 2 are amplified by the video amplification unit 3,
The video signal processing section 4 and the synchronization signal processing section 5 are manually operated. In the video signal processing section 4, the video signal is separated into a luminance signal (Y signal) and two color difference signals (RY signal, BY signal). On the other hand, the synchronization signal processing section 5 separates the received signal into a horizontal synchronization signal and a vertical synchronization signal and outputs the separated signals. At this time, in the video signal switching unit 6, the switching piece 6C has only one contact 6.
a, and the output of the video signal processing section 4 is input to the video output section 8. In the other synchronizing signal switching section 7, the switching piece 7C is connected to the contact 7a, and the output of the synchronizing signal processing section 5 is input to the deflection output section 9. In this way, a video signal is input to the main body of the CRT 1, and a synchronization signal is input to the deflection coil 10a of the CRT 1, so that a desired 1-channel image is displayed on the CRTIO screen. .

(b) Image display of multiple channels (-multi-mode) When multi-mode is set in the operation section 23, the CPU
20 operates to control each part to display multiple images in the CRTIO image 1f+i, but the CPU
20, the output section 24 instructs the tuning section 11 to select one of the plurality of channels, for example, the A channel. Channel A is selected at .

The video signal of the A channel is input to the multiplexer 12 via the video amplifier 3 and the video signal processor 4. The multiplexer 12 separates the Y signal and R-Y signal from among the video signals.
The signal and the BY signal are sequentially extracted and sent to the A/D converter 13. The A/D converter 13 converts analog signals into digital signals. The video signal thus converted into a digital quantity is sent to the buffer memory control unit 14.
The data is stored in the buffer 7 memory 15 at the timing of the buffer memory control unit 14.

FIG. 2 is a block diagram showing the internal configuration of the buffer memory control section 14, and FIG. 3 is a time chart of the buffer memory control section 14 in multi mode. 7. The operation when controlling writing to memory will be explained. The command signal sb) from the CPU 20 is input to the write period detection section 26. The write period detection section 26 receives a synchronization signal of the received radio wave, and generates a write pulse having a display scanning period length of one field from the synchronization signal of the received radio wave in response to the command signal sb. To be precise, the write pulse has a length from the fall of the vertical synchronization signal of the received radio wave to the rise of the next vertical synchronization signal υ, as shown in FIG. While the write pulse is rising, the write row counter 27 and the write column counter 28 count the clock pulses from the reference oscillation circuit 16 and output address signals in the row direction and column direction, respectively. In the changeover switches 30.31 connected to the row counter 27 and write column counter 28, respectively, the changeover pieces 30c, 31c are connected to the contacts 30a,
31a, so the write row counter 3
0, and each output of the write column counter 31 is supplied to the buffer memory 15, and the storage address of the Banoff 7 memory 15 is specified.On the other hand, the video signal stored in the Banoff 7 memory 15 is supplied to the 4 multiplexer 12,
It is supplied through the A/D converter 13 and the changeover switch 29. In the multiplexer 12, three contacts 12a, 12b+ are connected in synchronization with the horizontal synchronization signal of the received radio wave.
12c are closed sequentially, so Y every horizontal opening period.
The signal, RY signal, and BY signal are sequentially sent to the A/D converter 13, A/D converted, and stored in the buffer 1 memory 15.

When one field of the video signal of the desired channel (channel A) is stored in the backup memory 15 in this way, the operations of the write row counter 27 and the write column counter 28 are stopped, and the changeover switches 30 and 31 The switching pieces 30a, 31a are switched to other contacts 30b, 31b, and the address signal line of the buffer 1 memory 15 is connected to CP.
The data signal line of the buffer 1 memory 15 is connected to the data bus of the CPU 20 by connecting the switching piece 29c to the contact 29b of the changeover switch 29. In this state, the backup memory 15
When the storage contents of can be transferred to the display memory 18 and the display memory 18 side is in a state where the transfer is accepted, the transfer starts.0 Note that in FIG. The control unit 26 is a ternary counter.

On the other hand, the same number of storage areas are set in the display memory 18 corresponding to multiple channels (9 channels) of images to be displayed on the CRTIO, and the video signals stored in these storage areas are 5CRT1 accessed by the generated address signal and by the television synchronization signal also generated from the clock pulse.
Displayed as 0.

The operation in this case will be explained based on the block diagram of the display memory control section 17 shown in FIG. A control signal is sent from the control signal output section 24 to the video signal processing section 6 in response to a command from the CPU 20.
, is sent to the synchronization signal switching section 7, and both switching sections 6.7
The switching pieces 6c and 7c are switched to the contacts 6b and 7b, respectively, and as a result, the input terminals of the video output section 8 and the deflection output section 9 are switched to the display memory 18 side, respectively. In the display memory control unit 17, the horizontal synchronization signal generation counter 33 generates a television = 17 horizontal synchronization signal by coloring the clock pulse, and also generates a column direction address for the display memory 18 in synchronization with the television horizontal synchronization signal. Generate a signal. The vertical synchronization signal generation counter 34 generates a television vertical synchronization signal based on the television horizontal synchronization signal from the horizontal synchronization signal generation counter 33, and at the same time generates a row direction address signal for the display memory 18.

The display control circuit 35 switches the changeover switch 3 in response to the television horizontal synchronization signal and the television vertical synchronization signal.
6,37.38 are controlled. Changeover switch 36.3
7, the switching pieces 36b and 37b are connected to the contacts 36a and 3, respectively.
7a, and therefore the address signals generated by both the synchronization signal generation counters 33 and 34 are respectively supplied to the display memory 18, the display memory 18 is accessed by this address signal, and the stored contents of the display memory 18 are Read out. At this time, since the contact 38a of the changeover switch 38 is closed, the video signal read out from the display memory 18 is sent to the D/A converter 19 and converted into an analog signal, and the video signal is sent to the D/A converter 19 and converted into an analog signal. Input to output section 8. Further, the television horizontal synchronization signal generated by the horizontal synchronization signal generation counter 33,
The television vertical synchronization signal generated by the vertical synchronization signal generation counter 34 (hereinafter collectively referred to as television synchronization signal) is transmitted through the synchronization signal switching section 7 to the deflection output section 9.
Enter. During the display scanning period of these television synchronization signals, the video signals of multiple channels stored in the display memory 18 are displayed on the CRTlo, and the image of a predetermined channel among the images of multiple channels on one screen is updated and displayed. Ru.

During the vertical retrace period of the television synchronization signal, the control signals from the display control circuit 35 switch the switching pieces 36b and 37b of the changeover switches 36 and 37 to the contacts 36c and 37c, respectively, so that the address signal line of the display memory 18 is switched to the contact points 36c and 37c. CPU2
Connect to address bus 0 and select switch 38
The contact 38c1 is closed, and the data signal line of the display memory 18 is connected to the data bus of the CPU 20. This state is a state in which data transfer from the buffer 7 memory 15 is received. At this time, if the address bus of the CPU is connected to the address signal line of the buffer memory 15 on the buffer memory 15 side, and the data bus of the CPU 20 is connected to the data signal line of the buffer memory 15, then the display memory 18 and the buffer memory 15 are connected. is CPU2
Connected via 0 address bus and data bus. If connected in this way, the CPU 20 will be connected to the buffer memory 15.
The storage contents are read out from the display memory 18 and transferred to the corresponding storage area of the display memory 18. This transfer is repeated every vertical blanking period of the television synchronization signal, and when the video signal for one field of one required channel (A channel) is transferred and displayed on the CRTIO, the next channel (in this example Then, the next cycle of storing and displaying one field of the video signal of channel B is started, and the same operation as that of storing and displaying the video signal of channel A described above is repeated. One field of the video signal of channel B to
5, and then transfer it to the display memory 18,
The data is read from the display memory 18 and displayed at a predetermined location on the CRTIO screen. In addition, 1 field is stored in buffer memory 1.
5, the audio IF detection unit 39 and audio multiplex decoder 40 determine in advance whether the audio mode of the audio multiplex signal is stereo broadcast mode, bilingual broadcast mode, or monaural broadcast mode. Then, this discrimination output is connected to the data bus of the CPU 20. Then, when image data is transferred from the Nokunofa memory 15 to the display memory 18, a channel number display signal is specified in color according to the type of audio mode of each channel based on the output signals from the program ROM 21 and the audio multiplex decoder 40. As a result, as shown in Figure 5, on the CRTIO screen, the channel corresponding to each channel is displayed in the upper right corner of each image of the nine channels A, B, C...I. The channel numbers are displayed together, and each channel number is colored according to the audio mode at that time.For example, stereo broadcasting is displayed in yellow, bilingual broadcasting is in red, and monaural broadcasting is in 77 colors. Ru.

(・C Still image display (still mode) operation section 23
When the still mode is selected, the tuning in the tuner 2 is fixed to any one channel (channel D in this example) by a command from the CPU 20. Also CPU
A command signal Sa is output from 20 and the buffer memory control section 1
The still image control section 25 outputs a signal corresponding to the command signal Sa to the writing period detection section 26. In response to this, the write period detection unit 2
6 generates a write pulse having a length of two display scanning periods of received radio waves of a predetermined channel (D channel) as shown in the time chart of FIG. This write pulse is exactly the length from the fall of the vertical synchronization signal of the received radio wave to the rise of the second vertical synchronization signal, and this write pulse is the length of the image for one frame)
Signals can be written. write·
The clock response is sent to a horizontal synchronizing signal generation counter 33 and a vertical synchronizing signal generation counter 34 of the display memory control section 17.

The write pulse is also sent to the changeover switch 36.37 of the display memory control unit 7, and in the changeover switch 36.37, the changeover pieces 36b, 37b are switched to the contacts 36a, 37a. Therefore, the address signal is supplied to the display memory 18 while the write pulse is rising, that is, during the two display scanning periods of the synchronization signal of the received radio wave. On the other hand, on the buffer 1 memory 15 side, multiplexer 1
2 switches the contacts in a predetermined order as shown in FIG. That is, during the first display scanning period of the received radio wave, the contact 12a is closed and only the Y signal is introduced, and during the second display scanning period, two contacts 12b are introduced every horizontal open period.

12c are alternately closed, and the RY signal and the BY signal are alternately introduced. After these video signals are converted into digital signals by the A/D converter 13, the changeover switch 29
The display memory control section 17 is connected to the display memory control section 17 through the display memory control section 17, so that the video signal sent from the buffer memory control section 14 side is input to the data signal line of the display memory 18. This display memory 1
8 already receives an address signal synchronized with the display scanning period of the received radio wave, so one frame of the video signal of a predetermined channel is stored in a predetermined storage area by addressing the address signal. Ru.

The operation of reading out the video signal for one frame stored in the display memory 18 and displaying it on the CRTIO is the same as in the case of (b) multi mode, and the video signal switching unit 6
, respective switching pieces 6C+7c of the synchronization signal switching section 7
switches to the contacts 6b and 7b, thereby switching the input terminals of the video output section 8 and the deflection output section 9 to the display memory 18 side.

In the display memory control section 17, a horizontal synchronization signal generation counter 33 generates a television horizontal synchronization signal and a column direction address signal for the display memory 18 synchronized with the television horizontal synchronization signal. Further, the vertical synchronization signal generation counter 34 receives the television vertical synchronization signal and the display memory 18.
generates a row direction address signal for At this time, the changeover switches 36 and 37 are controlled by the display control circuit 35, so that the changeover pieces 36b and 37b are connected to the contacts 36a and 37b, and the television horizontal synchronization signal and the television vertical synchronization signal are respectively stored in the display memory. Supplied to 18,
The display memory 18 is accessed by this television synchronization signal, and the stored contents of the display memory 18 are read out.

Further, the contact 38a of the changeover switch 38 is closed, and the video signal read out from the display memory 18 is then sent to the D/A converter 19, converted into an analog signal, and output as a video signal through the video signal switching section 6. Part 8
Enter. Further, the television synchronization signal is inputted to the deflection output section 9 through the synchronization signal switching section 7. As a result, one predetermined channel (
D channel) video signal is displayed on the CRTIO.

After this, the stored contents of the display memory 18 are not updated and the same stored contents are continuously read out and displayed, so that the image of a predetermined channel (D channel) as shown in the block diagram of FIG. 7 is displayed on the CRTIO in a static state. Served.

<Effects of the Invention> As described above, according to the present invention, images of multiple channels are simultaneously displayed on the CRT screen by switching the operation unit to multi-mode (multiple image display).
Viewers are convenient because they can instantly check the broadcast content of multiple channels when desired, and can easily select the broadcast they want to watch without having to perform troublesome channel operations.

In addition, after the video signal is temporarily stored in the Vanofa memory, the stored contents are sequentially transferred to the display memory by the CPU and then transferred to the CRT.
Since the image is displayed on the CRT screen, the image on the CRT screen is continuously updated, a smooth image is obtained, and the visual effect is excellent.

Furthermore, according to the present invention, when the operation unit is switched to multi-mode, the current audio mode of each channel is displayed together with the images of multiple channels, so it is possible to determine which channel is currently performing audio multiplex broadcasting. You can instantly check whether the broadcast is in stereo or bilingual.

In addition, since a single tuner for normal reception is used as is, the same number of channels as for normal reception can be received and displayed simultaneously without the need to set new reception channels for multi-mode. It is possible,
Easy to use with no set operations required, and easy to configure.
It can be implemented in existing television receivers.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of its buffer memory control section, Fig. 3 is a time chart showing storage operation in multi mode, and Fig. 4 is a display memory. A block diagram of the control unit, Fig. 5 is a configuration diagram of a CRT screen in multi mode, Fig. 6 is a time chart showing memory operation in still mode, and Fig. 7 is a CRT screen diagram in still mode.
It is a block diagram of an RT screen. 2 Tuner, 6... Video signal switching section, 7 Synchronous signal switching section, 10... CRT, 11... Tuning selection
1 part, 14...Buffer memory control unit, 1
5--Nokura memory, 17... Display memory control unit, 18... Display memory, 20... Central control unit (CPU
), 23・Operation unit, 40・Audio multiplex decoder

Claims (1)

[Claims] 1. Switch channels at regular intervals using a single tuner, store the video signals of each channel, read out the stored video signals sequentially, display images of multiple channels on one screen, or display images of multiple channels on one screen. A television receiver that displays a still image of any one channel, comprising a tuning section that switches the receiving channel of the tuner, and a buffer memory that stores one image of the video signal of the selected channel. , an audio multiplex decoder unit that determines the audio mode of the audio multiplex signal of any of the selected channels; a display memory that stores one image of each video signal of the selected channel or channels; and a receiver. a buffer memory control unit that controls writing to the buffer memory based on a synchronization signal in radio waves; and a buffer memory control unit that generates a television synchronization signal based on a clock pulse and writes to the display memory in synchronization with the television synchronization signal. a display memory control section that controls reading; a video signal switching section and a synchronization signal switching section that are located before a video output section to a CRT and a deflection output section and switch inputs to the two sections to the display memory side, respectively;
The central control unit includes a central control unit that controls each of the units, and an operation unit that is operated to select the display mode of the CRT, and when displaying images of multiple channels on one screen, the central control unit After storing the video signal for one image in the buffer memory during the display scanning period of the synchronization signal, the contents of the buffer memory are transferred to the display memory during the vertical retrace period of the television synchronization signal, and the stored contents are transferred to the display memory. The audio mode information determined by the audio multiplex decoder section during this display scanning period is also read out and sent to the CRT during the display scanning period of the synchronization signal.
A television receiver characterized in that the type of audio mode corresponding to each channel can be displayed on each screen of a plurality of channels.